Mitsubishi MH4V6445BXJJ-5, MH4V6445BXJJ-5S, MH4V6445BXJJ-6, MH4V6445BXJJ-6S Datasheet

Preliminary

Some of contents are subject to change without notice.

MITSUBISHI LSIs

MH4V6445BXJJ-5,-6,-5S,-6S

HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM

DESCRIPTION

This is family of 4194304 - word by 64 - bit dynamic RAM module. This consists of four industry standard 4Mx16 dynamic RAMs in TSOP and one industry EEPROM in TSSOP. The mounting of TSOP on a card edge dual in line package provides any application where high densities and large of quantities memory are required. This is a socket-type memory module,suitable for easy interchange of addition of modules.

FEATURES

RAS

access

time

(max.ns) MH4V6445BXJJ-5,5S MH4V6445BXJJ-6,6S

50 60

single 3.3V± 0.3V supply Low stand-by power dissipation

7.2mW- - - - - - - - - LVCMOS input level

operating power dissipation

MH4V6445BXJJ-5,5S - - - - 2016 mW(max.) MH4V6445BXJJ-6,6S - - - - 1872 mW(max.)

CAS

access

time

(max.ns)

13 15

Address

access

time

(max.ns)

25 30

OE

access

time

(max.ns)

13 15

Cycle

time

(min.ns)

84

104

APPLICATION

Main memory unit for computer,Microcomputer memory,Refresh memory for CRT.

*:Applicable to self refresh version(MH4V645/6445AXJJ-5S,-6S) only

Self refresh capability*

Self refresh current - - - - 1600 uA(max.)

All input, output LVTTL compatible and low capacitance

Utilizes industry standard 4Mx16 RAMs in TSOP and industry standard EEPROM in TSSOP.

Includes decoupling capacitor(0.22uFx4) Hyper page mode , Read-modify-write,

CAS before RAS refresh,Hidden refresh capabilities. Early-write mode,OE and W to control output buffer impedance.

ADDRESS

Part No.

MH4V6445BXJJ

Row Add. Col Add.

A0~A11 A0~A9

Refresh

/RAS only Ref,Normal R/W CBR Ref,Hidden Ref

Refresh Cycle

Normal

4096/64ms

S-Version

4096/128ms

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1

Preliminary

Some of contents are subject to change without notice.

PIN CONFIGURATION

MITSUBISHI LSIs

MH4V6445BXJJ-5,-6,-5S,-6S

HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM

PIN Number

1 3 5

7

9 11 13 15

17 19 21 22 93 94 23 24

25 26 97 98 27 28 99 100 29 30 101 102 31 32 103 104 33 34 105 106

35 36 107 108 37 38 109 110 39 40 111 112 41 42 113 114 43 44 115 116

45 46 117 118 47 48 119 120 49 50 121 122 51 52 123 124

53 54 125 126 55 56 127 128 57 58 129 130 59 60 131 132 61 62 133 134

63 64 135 136 65 66 137 138 67 68 139 140 69 70 141 142 71 72 143 144

Front side Pin Name

Vss DQ0 DQ1

DQ2 DQ3

Vcc DQ4 DQ5

DQ6 DQ7

Vss Vss DQ20 DQ52

/CAS0 /CAS4 DQ21 DQ53 /CAS1 /CAS5 DQ22 DQ54

Vcc Vcc DQ23 DQ55

A0 A3 Vcc Vcc A1 A4 A6 A7 A2 A5 A8 A11

Vss Vss Vss Vss DQ8 DQ40 A9 DQ9 DQ41 A10 NC

DQ10 DQ42 Vcc Vcc DQ11 DQ43 /CAS2 /CAS6

Vcc Vcc /CAS3 /CAS7

DQ12 DQ44 Vss Vss DQ13 DQ45 DQ24 DQ56 DQ14 DQ46 DQ25 DQ57

DQ15 DQ47 DQ26 DQ58

Vss Vss DQ27 DQ59

Reserved Reserved Vcc Vcc Reserved Reserved DQ28 DQ60

RFU FRU DQ29 DQ61

Vcc Vcc DQ30 DQ62 RFU RFU DQ31 DQ63 /WE RFU Vss Vss

/RAS0 RFU SDA SCL

NC RFU Vcc Vcc

PIN Number

2 4 6

8 10 12 14 16

18 20

Back side Pin Name

Vss DQ32 DQ33

DQ34 DQ35

Vcc DQ36 DQ37

DQ38 DQ39

PIN Number

73 74 75 76

77 79 80 81 82 83 84

85 87 89 90 91 92

95

Front side Pin Name

/OE RFU Vss Vss

Reserved Reserved Reserved Reserved

Vcc Vcc DQ16 DQ48 DQ17 DQ49 DQ18 DQ50

DQ19 DQ51

Vss Vss

RFU:Reserved Future Use NC,RFU,Reserved: NO CONNECTION

PIN Number

78

86 88

96

Back side Pin Name

NC

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2

Preliminary

Some of contents are subject to change without notice.

Block Diagram

Address

/OE

/WE

/RAS0 /CAS0

DQ0 DQ1

DQ2 DQ3 DQ4

DQ5 DQ6 DQ7

MITSUBISHI LSIs

MH4V6445BXJJ-5,-6,-5S,-6S

HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM

/CAS4

/LCAS /RAS /WE /OE

I/O1 I/O2 I/O3

I/O4 I/O5

I/O6 I/O7 I/O8

DQ32 DQ33 DQ34

DQ35 DQ36

DQ37 DQ38 DQ39

/LCAS /RAS /WE /OE

I/O1 I/O2 I/O3

I/O4 I/O5

I/O6 I/O7 I/O8

/CAS1

DQ8

DQ9 DQ10 DQ11

DQ12 DQ13 DQ14 DQ15

/CAS2

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

/CAS3

DQ24 DQ25 DQ26

DQ27 DQ28

DQ29 DQ30 DQ31

/UCAS

I/O9 I/O10 I/O11

I/O12 I/O13

I/O14 I/O15 I/O16

/LCAS /RAS /WE /OE

I/O1 I/O2 I/O3

I/O4 I/O5

I/O6 I/O7 I/O8

/UCAS

I/O9 I/O10 I/O11

I/O12 I/O13

I/O14 I/O15 I/O16

D0

D1

/CAS5

DQ40 DQ41 DQ42 DQ43

DQ44 DQ45 DQ46 DQ47

/CAS6

DQ48 DQ49 DQ50 DQ51

DQ52 DQ53 DQ54 DQ55

/CAS7

DQ56 DQ57 DQ58 DQ59

DQ60 DQ61 DQ62 DQ63

/UCAS

I/O9 I/O10 I/O11

I/O12 I/O13

I/O14 I/O15 I/O16

/LCAS /RAS /WE /OE

I/O1 I/O2 I/O3

I/O4 I/O5

I/O6 I/O7 I/O8

/UCAS

I/O9 I/O10 I/O11

I/O12 I/O13

I/O14 I/O15 I/O16

D2

D3

SERIAL PD

Vcc

C1~C4

Vss

MIT-DS-0233-0.0 24/Jul./1998

D0 to D3

SCL

MITSUBISHI

A0 A1 A2

SDA

Vss

ELECTRIC

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3

Preliminary

Some of contents are subject to change without notice.

MH4V6445BXJJ-5,-6,-5S,-6S

HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM

FUNCTION

The MH4V6445BXJJ provide, in addition to normal read, write, and read-modify-write operations,

Table 1 Input conditions for each mode

MITSUBISHI LSIs

a number of other functions, e.g., Hyper page mode, /RAS-only refresh, and delayed-write. The input conditions for each are shown in Table 1.

Operation

Read Write (Early write) Write (Delayed write)

Read-modify-write /RAS-only refresh

Hidden refresh /CAS before /RAS refresh Standby Self refresh

Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid, APD : applied, OPN : open

*MH4V6445BXJJ-5S,-6S only

*

/RAS /CAS

ACT ACT

ACT ACT ACT

NAC ACT ACT NAC DNC OPN YESDNC DNC DNC

ACT ACT

NAC ACT ACT

DNC

Inputs Input/Output

Column

/W

NAC ACT

ACT ACT

DNC NAC NAC

DNC

/OE

ACT DNC

DNC ACT

DNC ACT DNC

DNC

Row

address address

APD APD

APD APD DNC

DNC

APD APD

DNC DNC DNC

DNC

Input

OPN

VLD VLD VLD

DNC OPN DNC

DNC

Output

VLD

OPN

IVD

VLD

OPN

VLD

OPN OPN

Refresh Remark

YES YES

YES YES YES

NO

Hyper page mode identical

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4

Preliminary

Some of contents are subject to change without notice.

HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM

ABSOLUTE MAXIMUM RATINGS

Symbol Vcc VI VO IO Pd Topr Tstg

Supply voltage Input voltage Output voltage

Output current

Power dissipation

Operating temperature Storage temperature -40~ 100

Parameter Conditions

MITSUBISHI LSIs

MH4V6445BXJJ-5,-6,-5S,-6S

With respect to Vss

Ta=25°C

Ratings

-0.5~4.6

-0.5~4.6 50

4

0~ 70

Unit

V V

V

mA

W °C °C

RECOMMENDED OPERATING CONDITIONS

Symbol

Vcc Vss VIH VIL

Note 1 : All voltage values are with respect to Vss

Supply voltage Supply voltage High-level input voltage, all inputs Low-level input voltage, all inputs

ELECTRICAL CHARACTERISTICS

Symbol

VOH VOL IOZ I I

ICC1 (AV)

ICC2

ICC4(AV)

ICC6(AV)

Note 2: Current flowing into an IC is positive, out is negative. 3: Icc1 (AV), Icc4 (AV) and Icc6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate. 4: Icc1 (AV) and Icc4 (AV) are dependent on output loading. Specified values are obtained with the output open. 5: Column address can be changed once or less while /RAS=VIL and /CAS=VOH

High-level output voltage Low-level output voltage Off-state output current Input current Average supply current from Vcc operating

Supply current from Vcc , stand-by

Average supply current from Vcc Hyper-Page-Mode

Average supply current from Vcc /CAS before /RAS refresh mode

Parameter

(Note 3,4,5)

(Note 3,5)

(Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless otherwise noted) (Note 2)

-5,-5S

-6,-6S

-5,-5S

-6,-6S

-5,-5S

-6,-6S

(Ta=0~ 70°C, unless otherwise noted) (Note 1)

Limits

Min Nom Max

3.0

2.0

-0.3

IOH=-2.0mA IOL=2.0mA Q floating 0V≤VOUT≤3.6V 0V≤VIN≤3.6V, Other input pins=0V /RAS, /CAS cycling tRC=tWC=min. output open /RAS=/CAS =VIH, output open /RAS=/CAS≥Vcc -0.2, output open /RAS=VIL,/CAS cycling tPC=min. output open

/CAS before /RAS refresh cycling tRC=min. output open

3.3

0

Test conditions

3.6

0

Vcc+0.3

0.8

Unit

V

0

V V V

Min

2.4 0

-10

-40

Limits

Typ

Max

Vcc

0.4 10

40

560 520

4 2

480 440

560 520

Unit

V V

uA uA

mA

CAPACITANCE

Symbol Parameter

CI (A)

C(CAS) C(DQ) Input/Output capacitance,DATA

C(SDA) C(SCL)

MIT-DS-0233-0.0 24/Jul./1998

Input capacitance, address inputs

Input capacitance, clock inputs except CAS

Input capacitance, CAS

Input/Output capacitance,SDA Input capacitance, SCL

(Ta = 0~70°C, Vcc = 3.3V±0.3V, Vss = 0V, unless otherwise noted)

Test conditions

VI=Vss f=1MHZ Vi=25mVrms

MITSUBISHI

Limits

Min Max

Typ

40 45 25

25 12

12

Unit

pF pFCI pF pF pF pF

ELECTRIC

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5

Preliminary

Some of contents are subject to change without notice.

MITSUBISHI LSIs

MH4V6445BXJJ-5,-6,-5S,-6S

HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM

SWITCHING CHARACTERISTICS

tCAC tRAC tAA tCPA tOEA tOHC tOHR tCLZ tOEZ tWEZ tOFF tREZ tDOH

Note 6: An initial pause of 500us is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles containing a /RAS clock such as /RAS-Only refresh). Note the /RAS may be cycled during the initial pause . And any 8 /RAS or /RAS /CAS cycles are required after prolonged periods (greater than 64 ms) of /RAS inactivity before proper device operation is achieved. 7: Measured with a load circuit equivalent to 100pF. The reference levels for measuring of output signals are 2.0(VOH)and 0.8(VOL). 8: Assumes that tRCD≥tRCD(max), tASC≥tASC(max) and tCP≥tCP(max). 9: Assumes that tRCD≤tRCD(max) and tRAD≤tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table,tRAC will increase by amount that tRCD exceeds the value shown. 10: Assumes that tRAD≥tRAD(max) and tASC≤tASC(max). 11: Assumes that tCP≤tCP(max) and tASC≥tASC(max). 12: tOEZ (max), tWEZ(max), tOFF(max) and tREZ(max) defines the time at which the output achieves the high impedance state (IOUT≤ ±10uA) and is not reference to VOH(min) or VOL(max). 13: Output is disable after both /RAS and /CAS go to high

Access time from /CAS Access time from /RAS

Column address access time Access time from /CAS precharge

Access time from /OE Output hold time /CAS high Output hold time /RAS high

Output low impedance time from /CAS low Output disable time after /OE high Output disable time after /WE high

Output disable time after /CAS high Output disable time after /RAS high Output hold time from /CAS low

(Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless otherwise noted , see notes 6,14,15)

Limits

ParameterSymbol Unit

(Note 7,8)

(Note 7,9) (Note 7,10) (Note 7,11)

(Note 7)

(Note 13)

(Note 7) (Note 12) (Note 12)

(Note 12,13) (Note 12,13)

-5,-5S

Min Max

13 50 25 28

13 5 5 5

13

13 5

-6,-6S

Min Max

15 60 30 33

15 5 5 5 5

15

15 5

-7,-7S

Unit

Min Max

20

ns

70

ns

35

ns

40

ns

20

ns

5

ns ns

5

ns

20

ns

20

ns

20

ns

20

ns

5

ns

ns ns ns ns ns ns ns ns ns ns ns ns ns

TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write ,Refresh, and Hyper-Page Mode Cycles)

(Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless otherwise noted ,see notes 14,15)

Limits

ParameterSymbol

tREF tREF tRP tRCD tCRP tRPC tCPN tRAD tASR tASC tRAH tCAH tDZC tDZO tRDD tCDD tODD tT

Note 14: The timing requirements are assumed tT =2ns. 15: VIH(min) and VIL(max) are reference levels for measuring timing of input signals. 16: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access time is controlled exclusively by tCAC or tAA. . 17: tRAD(max) is specified as a reference point only. If tRAD≥tRAD(max) and tASC≤tASC(max), access time is controlled exclusively by tAA. 18: tASC(max) is specified as a reference point only. If tRCD≥tRCD(max) and tASC≥tASC(max), access time is controlled exclusively by tCAC. 19: Either tDZC or tDZO must be satisfied. 20: Either tRDD or tCDD or tODD must be satisfied. 21: tT is measured between VIH(min) and VIL(max).

Refresh cycle time Refresh cycle time(S-version ONLY) /RAS high pulse width Delay time, /RAS low to /CAS low Delay time, /CAS high to /RAS low Delay time, /RAS high to /CAS low /CAS high pulse width Column address delay time from /RAS low Row address setup time before /RAS low Column address setup time before /CAS low Row address hold time after /RAS low Column address hold time after /CAS low Delay time, data to /CAS low Delay time, data to /OE low Delay time, /RAS high to data Delay time, /CAS high to data Delay time, /OE high to data Transition time

(Note16)

(Note17)

(Note18)

(Note19) (Note19) (Note20) (Note20) (Note20) (Note21)

-5,-5S

Min Max

64

30

37

14

5 0 8

10

25

0

10

0 8 8 0

0 13 13 13

50

1

-6,-6S

Min Max

64

128128

40

45

14

5 0

10

12

30 0 0

13

10 10

0 0

15 15 15

50

1

Unit

ms ms

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

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6

Preliminary

Some of contents are subject to change without notice.

MH4V6445BXJJ-5,-6,-5S,-6S

HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM

Read and Refresh Cycles

ParameterSymbol Unit-6,-6S

tRC tRAS tCAS tCSH tRSH tRCS tRCH tRRH tRAL

tCAL tORH tOCH

Note 22: Either tRCH or tRRH must be satisfied for a read cycle.

Read cycle time /RAS low pulse width

/CAS low pulse width /CAS hold time after /RAS low

/RAS hold time after /CAS low Read Setup time after /CAS high

Read hold time after /CAS low Read hold time after /RAS low

Column address to /RAS hold time Column address to /CAS hold time

/RAS hold time after /OE low /CAS hold time after /OE low

(Note 22) (Note 22)

Write Cycle (Early Write and Delayed Write)

ParameterSymbol Unit

tWC tRAS tCAS tCSH tRSH tWCS tWCH tCWL tRWL tWP tDS tDH

Write cycle time /RAS low pulse width

/CAS low pulse width /CAS hold time after /RAS low /RAS hold time after /CAS low

Write setup time before /CAS low Write hold time after /CAS low /CAS hold time after /W low

/RAS hold time after /W low Write pulse width Data setup time before /CAS low or /W low

Data hold time after /CAS low or /W low

(Note 24)

-5,-5S

Min Max

84 50

10000

8

10000 35 13

0 0

0 25 13 13 13

-5,-5S

Min Max

84 50

10000

8

10000 35 13

0 8 8 8 8 0 8

Limits

Min Max 104 60

10000

10

10000

40

15

0 0

0 30 18 23 15

15

Limits

-6,-6S

Min Max

104

10000

60

10000

10

40 15

0 10

10 10 13 10

0 10

-7,-7S

Unit

Min Max

130

ns

70

10000

ns ns

10000

13 55

ns

20

ns

0

ns

0

ns

10

ns

35

ns ns

20

ns

20

ns

-7,-7S

Unit Min Max 130

ns

10000

70

ns

10000

ns

13

ns

55 20

ns

0

ns

13

ns

13

ns ns

13

ns

0

ns ns

13

MITSUBISHI LSIs

ns ns ns ns ns ns ns ns ns ns ns ns

Read-Write and Read-Modify-Write Cycles

Limits

ParameterSymbol

tRWC tRAS tCAS tCSH tRSH tRCS tCWD tRWD tAWD tOEH

Note 23: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT. 24:tWCS, tCWD,tRWD ,tAWD and,tCPWD are specified as reference points only. If tWCS≥tWCS(min) the cycle is an early write cycle and the DQ pins will remain high impedance throughout the entire cycle. If tCWD≥tCWD(min), tRWD≥tRWD (min), tAWD≥tAWD(min) and tCPWD≥tCPWD(min) (for Hyper page mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address. If neither of the above condition (delayed write) of the DQ (at access time and until /CAS or /OE goes back to VIH) is indeterminate.

MIT-DS-0233-0.0 24/Jul./1998

Read write/read modify write cycle time /RAS low pulse width

/CAS low pulse width /CAS hold time after /RAS low

/RAS hold time after /CAS low Read setup time before /CAS low Delay time, /CAS low to /W low

Delay time, /RAS low to /W low Delay time, address to /W low /OE hold time after /W low

(Note21)

(Note24) (Note24) (Note24)

MITSUBISHI

-5,-5S

Min Max

109

75 10000 38

10000 70 38 0 28 65 40 13

-6,-6S Min Max 133

10000

89 44

10000 82 44 0 32 77 47 15

-7,-7S

Unit

Min Max

161

ns

10000

107

ns ns

10000

57 99

ns

57

ns ns

0

ns

42 92

ns ns

57

ns

20

Unit

ns ns ns ns ns ns ns ns ns ns

ELECTRIC

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7

MITSUBISHI LSIs

Preliminary

Some of contents are subject to change without notice.

Hyper Page Mode Cycle (Read, Early Write, Read -Write, Read-Modify-Write Cycle, Read Write Mix Cycle,Hi-Z control by /OE or /WE) (Note 25)

tHPC tHPRWC tRAS tCP tCPRH tCPWD tCHOL tOEPE tWPE tHCWD tHAWD tHPWD tHCOD tHAOD tHPOD

Note 25: All previously specified timing requirements and switching characteristics are applicable to their respective Hyper page mode cycle. 26: tRAS(min) is specified as two cycles of /CAS input are performed. 27: tCP(max) is specified as a reference point only.If tCP≥tCP(max),access time is controlled exclusively by tCAC.

Hyper page mode read/write cycle time

Hyper page mode read write/read modify write cycle time

/RAS low pulse width for read write cycle /CAS high pulse width /RAS hold time after /CAS precharge Delay time, /CAS precharge to /W low

Hold time to maintain the data Hi-Z until /CAS access /OE Pulse Width (Hi-Z control) /W Pulse Width (Hi-Z control) Delay time, /CAS low to /W low after read Delay time, Address to /W low after read Delay time, /CAS precharge to /W low after read Delay time, /CAS low to /OE high after read Delay time, Address to /OE high after read Delay time, /CAS prechargeto /OE high after read

MH4V6445BXJJ-5,-6,-5S,-6S

HYPER PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM

Limits

ParameterSymbol

(Note26) (Note27)

(Note24)

-5,-5S

Min Max

20 55

100000

65

13

8 28 43

7

7 28 40 43 13 25 28

-6,-6S

Min Max

25 66

100000

77

16

10 33 50

7 7

7 32 47 50 15 30 33

-7,-7S

Unit

Min Max

30

ns

79

ns

100000

92

ns

16

10

ns

40

ns

62

ns

7

ns

7

ns

7

ns

42

ns

72

ns ns

82 20

ns

35

ns ns

40

Unit

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

/CAS before /RAS Refresh Cycle (Note 28)

Limits

ParameterSymbol Unit

tCSR tCHR tRSR tRHR

Note 28: Eight or more /CAS before /RAS cycles instead of eight /RAS cycles are necessary for proper operation of /CAS before /RAS refresh mode.

/CAS setup time before /RAS low /CAS hold time after /RAS low 10 Read setup time before /RAS low Read hold time after /RAS low 10

-5,-5S

Min Max

5 10 10

-6,-6S

Min Max

5 5

10 5

-7,-7S

Unit

Min Max

ns

15

ns ns

1510

ns

ns ns ns ns

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