Mitsubishi MH4V36AM-7, MH4V36AM-6 Datasheet

Preliminary Spec.

Some of contents are subject to change without notice.

FAST PAGE MODE 150994944-BIT ( 4194304-WORD BY 36-BIT ) DYNAMIC RAM

MITSUBISHI LSIs

MH4V36AM-6,-7

DESCRIPTION

The MH4V36AM is an 4M word by 36-bit dynamic RAM module and consists of 2 industry standard 4M X 16 dynamic RAMs in TSOP and 1 industry standard 4M X 4(4CAS) dynamic RAMs in TSOP. The ICs are mounted on both sides of one small ceracom PC board with flash gold plating and form a convenient 68-pin package.

FEATURES

CAS

access

time

(max.ns)

Address

access

(max.ns)

RAS

Type name

MH4V36AM-6

Utilizes industry standard 4M X 16 DRAMs in TSOP package and industry standard 4M X 4(4CAS) DRAM in TSOP package Single 3.3V +/- 0.3V supply Low stand-by power dissipation

5.4mW (Max) . . . . . . . . . . . . . . . . . CMOS lnput level

Low operating power dissipation

MH4V36AM - 6 . . . . . . . . . . . . . . . . 1.155W (Max)

MH4V36AM - 7 . . . . . . . . . . . . . . . . 1.100W (Max)

All inputs, output TTL compatible and low capacitance 4096 refresh cycles every 64ms (A0 ~ A11) Includes 2pcs 0.22uF decoupling capacitors

APPLICATION

Main memory unit for computers, Microcomputer memory, Refresh memory for CRT

access

time

(max.ns)

60 15 30 11015

70 20 35 13020MH4V36AM-7

time

access

time

(max.ns)

Cycle

time

(min.ns)

PIN CONFIGURATION ( TOP VIEW )

DQ1 1 DQ2 2 DQ3 3 DQ4 4 DQ5 5

Vss 6 DQ6 7 DQ7 8 DQ8 9

DQP1 10

DQ9 11

Vcc 12

DQ10 13

DQ11 14

DQ12 15 DQ13 16 DQ14 17

Vss 18 DQ15 19 DQ16 20

DQP2 21

Vcc 22 /CAS0 23 /CAS3 24

A0 25 A1 26 A2 27

Vss 28

A3 29 A4 30 A5 31

/RAS 32

A6 33

Vcc 34

68 DQP4 67 DQ32 66 DQ31 65 DQ30 64 DQ29 63 Vss 62 DQ28 61 DQ27 60 DQ26 59 DQ25 58 DQP3 57 Vcc 56 DQ24 55 DQ23 54 DQ22 53 DQ21 52 DQ20 51 Vss 50 DQ19 49 DQ18 48 DQ17 47 Vcc 46 /CAS2 45 /CAS1 44 /W 43 /OE 42 RFU(NC) 41 Vss 40 A11 39 A10 38 A9 37 A8 36 A7 35 Vcc

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Preliminary Spec.

Some of contents are subject to change without notice.

FAST PAGE MODE 150994944-BIT ( 4194304-WORD BY 36-BIT ) DYNAMIC RAM

MITSUBISHI LSIs

MH4V36AM-6,-7

FUNCTION

The MH4V36AM provide, in addition to normal read, write, and read-modify-write operations, a number of

other functions, e.g., fast page mode, CAS before RAS refresh, and delayed-write. The input conditionsfor each are shown in Table 1.

Table 1 Input conditions for each mode

Operation

Read Write Read-modify-write RAS-only refresh Hidden refresh CAS before RAS refresh Standby

Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid,APD : applied, OPN : open

RAS CAS ACT ACT ACT ACT

ACT ACT NAC

BLOCK DIAGRAM

25,26,27,29,30,31,33,36,37,38,39,40

Add /W

/OE

/CAS3

/CAS2

/CAS1

/CAS0

/RAS

/LCAS

M5M465160A

DQ9

DQ10

DQ11

DQ12

15 16

DQ13 DQ14

DQ15

DQ16

DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24

48 49 50 52 53 54 55 56

C1 to C2

0.22 uF

Inputs Input/Output

ACT ACT ACT NAC ACT ACT DNC

Add/OE /W/RAS /UCAS

W NAC ACT ACT

DNC DNC NAC DNC

ACT NAC

ACT DNC ACT DNC DNC

/LCAS /CAS1/RAS

M5M465160A

Input Output OPN VLD VLD DNC

OPN DNC DNC

VLD OPN

VLD OPN OPN

Add/OE /W/RAS /UCAS

/CAS3

/CAS2

M5M4V17500B

DQ1 DQ2 DQ3 DQ4

/CAS4

Add/OE /W

DQP4

DQP3

DQP2

DQP1

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ32

57 6 18 2847

353422 41 51 6312

Vcc Vss

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Preliminary Spec.

Some of contents are subject to change without notice.

MITSUBISHI LSIs

MH4V36AM-6,-7

FAST PAGE MODE 150994944-BIT ( 4194304-WORD BY 36-BIT ) DYNAMIC RAM

ABSOLUTE MAXIMUM RATINGS

Symbol Vcc VI V0 I0 Pd Topr Tstg

Supply voltage Input voltage

Output voltage Output current Power dissipation Operating temperature Storage temperature

RECOMMENDED OPERATING CONDITIONS

Symbol Vcc

Vss VIH VIL

Note 1 : All voltage values are with respect to Vss

Supply voltage Supply voltage High-level input voltage, all inputs Low-level input voltage, all inputs

ELECTRICAL CHARACTERISTICS (Ta=0 ~70 °C, Vcc=3.3V+/- 0.3V, Vss=0V, unless otherwise noted) (Note 2)

Symbol VOH

VOL IOZ I I

ICC1 (AV)

ICC2

ICC4(AV)

ICC6(AV)

High-level output voltage Low-level output voltage

Off-state output current Input current

Average supply current from Vcc operating

Supply current from Vcc , stand-by Average supply current

from Vcc Fast-Page-Mode

Average supply current from Vcc CAS before RAS refresh mode

Parameter Conditions Ratings Unit

-0.5 ~ 4.6

Parameter

(Note 3,4,5)

(Note 3,5)

With respect to Vss

Ta=25°C

(Ta=0 ~70 °C , unless otherwise noted) (Note 1)

Limits

Min Nom Max

3.0 0

3.0

-0.3

IOH=-2.0mA IOL=2.0mA Q floating 0V ≤ VOUT ≤ 3.6V

0V ≤ VIN ≤ 3.6V, Other inputs pins = 0V

-6

-7

-6

-7

-6

-7

RAS, CAS cycling tRC=tWC=min. output open

RAS= CAS =VIH, output open RAS= CAS≥Vcc -0.2V, output open

RAS=VIL, CAS cycling tPC=min. output open

CAS before RAS refresh cycling tRC=min. , W ≥ Vcc - 0.2 output open

3.3 0

Test conditions

3.6 0

3.6

0.8

Unit

V V V V

-0.5 ~ 4.6

-0.5 ~ 4.6 50

0 ~ 70

-40 ~ 100

Limits

Min Max

Typ

2.4 0

-10

-30

Vcc

0.4 10 30

380 305

1.4

260

240

380

365

V V V

W °C °C

Unit

V V

µA µA

Note 2: Current flowing into an IC is positive, out is negative. 3: Icc1 (AV), Icc4 (AV) and Icc6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate. 4: Icc1 (AV) and Icc4 (AV) are dependent on output loading. Specified values are obtained with the output open. 5: Column Address can be channged once or less while RAS=VIL and CAS=VIH

CAPACITANCE

Symbol Parameter Test conditions

CI (A) CI (OE)

CI (W) CI (RAS) CI (CAS) CI / O

MIT-DS-0071-0.1 Sep./19 /1996

Input capacitance, address inputs

Input capacitance, OE input Input capacitance, write control input

Input capacitance, RAS input Input capacitance, CAS input Input/Output capacitance, data ports

(Ta=0~70°C , Vcc=3.3V+/-0.3V, Vss=0V, unless otherwise noted)

VI=Vss f=1MHZ Vi=25mVrms

MITSUBISHI

Min

Limits

Typ

Max

30 36

36 36 30 25

Unit

pF pF

pF pF pF pF

ELECTRIC

( / 18 )3

Preliminary Spec.

Some of contents are subject to change without notice.

FAST PAGE MODE 150994944-BIT ( 4194304-WORD BY 36-BIT ) DYNAMIC RAM

MITSUBISHI LSIs

MH4V36AM-6,-7

SWITCHING CHARACTERISTICS

Symbol

Access time from CAS

tCAC

Access time from RAS

tRAC

Columu address access time

tAA tCPA

Access time from CAS precharge

tOEA

Access time from OE

tCLZ

Output low impedance time from CAS low Output disable time after CAS high

tOFF tOEZ

Output disable time after OE high

Note 6: An initial pause of 500 µs is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-Only refresh or CAS before RAS refresh). Note the RAS may be cycled during the initial pause . And any 8 RAS or RAS/CAS cycles are required after prolonged periods (greater than 64 ms) of RAS inactivity before proper device operation is achieved. 7: Measured with a load circuit equivalent to VOH=2.4V(IOH=-2mA)/VOL=0.4V(IOL=2mA) load 100pF. The reference levels for measuring of output signal are 2.0V(VOH) and 0.8V(VOL). 8: Assumes that tRCD≥ tRCD(max) and tASC ≥ tASC(max).

9: Assumes that tRCD ≤ tRCD(max) and tRAD ≤ tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table,

tRAC will increase by amount that tRCD exceeds the value shown. 10: Assumes that tRAD ≥ tRAD(max) and tASC ≤ tASC(max).

11: Assumes that tCP ≤ tCP(max) and tASC ≥ tASC(max). 12: tOFF(max) and tOEZ (max) defines the time at which the output achieves the high impedance state (IOUT ≤ I +/- 10 µAI) and is not reference to

VOH(min) or VOL(max).

(Ta=0~70°C , Vcc=3.3V +/-0.3V, Vss=0V, unless otherwise noted , see notes 6,13,14)

Limits

-7

15 60 30 35 15

15 15

Min Max

20 70 35 40

20 5 0 0 15

Unit

ns ns ns ns ns ns ns ns

Parameter

(Note 7,10)

(Note 7,11)

(Note 7,8) (Note 7,9)

(Note 7)

(Note 7) (Note 12) (Note 12)

-6

Min Max

5 0 0

TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write ,Refresh, and Fast-Page Mode Cycles)

(Ta=0 ~ 70 °C, Vcc=3.3V +/- 0.3V, Vss=0V, unless otherwise noted See notes 13,14)

Symbol

Refresh cycle time

tREF

RAS high pulse width

tRP

Delay time, RAS low to CAS low

tRCD tCRP

Delay time, CAS high to RAS low Delay time, RAS high to CAS low

tRPC tCPN

CAS high pulse width

Column address delay time from RAS low

tRAD tASR

Row address setup time before RAS low

Column address setup time before CAS low

tASC

Row address hold time after RAS low

tRAH tCAH

Column address hold time after CAS low

tDZC

Delay time, data to CAS low

tDZO

Delay time, data to OE low Delay time, CAS high to data

tCDD tODD

Delay time, OE high to data

Transition time

Note 13: The timing requirements are assumed tT =5ns. 14: VIH(min) and VIL(max) are reference levels for measuring timing of input signals. 15: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access

time is controlled exclusively by tCAC or tAA. tRCD(min) is specified as tRCD(min) =tRAH(min) +2tH+tASC(min). 16: tRAD(max) is specified as a reference point only. If tRAD≥ tRAD(max) and tASC ≤ tASC(max), access time is controlled exclusively by tAA. 17: tASC(max) is specified as a reference point only. If tRCD≥ tRCD(max) and tASC ≥ tASC(max), access time is controlled exclusively by tCAC. 18: Either tDZC or tDZO must be satisfied. 19: Either tCDD or tODD must be satisfied. 20: tT is measured between VIH(min) and VIL(max).

Parameter

(Note15)

(Note16)

(Note17)

(Note18) (Note18) (Note19) (Note19) (Note20)

-6

Min Max

40 20 10

0 10 15

0 15 15

Limits

-7

Min Max

64 50 20 10

0 10 15

0 15 15

Unit

ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

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Preliminary Spec.

Some of contents are subject to change without notice.

FAST PAGE MODE 150994944-BIT ( 4194304-WORD BY 36-BIT ) DYNAMIC RAM

Read and Refresh Cycles

Symbol

Read cycle time

tRC

RAS low pulse width

tRAS

CAS low pulse width

tCAS tCSH

CAS hold time after RAS low

tRSH

RAS hold time after CAS low

tRCS

Read Setup time after CAS high Read hold time after CAS low

tRCH tRRH

Read hold time after RAS low

tRAL

Column address to RAS hold time

tOCH

CAS hold time after OE low

tORH

RAS hold time after OE low

Note 21: Either tRCH or tRRH must be satisfied for a read cycle.

Parameter

(Note 21) (Note 21)

-6

Min Max

110

60 15 60 15

30 15 15

10000 10000

0 0

MITSUBISHI LSIs

MH4V36AM-6,-7

Limits

-7

Min Max

130

70 20 70 20

35 20 20

10000 10000

0 0

Unit

ns ns ns ns ns ns ns ns ns ns ns

Write Cycle (Early Write and Delayed Write)

Symbol

tWC tRAS tCAS tCSH tRSH tWCS tWCH tCWL tRWL tWP tDS tDH tOEH

Write cycle time RAS low pulse width CAS low pulse width CAS hold time after RAS low RAS hold time after CAS low Write setup time before CAS low Write hold time after CAS low CAS hold time after W low RAS hold time after W low Write pulse width Data setup time before CAS low or W low Data hold time after CAS low or W low OE hold time after W low

Parameter

(Note 23)

-6 Min Max 110

60 15 60 15

0 10 15 15 10

10 15

10000 10000

Limits

Min Max 130

-7

70 20 70 20

0 10 20 20 10

15 20

10000 10000

Unit

ns ns ns ns ns ns ns ns ns ns ns ns ns

MIT-DS-0071-0.1 Sep./19 /1996

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Preliminary Spec.

Some of contents are subject to change without notice.

MITSUBISHI LSIs

MH4V36AM-6,-7

FAST PAGE MODE 150994944-BIT ( 4194304-WORD BY 36-BIT ) DYNAMIC RAM

Read-Write and Read-Modify-Write Cycles

10000 10000

Limits

-7 Min Max 180 120

120

70 0 45 95 60 20 20 10

0 15 15

10000 10000

Unit

ns ns ns ns ns ns

ns ns ns ns ns ns ns ns

Symbol

Read write/read modify write cycle time

tRWC

RAS low pulse width

tRAS

CAS low pulse width

tCAS tCSH

CAS hold time after RAS low RAS hold time after CAS low

tRSH tRCS

Read setup time before CAS low

tCWD

Delay time, CAS low to W low

tRWD

Delay time, RAS low to W low

tAWD

Delay time, address to W low

tCWL

CAS hold time after W low

tRWL

RAS hold time after W low

tWP

Write pulse width

tDS

Data setup time before W low Data hold time after W low

tDH tOEH

OE hold time after W low

Note 22: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+5tT. 23: tWCS, tCWD,tRWD and tAWD and,tCPWD are specified as reference points only. If tWCS≥tWCS(min) the cycle is an early write cycle and the DQ pins will remain high impedance throughout the entire cycle. If tCWD≥tCWD(min), tRWD≥tRWD (min), tAWD≥tAWD(min) and tCPWD≥tCPWD(min)

(for fast page mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address.

If neither of the above condition (delayed write) of the DQ (at access time and until CAS or OE goes back to VIH ) is indeterminate.

Parameter

(Note22)

(Note23) ns (Note23) (Note23)

ÅÜ ÅÜ

ÅÖ ÅÖ

-6 Min Max 155 105

105

60 0 40 85 55 15 15 10

0 10 15

Fast-Page Mode Cycle (Read, Early Write, Read -Write, Read-Modify-Write Cycle) (Note 24)

125000

Limits

-7

Min Max

45 95

115

10 40 65

125000

Unit

ns ns ns ns ns ns

Symbol

Fast page mode read/write cycle time

tPC

Fast page mode read write/read modify write cycle time

tPRWC

RAS low pulse width for read write cycle

tRAS

CAS high pulse width

tCP

RAS hold time after CAS precharge

tCPRH tCPWD

Delay time, CAS precharge to W low

Note 24: All previously specified timing requirements and switching characteristics are applicable to their respective fast page mode cycle. 25: tRAS(min) is specified as two cycles of CAS input are performed. 26: tCP(max) is specified as a reference point only.

Parameter

(Note25) (Note26)

(Note23)

-6

Min Max

40 85

100

10 35 60

CAS before RAS Refresh Cycle (Note 27)

Symbol

CAS setup time before RAS low

tCSR tCHR

CAS hold time after RAS low

tRSR

Read setup time before RAS low

tRHR

Read hold time after RAS low

Note 27: Eight or more CAS before RAS cycles instead of eight RAS cycles are necessary for proper operation of CAS before RAS refresh mode.

Parameter

-6

Min Max

Limits

-7

Min Max

Unit

ns ns ns ns

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