Mitsubishi MH4S64DBKG-8L, MH4S64DBKG-8, MH4S64DBKG-7, MH4S64DBKG-7L Datasheet
Preliminary Spec.
for easy interchange or addition of modules.
APPLICATION
4096 refresh cycle /64ms
(Component SDRAM)
Some contents are subject to change without notice.
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
MH4S64DBKG -7,-7L,-8,-8L
DESCRIPTION
The MH4S64DBKG is 8388608 - word by 64-bit
Synchronous DRAM module. This consists of four
industry standard 4Mx16 Synchronous DRAMs in
TSOP and one industory standard EEPROM in
TSSOP.
The mounting of TSOP on a card edge Dual
Inline package provides any application where
high densities and large quantities of memory are
required.
This is a socket type - memory modules, suitable
FEATURES
Frequency
-7,-7L
-8,-8L
100MHz
PC100 compliant
CLK Access Time
6.0ns(CL=3)
6.0ns(CL=3)100MHz
Utilizes industry standard 4M x 16 Synchronous DRAMs
TSOP and industry standard EEPROM in TSSOP
144-pin (72-pin dual in-line package)
single 3.3V±0.3V power supply
Clock frequency 100MHz(max.)
Fully synchronous operation referenced to clock rising
edge
4 bank operation controlled by BA0,1(Bank Address)
/CAS latency- 2/3(programmable)
Burst length- 1/2/4/8/Full Page(programmable)
Burst type- sequential / interleave(programmable)
Column access - random
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
LVTTL Interface
PCB Outline
(Front)
(Back)
main memory or graphic memory in computer systems
1
2
143
144
MIT-DS-0338-0.0
MITSUBISHI
ELECTRIC
( / 55 )
1
17.Sep.1999
Preliminary Spec.
PIN CONFIGURATION
Number
Pin Name
Pin Name
Number
1
357911131517192468101214161820
Number
Pin Name
Pin Name
Number
73747576777879808182838485
868788899091922122939423249596252697982728991002930
101
1023132
103
1043334
105
1063536
107
1083738
109
1103940
111
1124142
113
1144344
115
1164546
117
1184748
119
1204950
121
1225152
123
1245354
125
1265556
127
1285758
129
1305960
131
1326162
133
1346364
135
1366566
137
1386768
139
1406970
141
1427172
143
144
Vss
DQ0
DQ1
DQ2
DQ3
Vcc
DQ4
DQ5
DQ6
DQ7
Vss
DQ32
DQ33
DQ34
DQ35
Vcc
DQ36
DQ37
DQ38
DQ39
NC
CLK1
Vss
VssNCNCNCNC
Vcc
Vcc
DQ16
DQ48
DQ17
DQ49
DQ18
DQ50
DQ19
DQ51
Vss
Vss
Vss
Vss
DQ20
DQ52
DQMB0
DQMB4
DQ21
DQ53
DQMB1
DQMB5
DQ22
DQ54
Vcc
Vcc
DQ23
DQ55
A0A3Vcc
VccA1A4A6A7A2A5A8BA0
Vss
Vss
Vss
Vss
DQ8
DQ40
A9
BA1
DQ9
DQ41
A10
A11
DQ10
DQ42
Vcc
Vcc
DQ11
DQ43
DQMB2
DQMB6
Vcc
Vcc
DQMB3
DQMB7
DQ12
DQ44
Vss
Vss
DQ13
DQ45
DQ24
DQ56
DQ14
DQ46
DQ25
DQ57
DQ15
DQ47
DQ26
DQ58
Vss
Vss
DQ27
DQ59
NCNCVcc
VccNCNC
DQ28
DQ60
CLK0
CKE0
DQ29
DQ61
Vcc
Vcc
DQ30
DQ62
/RAS
/CAS
DQ31
DQ63
/WE
CKE1
Vss
Vss
/S0NCSDA
SCL
/S1NCVcc
Vcc
Some contents are subject to change without notice.
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
MH4S64DBKG -7,-7L,-8,-8L
PIN
Front side
PIN
Back side
PIN
Front side
PIN
Back side
MIT-DS-0338-0.0
NC = No Connection
MITSUBISHI
ELECTRIC
( / 55 )
2
17.Sep.1999
Preliminary Spec.
Block Diagram
Some contents are subject to change without notice.
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
/S0
MITSUBISHI LSIs
MH4S64DBKG -7,-7L,-8,-8L
DQMB0
DQMB1
DQMB2
DQMB3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
10Ω
DQML
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQMU
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
DQML
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQMU
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
/CS
D0
/CS
D1
DQMB4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQMB5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQMB6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQMB7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQML
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQMU
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
DQML
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQMU
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
/CS
D2
/CS
D3
BA0,BA1,A<11:0>
MIT-DS-0338-0.0
CLK0
CKE0
/RAS
/CAS
/WE
Vcc
Vss
D0 - D3
D0 - D3
D0 - D3
D0 - D3
D0 - D3
D0 - D3
D0 - D3
CLK1
MITSUBISHI
ELECTRIC
( / 55 )
3
SCL
SERIAL PD
A0 A1 A2
SDA
17.Sep.1999
Preliminary Spec.
Serial Presence Detect Table I
SDRAM Cycletime at Max. Supported CAS Latency (CL).
Non-PARITY
Minimum Clock Delay,Back to Back Random Column Addresses
1/2/4/8/Full page
non-buffered,non-registered
Precharge All,Auto precharge
SDRAM Access form Clock(2nd highest CAS latency)
SDRAM Access form Clock(3rd highest CAS latency)
-8,8L
-8,8L
-7,7L
-7,7L
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
Byte Function described SPD enrty data SPD DATA(hex)
Defines # bytes written into serial memory at module mfgr 128
0
1 Total # bytes of SPD memory device
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27 Precharge to Active Minimum
28
29
30 Active to Precharge Min
DIMM Configuration type (Non-parity,Parity,ECC)
SDRAM Cycle time(2nd highest CAS latency)
SDRAM Cycle time(3rd highest CAS latency)
Fundamental memory type SDRAM 04
# Row Addresses on this assembly A0-A11 0C
# Column Addresses on this assembly
# Module Banks on this assembly
Data Width of this assembly... x64 40
... Data Width continuation 0 00
Voltage interface standard of this assembly LVTTL 01
Cycle time for CL=3
SDRAM Access from Clock
tAC for CL=3
Refresh Rate/Type self refresh(15.625uS) 80
SDRAM width,Primary DRAM
Error Checking SDRAM data width N/A 00
Burst Lengths Supported
# Banks on Each SDRAM device 4bank 04
CAS# Latency 2/3 06
CS# Latency 0 01
Write Latency 0 01
SDRAM Module Attributes
SDRAM Device Attributes:General
Cycle time for CL=2
tAC for CL=2
Row Active to Row Active Min.
RAS to CAS Delay Min
256 Bytes 08
A0-A7 08
1BANK 01
10ns
6ns 60
x16 10
1 01
10ns
13ns D0
6ns 60
7ns 70
N/A 00
N/A 00
20ns 14
20ns 14
20ns
50ns 32
80
A0
00
8F
00
0E
A0
14
MIT-DS-0338-0.0
MITSUBISHI
ELECTRIC
( / 55 )
4
17.Sep.1999
Preliminary Spec.
Serial Presence Detect Table II
4D483453363444424B472D38202020202020
Manufacturing date
4D483453363444424B472D384C2020202020
4D483453363444424B472D374C2020202020
-7,7L-8,8L
-7,7L8F-8,8L
4D483453363444424B472D37202020202020
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
31 Density of each bank on module 32MByte 08
32 Command and Address signal input setup time 2ns 20
33 Command and Address signal input hold time
34 Data signal input setup time 2ns
35 Data signal input hold time
36-61
62 SPD Revision
63 Checksum for bytes 0-62
64-71 Manufactures Jedec ID code per JEP-108E MITSUBISHI 1CFFFFFFFFFFFFFF
72 Manufacturing location Miyoshi,Japan 01
73-90 Manufactures Part Number
91-92 Revision Code PCB revision rrrr
93-94
95-98 Assembly Serial Number serial number ssssssss
99-125 Manufacture Specific Data option 00
126 Intetl specification frequency
127 Intel specification CAS# Latency support
128+ Unused storage locations open 00
Superset Information (may be used in future) option 00
1ns 10
20
1ns 10
rev 1.2A 12
Check sum for -7,7L 04
Check sum for -8,-8L 44
Tajima,Japan 02
NC,USA 03
Germany 04
MH4S64DBKG-7
MH8S64DBKG-7L
MH8S64DBKG-8
MH8S64DBKG-8L
year/week code yyww
100MHz 64
8D
MIT-DS-0338-0.0
MITSUBISHI
ELECTRIC
( / 55 )
5
17.Sep.1999
Preliminary Spec.
Combination of /RAS,/CAS,/WE defines basic commands.
Some contents are subject to change without notice.
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
PIN FUNCTION
MITSUBISHI LSIs
MH4S64DBKG -7,-7L,-8,-8L
CLK0
CKE0 Input
/S0
/RAS,/CAS,/WE Input
A0-11 Input
Input
Input
Master Clock:All other inputs are referenced to the rising
edge of CK
Clock Enable:CKE controls internal clock.When CKE is
low,internal clock for the following cycle is ceased. CKE is
also used to select auto / self refresh. After self refresh
mode is started, CKE E becomes asynchronous input.Self
refresh is maintained as long as CKE is low.
Chip Select: When /S is high,any command means
No Operation.
A0-11 specify the Row/Column Address in conjunction with
BA0,1.The Row Address is specified by A0-11.The Column
Address is specified by A0-7.A10 is also used to indicate
precharge option.When A10 is high at a read / write
command, an auto precharge is performed. When A10 is
high at a precharge command, both banks are precharged.
BA0,1 Input
DQ0-63
DQMB0-7 Input
Vdd,Vss
SCL
SDA
MIT-DS-0338-0.0
Bank Address:BA0,1 is not simply BA.BA specifies the
bank to which a command is applied.BA0,1 must be set
with ACT,PRE,READ,WRITE commands
Input/Output
Power Supply Power Supply for the memory mounted module.
Input
Output
Data In and Data out are referenced to the rising edge
of CK
Din Mask/Output Disable:When DQMB is high in burst
write.Din for the current cycle is masked.When DQMB is
high in burst read,Dout is disabled at the next but one cycle.
Serial clock for serial PD
Serial data for serial PD
MITSUBISHI
ELECTRIC
( / 55 )
6
17.Sep.1999
Preliminary Spec.
The MH4S64DBKG provides basic functions,bank(row)activate,burst read / write,
To know the detailed definition of commands please see the command truth table.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
BASIC FUNCTIONS
bank(row)precharge,and auto / self refresh.
Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge.
In addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and
precharge option,respectively.
CK
/S
Chip Select : L=select, H=deselect
/RAS
/CAS
/WE
CKE
A10
Command
Command
Command
Refresh Option @refresh
command
Precharge Option @precharge or read/write
command
define basic commands
Activate(ACT) [/RAS =L, /CAS = /WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read(READ) [/RAS =H,/CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA.First output
data appears after /CAS latency. When A10 =H at this command,the bank is
deactivated after the burst read(auto-precharge,READA).
Write(WRITE) [/RAS =H, /CAS = /WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data
length to be written is set by burst length. When A10 =H at this command, the bank is
deactivated after the burst write(auto-precharge,WRITEA).
Precharge(PRE) [/RAS =L, /CAS =H,/WE =L]
PRE command deactivates the active bank indicated by BA. This command also
terminates burst read / write operation. When A10 =H at this command, both banks
are deactivated(precharge all, PREA).
Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H]
PEFA command starts auto-refresh cycle. Refresh address including bank address
are generated internally. After this command, the banks are precharged automatically.
MIT-DS-0338-0.0
MITSUBISHI
ELECTRIC
( / 55 )
7
17.Sep.1999
Preliminary Spec.
Precharge All Bank
Some contents are subject to change without notice.
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
COMMAND TRUTH TABLE
COMMAND MNEMONIC
CKE
n-1
CKE
n
MITSUBISHI LSIs
MH4S64DBKG -7,-7L,-8,-8L
/S
/RAS
/CAS
/WE BA0,1 A10
A11
A0-9
Deselect DESEL H X H X X X X X X
No Operation NOP H X L H H H X X X
Row Adress Entry &
Bank Activate
Single Bank Precharge PRE H X L L H L V L X
Column Address Entry
& Write
Column Address Entry
& Write with Auto-
Precharge
Column Address Entry
& Read
Column Address Entry
& Read with Auto
Precharge
Auto-Refresh REFA H H L L L H X X X
Self-Refresh Entry REFS H L L L L H X X X
Self-Refresh Exit REFSX L H H X X X X X X
Burst Terminate TERM
Mode Register Set
ACT H X L L H H V V V
PREA
WRITE
WRITEA H X L H L L V H V
READ H X L H L H V L V
READA H X L H L H V H V
MRS
H X L L H L X H X
H X L H L L V L V
L H L H H H X X X
H X L H H L X X X
H X L L L L L L
X
X
V
X
X
X
X
X
X
X
X
X
X
X
L
V*1
H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CK cycle number
NOTE:
1.A7-9 = 0, A0-6 = Mode Address
MIT-DS-0338-0.0
MITSUBISHI
ELECTRIC
( / 55 )
8
17.Sep.1999
Preliminary Spec.
Some contents are subject to change without notice.
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE
MITSUBISHI LSIs
MH4S64DBKG -7,-7L,-8,-8L
Current State /S /RAS /CAS /WE Address
IDLE H X X X X DESEL NOP
L H H H X NOP NOP
L H H L
L H L X
L L H H
L L H L
L L L H X REFA
L L L L
ROW ACTIVE H X X X X DESEL NOP
L H H H X NOP NOP
L H H L BA TBST NOP
L H L H BA,CA,A10 READ/READA
L H L L BA,CA,A10
L L H H BA,RA ACT Bank Active/ILLEGAL*2
L L H L BA,A10 PRE/PREA Precharge/Precharge All
L L L H X REFA ILLEGAL
L L L L
READ H X X X X DESEL NOP(Continue Burst to END)
L H H H X NOP NOP(Continue Burst to END)
L H H L
L H L H BA,CA,A10 READ/READA
L H L L BA,CA,A10 WRITE/WRITEA
L L H H BA,RA ACT Bank Active/ILLEGAL*2
L L H L BA,A10 PRE/PREA Terminate Burst,Precharge
L L L H X REFA ILLEGAL
L L L L
BA TBST ILLEGAL*2
BA,CA,A10
BA,RA
BA,A10 PRE/PREA NOP*4
Op-Code,
Mode-Add
Op-Code,
Mode-Add
BA
Op-Code,
Mode-Add
Command
READ/WRITE ILLEGAL*2
ACT Bank Active,Latch RA
Auto-Refresh*5
MRS Mode Register Set*5
Begin Read,Latch CA,
Determine Auto-Precharge
WRITE/
WRITEA
MRS ILLEGAL
TBST Terminate Burst
MRS ILLEGAL
Begin Write,Latch CA,
Determine Auto-Precharge
Terminate Burst,Latch CA,
Begin New Read,Determine
Auto-Precharge*3
Terminate Burst,Latch CA,
Begin Write,Determine AutoPrecharge*3
Action
MIT-DS-0338-0.0
MITSUBISHI
ELECTRIC
( / 55 )
9
17.Sep.1999
Preliminary Spec.
Some contents are subject to change without notice.
MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
MITSUBISHI LSIs
Current State /S /RAS /CAS /WE Address
WRITE H X X X X DESEL NOP(Continue Burst to END)
L H H H X NOP NOP(Continue Burst to END)
L H H L BA TBST Terminate Burst
L H L H BA,CA,A10
L H L L BA,CA,A10
L L H H BA,RA ACT Bank Active/ILLEGAL*2
L L H L BA,A10 PRE/PREA Terminate Burst,Precharge
L L L H X REFA ILLEGAL
L L L L
READ with H X X X X DESEL NOP(Continue Burst to END)
AUTO L H H H X NOP NOP(Continue Burst to END)
PRECHARGE L H H L BA TBST ILLEGAL
L H L H BA,CA,A10 READ/READA ILLEGAL
L H L L BA,CA,A10
L L H H BA,RA ACT Bank Active/ILLEGAL*2
L L H L BA,A10 PRE/PREA ILLEGAL*2
L L L H X REFA ILLEGAL
L L L L
WRITE with H X X X X DESEL NOP(Continue Burst to END)
AUTO L H H H X NOP NOP(Continue Burst to END)
PRECHARGE L H H L
L H L H BA,CA,A10 READ/READA ILLEGAL
L H L L BA,CA,A10
L L H H
L L H L BA,A10 PRE/PREA ILLEGAL*2
L L L H X REFA ILLEGAL
L L L L
Op-Code,
Mode-Add
Op-Code,
Mode-Add
BA
BA,RA
Op-Code,
Mode-Add
Command
Terminate Burst,Latch CA,
READ/READA
WRITE/
WRITEA
MRS ILLEGAL
WRITE/
WRITEA
MRS ILLEGAL
TBST ILLEGAL
WRITE/
WRITEA
ACT Bank Active/ILLEGAL*2
MRS ILLEGAL
Begin Read,Determine AutoPrecharge*3
Terminate Burst,Latch CA,
Begin Write,Determine AutoPrecharge*3
ILLEGAL
ILLEGAL
Action
MIT-DS-0338-0.0
MITSUBISHI
ELECTRIC
( / 55 )
10
17.Sep.1999
Preliminary Spec.
Some contents are subject to change without notice.
MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
MITSUBISHI LSIs
Current State /S /RAS /CAS /WE Address
PRE - H X X X X DESEL NOP(Idle after tRP)
CHARGING L H H H X NOP NOP(Idle after tRP)
L H H L BA TBST ILLEGAL*2
L H L X BA,CA,A10 READ/WRITE ILLEGAL*2
L L H H BA,RA ACT ILLEGAL*2
L L H L BA,A10 PRE/PREA NOP*4(Idle after tRP)
L L L H X REFA ILLEGAL
L L L L
ROW H X X X X DESEL NOP(Row Active after tRCD
ACTIVATING L H H H X NOP NOP(Row Active after tRCD
L H H L BA TBST ILLEGAL*2
L H L X BA,CA,A10 READ/WRITE ILLEGAL*2
L L H H BA,RA ACT ILLEGAL*2
L L H L BA,A10 PRE/PREA ILLEGAL*2
L L L H X REFA ILLEGAL
L L L L
Op-Code,
Mode-Add
Op-Code,
Mode-Add
Command
MRS ILLEGAL
MRS ILLEGAL
Action
WRITE RE- H X X X X DESEL NOP
COVERING L H H H X NOP NOP
L H H L BA TBST ILLEGAL*2
L H L X BA,CA,A10 READ/WRITE ILLEGAL*2
L L H H BA,RA ACT ILLEGAL*2
L L H L BA,A10 PRE/PREA ILLEGAL*2
L L L H X REFA ILLEGAL
L L L L
MIT-DS-0338-0.0
Op-Code,
Mode-Add
MITSUBISHI
MRS ILLEGAL
ELECTRIC
( / 55 )
11
17.Sep.1999
Preliminary Spec.
1. All entries assume that CKE was High during the preceding clock cycle and the current
Some contents are subject to change without notice.
MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
Current State /S /RAS /CAS /WE Address Command Action
RE- H X X X X DESEL NOP(Idle after tRC)
MITSUBISHI LSIs
FRESHING L H H H X NOP
L H H L BA TBST ILLEGAL
L H L X BA,CA,A10 READ/WRITE ILLEGAL
L L H H BA,RA ACT ILLEGAL
L L H L BA,A10 PRE/PREA ILLEGAL
L L L H X REFA ILLEGAL
L L L L
MODE H X X X X DESEL NOP(Idle after tRSC)
REGISTER L H H H X NOP NOP(Idle after tRSC)
SETTING L H H L BA TBST ILLEGAL
L H L X BA,CA,A10 READ/WRITE ILLEGAL
L L H H BA,RA ACT ILLEGAL
L L H L BA,A10 PRE/PREA ILLEGAL
L L L H X REFA ILLEGAL
L L L L
Op-Code,
MRS ILLEGAL
Mode-Add
Op-Code,
MRS ILLEGAL
Mode-Add
NOP(Idle after tRC)
ABBREVIATIONS:
H = Hige Level, L = Low Level, X = Don't Care
BA = Bank Address, RA = Row Address, CA = Column Address, NOP = No Operation
NOTES:
clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA,
depending on the state of that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state.May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
ILLEGAL = Device operation and / or date-integrity are not guaranteed.
MIT-DS-0338-0.0
MITSUBISHI
17.Sep.1999
ELECTRIC
( / 55 )
12
Preliminary Spec.
Some contents are subject to change without notice.
MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE FOR CKE
MITSUBISHI LSIs
Current State
SELF - H X X X X X X
REFRESH*1 L H H X X X X
POWER H X X X X X X
DOWN L H X X X X X
ALL BANKS H H X X X X X
IDLE*2 H L L L L H X
CK
CK
n-1
L H L H H H X
L H L H H L X
L H L H L X X
L H L L X X X
L L X X X X X
L L X X X X X
H L H X X X X
H L L H H H X
H L L H H L X
H L L H L X X
H L L L X X X
n
/RAS /CAS /WE Add
/S
Action
INVALID
Exit Self-Refresh(Idle after tRC)
Exit Self-Refresh(Idle after tRC)
ILLEGAL
ILLEGAL
ILLEGAL
NOP(Maintain Self-Refresh)
INVALID
Exit Power Down to Idle
NOP(Maintain Self-Refresh)
Refer to Function Truth Table
Enter Self-Refresh
Enter Power Down
Enter Power Down
ILLEGAL
ILLEGAL
ILLEGAL
L X X X X X X
ANY STATE H H X X X X X
other than H L X X X X X
listed above L H X X X X X
L L X X X X X
Refer to Current State = Power Down
Refer to Function Truth Table
Begin CK0 Suspend at Next Cycle*3
Exit CK0 Suspend at Next Cycle*3
Maintain CK0 Suspend
ABBREVIATIONS:
H = High Level, L = Low Level, X = Don't Care
NOTES:
1. CKE Low to High transition will re-enable CK and other inputs asynchronously.
A minimum setup time must be satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only form the All banks idle State.
3. Must be legal command.
MIT-DS-0338-0.0
MITSUBISHI
ELECTRIC
( / 55 )
13
17.Sep.1999
Preliminary Spec.
Some contents are subject to change without notice.
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
SIMPLIFIED STATE DIAGRAM
MITSUBISHI LSIs
MH4S64DBKG -7,-7L,-8,-8L
SELF
REFRESH
REFS
REFSX
WRITE
SUSPEND
MODE
REGISTER
SET
CLK
SUSPEND
CKEL
WRITE
CKEH
WRITEA READA
MRS
IDLE
ACT
CKEL
CKEH
ROW
ACTIVE
WRITE READ
WRITEA
WRITE
WRITEA
READA
READ
READA
REFA
CKEL
CKEH
READ
AUTO
REFRESH
POWER
DOWN
CKEL
CKEH
READ
SUSPEND
SUSPEND
POWER
APPLIED
MIT-DS-0338-0.0
WRITEA
CKEL
CKEH
POWER
ON
WRITEA
PRE
PRE
PRE PRE
PRE
CHARGE
MITSUBISHI
ELECTRIC
( / 55 )
14
READA
CKEL
CKEH
READA
SUSPEND
Automatic Sequence
Command Sequence
17.Sep.1999
Preliminary Spec.
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent
After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode
SDRAM is ready for new command.
LENGTH
LATENCY
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
a SDRAM from damaged or malfunctioning.
1. Clock will be applied at power up along with power.Attempt to maintain CKE high,DQM0-7
high and NOP condition at the inputs along with power.
2. Maintain stable power, stable cock, and NOP input conditions for a minimum of 500us.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
register(MRS). The mode register stores these date until the next MRS command, which
may be issued when both banks are in idle state. After tRSC from a MRS command, the
CK
/S
/RAS
/CAS
/WE
BT= 0 BT= 1
1
2
4
8
R
R
R
FP
SEQUENTIAL
INTERLEAVED
V
1
2
4
8
R
R
R
R
MODE
00
CL
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0BA1BA0
0 0
/CAS LATENCY
WM
R
R
2
3
R
R
R
R
0 0
LTMODE BT BL
BURST
BURST
TYPE
BA0,1 A11-0
BL
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0
1
WRITE
MODE
MIT-DS-0338-0.0
BURST
0
SINGLE BIT FP: Full Page
1
MITSUBISHI
R:Reserved for Future Use
ELECTRIC
( / 55 )
15
17.Sep.1999
Preliminary Spec.
READ
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
[ /CAS LATENCY]
/CAS latency,CL,is used to synchronize the first output data with the CLK
frequency,i.e.,the speed of CLK determines which CL should be used.First output data is
available after CL cycles from READ command.
/CAS Latency Timing(BL=4)
CK
Command
Address
DQ
DQ
ACT
tRCD
X
READ
Y
CL=2
Q0 Q1 Q2 Q3
CL=3
Q0 Q1 Q2 Q3
CL=2
CL=3
[ BURST LENGTH ]
The burst length,BL,determines the number of consecutive wrutes or reads that will be
automatically performed after the initial write or read command.For BL=1,2,4,8,full page
the output data is tristated(Hi-Z) after the last read.For BL=FP (Full Page),the TBST (Burst
Terminate) command should be issued to stop the output of data.
Burst Length Timing(CL=2)
tRCD
CK
Command
ACT
Address
DQ
DQ
DQ
DQ
DQ
MIT-DS-0338-0.0
X
Y
Q0
Q0 Q1
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3 Q5 Q6Q4 Q7
Q0 Q1 Q2 Q3 Q5 Q6Q4 Q7
m=255
MITSUBISHI
Q8
Qm Q0 Q1
Full Page counter rolls over
and continues to count.
BL=1
BL=2
BL=4
BL=8
BL=FP
17.Sep.1999
ELECTRIC
( / 55 )
16
Preliminary Spec.
Some contents are subject to change without notice.
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
CK
MITSUBISHI LSIs
MH4S64DBKG -7,-7L,-8,-8L
Command
Address
DQ
Initial Address
A2 A1 A0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
CL= 3
BL= 4
BL
8
Read
Y
Q0 Q1 Q2 Q3
/CAS Latency Burst Length Burst Length
Burst Type
Column Addressing
Sequential Interleaved
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6
2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5
3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4
4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3
Write
Y
D0 D1
D2
D3
1 0 1
1 1 0
1 1 1
- 0 0
- 0 1
- 1 0
- 1 1
- - 0
- - 1
MIT-DS-0338-0.0
5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2
6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1
7 0 1 2
0 1 2 3
1 2 3 0
4
2 3 0 1
3 0
0 1
2
1 0
3 4 5 6 3 2 1 0
1 2
7 6 5 4
0 1 2 3
1 0 3 2
2 3 0 1
3 2
0 1
1 0
1 0
MITSUBISHI
ELECTRIC
( / 55 )
17
17.Sep.1999
Loading...