Some contents are subject to change without notice.
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
MH4S64DBKG -7,-7L,-8,-8L
DESCRIPTION
The MH4S64DBKG is 8388608 - word by 64-bit
Synchronous DRAM module. This consists of four
industry standard 4Mx16 Synchronous DRAMs in
TSOP and one industory standard EEPROM in
TSSOP.
The mounting of TSOP on a card edge Dual
Inline package provides any application where
high densities and large quantities of memory are
required.
This is a socket type - memory modules, suitable
FEATURES
Frequency
-7,-7L
-8,-8L
100MHz
PC100 compliant
CLK Access Time
6.0ns(CL=3)
6.0ns(CL=3)100MHz
Utilizes industry standard 4M x 16 Synchronous DRAMs
TSOP and industry standard EEPROM in TSSOP
144-pin (72-pin dual in-line package)
single 3.3V±0.3V power supply
Clock frequency 100MHz(max.)
Fully synchronous operation referenced to clock rising
edge
4 bank operation controlled by BA0,1(Bank Address)
/CAS latency- 2/3(programmable)
Burst length- 1/2/4/8/Full Page(programmable)
Burst type- sequential / interleave(programmable)
Column access - random
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
Some contents are subject to change without notice.
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
MH4S64DBKG -7,-7L,-8,-8L
PIN
Front side
PIN
Back side
PIN
Front side
PIN
Back side
MIT-DS-0338-0.0
NC = No Connection
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Preliminary Spec.
Block Diagram
Some contents are subject to change without notice.
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
/S0
MITSUBISHI LSIs
MH4S64DBKG -7,-7L,-8,-8L
DQMB0
DQMB1
DQMB2
DQMB3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
10Ω
DQML
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQMU
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
DQML
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQMU
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
/CS
D0
/CS
D1
DQMB4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQMB5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQMB6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQMB7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQML
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQMU
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
DQML
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQMU
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
/CS
D2
/CS
D3
BA0,BA1,A<11:0>
MIT-DS-0338-0.0
CLK0
CKE0
/RAS
/CAS
/WE
Vcc
Vss
D0 - D3
D0 - D3
D0 - D3
D0 - D3
D0 - D3
D0 - D3
D0 - D3
CLK1
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SCL
SERIAL PD
A0 A1 A2
SDA
17.Sep.1999
Preliminary Spec.
Serial Presence Detect Table I
SDRAM Cycletime at Max. Supported CAS Latency (CL).
Non-PARITY
Minimum Clock Delay,Back to Back Random Column Addresses
1/2/4/8/Full page
non-buffered,non-registered
Precharge All,Auto precharge
SDRAM Access form Clock(2nd highest CAS latency)
SDRAM Access form Clock(3rd highest CAS latency)
-8,8L
-8,8L
-7,7L
-7,7L
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
ByteFunction describedSPD enrty dataSPD DATA(hex)
Defines # bytes written into serial memory at module mfgr128
0
1Total # bytes of SPD memory device
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27Precharge to Active Minimum
28
29
30Active to Precharge Min
DIMM Configuration type (Non-parity,Parity,ECC)
SDRAM Cycle time(2nd highest CAS latency)
SDRAM Cycle time(3rd highest CAS latency)
Fundamental memory typeSDRAM04
# Row Addresses on this assemblyA0-A110C
# Column Addresses on this assembly
# Module Banks on this assembly
Data Width of this assembly...x6440
... Data Width continuation000
Voltage interface standard of this assemblyLVTTL01
Cycle time for CL=3
SDRAM Access from Clock
tAC for CL=3
Refresh Rate/Typeself refresh(15.625uS)80
SDRAM width,Primary DRAM
Error Checking SDRAM data widthN/A00
Burst Lengths Supported
# Banks on Each SDRAM device4bank04
CAS# Latency2/306
CS# Latency001
Write Latency001
SDRAM Module Attributes
SDRAM Device Attributes:General
Cycle time for CL=2
tAC for CL=2
Row Active to Row Active Min.
RAS to CAS Delay Min
256 Bytes08
A0-A708
1BANK01
10ns
6ns60
x1610
101
10ns
13nsD0
6ns60
7ns70
N/A00
N/A00
20ns14
20ns14
20ns
50ns32
80
A0
00
8F
00
0E
A0
14
MIT-DS-0338-0.0
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Preliminary Spec.
Serial Presence Detect Table II
4D483453363444424B472D38202020202020
Manufacturing date
4D483453363444424B472D384C2020202020
4D483453363444424B472D374C2020202020
-7,7L-8,8L
-7,7L8F-8,8L
4D483453363444424B472D37202020202020
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
31Density of each bank on module32MByte08
32Command and Address signal input setup time2ns20
33Command and Address signal input hold time
34Data signal input setup time2ns
35Data signal input hold time
36-61
62SPD Revision
63Checksum for bytes 0-62
64-71Manufactures Jedec ID code per JEP-108EMITSUBISHI1CFFFFFFFFFFFFFF
72Manufacturing locationMiyoshi,Japan01
73-90Manufactures Part Number
91-92Revision CodePCB revisionrrrr
93-94
95-98Assembly Serial Numberserial numberssssssss
99-125Manufacture Specific Dataoption00
126Intetl specification frequency
127Intel specification CAS# Latency support
128+Unused storage locationsopen00
Superset Information (may be used in future)option00
1ns10
20
1ns10
rev 1.2A12
Check sum for -7,7L04
Check sum for -8,-8L44
Tajima,Japan02
NC,USA03
Germany04
MH4S64DBKG-7
MH8S64DBKG-7L
MH8S64DBKG-8
MH8S64DBKG-8L
year/week codeyyww
100MHz64
8D
MIT-DS-0338-0.0
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17.Sep.1999
Preliminary Spec.
Combination of /RAS,/CAS,/WE defines basic commands.
Some contents are subject to change without notice.
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
PIN FUNCTION
MITSUBISHI LSIs
MH4S64DBKG -7,-7L,-8,-8L
CLK0
CKE0Input
/S0
/RAS,/CAS,/WEInput
A0-11Input
Input
Input
Master Clock:All other inputs are referenced to the rising
edge of CK
Clock Enable:CKE controls internal clock.When CKE is
low,internal clock for the following cycle is ceased. CKE is
also used to select auto / self refresh. After self refresh
mode is started, CKE E becomes asynchronous input.Self
refresh is maintained as long as CKE is low.
Chip Select: When /S is high,any command means
No Operation.
A0-11 specify the Row/Column Address in conjunction with
BA0,1.The Row Address is specified by A0-11.The Column
Address is specified by A0-7.A10 is also used to indicate
precharge option.When A10 is high at a read / write
command, an auto precharge is performed. When A10 is
high at a precharge command, both banks are precharged.
BA0,1Input
DQ0-63
DQMB0-7Input
Vdd,Vss
SCL
SDA
MIT-DS-0338-0.0
Bank Address:BA0,1 is not simply BA.BA specifies the
bank to which a command is applied.BA0,1 must be set
with ACT,PRE,READ,WRITE commands
Input/Output
Power Supply Power Supply for the memory mounted module.
Input
Output
Data In and Data out are referenced to the rising edge
of CK
Din Mask/Output Disable:When DQMB is high in burst
write.Din for the current cycle is masked.When DQMB is
high in burst read,Dout is disabled at the next but one cycle.
Serial clock for serial PD
Serial data for serial PD
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Preliminary Spec.
The MH4S64DBKG provides basic functions,bank(row)activate,burst read / write,
To know the detailed definition of commands please see the command truth table.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
BASIC FUNCTIONS
bank(row)precharge,and auto / self refresh.
Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge.
In addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and
precharge option,respectively.
CK
/S
Chip Select : L=select, H=deselect
/RAS
/CAS
/WE
CKE
A10
Command
Command
Command
Refresh Option @refresh
command
Precharge Option @precharge or read/write
command
define basic commands
Activate(ACT) [/RAS =L, /CAS = /WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read(READ) [/RAS =H,/CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA.First output
data appears after /CAS latency. When A10 =H at this command,the bank is
deactivated after the burst read(auto-precharge,READA).
Write(WRITE) [/RAS =H, /CAS = /WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data
length to be written is set by burst length. When A10 =H at this command, the bank is
deactivated after the burst write(auto-precharge,WRITEA).
Precharge(PRE) [/RAS =L, /CAS =H,/WE =L]
PRE command deactivates the active bank indicated by BA. This command also
terminates burst read / write operation. When A10 =H at this command, both banks
are deactivated(precharge all, PREA).
Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H]
PEFA command starts auto-refresh cycle. Refresh address including bank address
are generated internally. After this command, the banks are precharged automatically.
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Preliminary Spec.
Precharge All Bank
Some contents are subject to change without notice.
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
COMMAND TRUTH TABLE
COMMANDMNEMONIC
CKE
n-1
CKE
n
MITSUBISHI LSIs
MH4S64DBKG -7,-7L,-8,-8L
/S
/RAS
/CAS
/WE BA0,1A10
A11
A0-9
DeselectDESELHXHXXXXXX
No OperationNOPHXLHHHXXX
Row Adress Entry &
Bank Activate
Single Bank PrechargePREHXLLHLVLX
Column Address Entry
& Write
Column Address Entry
& Write with Auto-
Precharge
Column Address Entry
& Read
Column Address Entry
& Read with Auto
Precharge
Auto-RefreshREFAHHLLLHXXX
Self-Refresh EntryREFSHLLLLHXXX
Self-Refresh ExitREFSXLHHXXXXXX
Burst TerminateTERM
Mode Register Set
ACTHXLLHHVVV
PREA
WRITE
WRITEAHXLHLLVHV
READHXLHLHVLV
READAHXLHLHVHV
MRS
HXLLHLXHX
HXLHLLVLV
LHLHHHXXX
HXLHHLXXX
HXLLLLLL
X
X
V
X
X
X
X
X
X
X
X
X
X
X
L
V*1
H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CK cycle number
NOTE:
1.A7-9 = 0, A0-6 = Mode Address
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Preliminary Spec.
Some contents are subject to change without notice.
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE
MITSUBISHI LSIs
MH4S64DBKG -7,-7L,-8,-8L
Current State/S/RAS /CAS/WEAddress
IDLEHXXXXDESELNOP
LHHHXNOPNOP
LHHL
LHLX
LLHH
LLHL
LLLHXREFA
LLLL
ROW ACTIVEHXXXXDESELNOP
LHHHXNOPNOP
LHHLBATBSTNOP
LHLHBA,CA,A10READ/READA
LHLLBA,CA,A10
LLHHBA,RAACTBank Active/ILLEGAL*2
LLHLBA,A10PRE/PREAPrecharge/Precharge All
LLLHXREFAILLEGAL
ABBREVIATIONS:
H = Hige Level, L = Low Level, X = Don't Care
BA = Bank Address, RA = Row Address, CA = Column Address, NOP = No Operation
NOTES:
clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA,
depending on the state of that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state.May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
ILLEGAL = Device operation and / or date-integrity are not guaranteed.
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Preliminary Spec.
Some contents are subject to change without notice.
MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE FOR CKE
MITSUBISHI LSIs
Current State
SELF - HXXXXXX
REFRESH*1LHHXXXX
POWERHXXXXXX
DOWNLHXXXXX
ALL BANKSHHXXXXX
IDLE*2HLLLLHX
CK
CK
n-1
LHLHHHX
LHLHHLX
LHLHLXX
LHLLXXX
LLXXXXX
LLXXXXX
HLHXXXX
HLLHHHX
HLLHHLX
HLLHLXX
HLLLXXX
n
/RAS /CAS/WEAdd
/S
Action
INVALID
Exit Self-Refresh(Idle after tRC)
Exit Self-Refresh(Idle after tRC)
ILLEGAL
ILLEGAL
ILLEGAL
NOP(Maintain Self-Refresh)
INVALID
Exit Power Down to Idle
NOP(Maintain Self-Refresh)
Refer to Function Truth Table
Enter Self-Refresh
Enter Power Down
Enter Power Down
ILLEGAL
ILLEGAL
ILLEGAL
LXXXXXX
ANY STATEHHXXXXX
other thanHLXXXXX
listed aboveLHXXXXX
LLXXXXX
Refer to Current State = Power Down
Refer to Function Truth Table
Begin CK0 Suspend at Next Cycle*3
Exit CK0 Suspend at Next Cycle*3
Maintain CK0 Suspend
ABBREVIATIONS:
H = High Level, L = Low Level, X = Don't Care
NOTES:
1. CKE Low to High transition will re-enable CK and other inputs asynchronously.
A minimum setup time must be satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only form the All banks idle State.
3. Must be legal command.
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Preliminary Spec.
Some contents are subject to change without notice.
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
SIMPLIFIED STATE DIAGRAM
MITSUBISHI LSIs
MH4S64DBKG -7,-7L,-8,-8L
SELF
REFRESH
REFS
REFSX
WRITE
SUSPEND
MODE
REGISTER
SET
CLK
SUSPEND
CKEL
WRITE
CKEH
WRITEAREADA
MRS
IDLE
ACT
CKEL
CKEH
ROW
ACTIVE
WRITEREAD
WRITEA
WRITE
WRITEA
READA
READ
READA
REFA
CKEL
CKEH
READ
AUTO
REFRESH
POWER
DOWN
CKEL
CKEH
READ
SUSPEND
SUSPEND
POWER
APPLIED
MIT-DS-0338-0.0
WRITEA
CKEL
CKEH
POWER
ON
WRITEA
PRE
PRE
PREPRE
PRE
CHARGE
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READA
CKEL
CKEH
READA
SUSPEND
Automatic Sequence
Command Sequence
17.Sep.1999
Preliminary Spec.
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent
After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode
SDRAM is ready for new command.
LENGTH
LATENCY
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
a SDRAM from damaged or malfunctioning.
1. Clock will be applied at power up along with power.Attempt to maintain CKE high,DQM0-7
high and NOP condition at the inputs along with power.
2. Maintain stable power, stable cock, and NOP input conditions for a minimum of 500us.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
register(MRS). The mode register stores these date until the next MRS command, which
may be issued when both banks are in idle state. After tRSC from a MRS command, the
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH4S64DBKG -7,-7L,-8,-8L
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM
[ /CAS LATENCY]
/CAS latency,CL,is used to synchronize the first output data with the CLK
frequency,i.e.,the speed of CLK determines which CL should be used.First output data is
available after CL cycles from READ command.
/CAS Latency Timing(BL=4)
CK
Command
Address
DQ
DQ
ACT
tRCD
X
READ
Y
CL=2
Q0Q1Q2Q3
CL=3
Q0Q1Q2Q3
CL=2
CL=3
[ BURST LENGTH ]
The burst length,BL,determines the number of consecutive wrutes or reads that will be
automatically performed after the initial write or read command.For BL=1,2,4,8,full page
the output data is tristated(Hi-Z) after the last read.For BL=FP (Full Page),the TBST (Burst
Terminate) command should be issued to stop the output of data.
Burst Length Timing(CL=2)
tRCD
CK
Command
ACT
Address
DQ
DQ
DQ
DQ
DQ
MIT-DS-0338-0.0
X
Y
Q0
Q0 Q1
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3Q5 Q6Q4Q7
Q0 Q1 Q2 Q3Q5 Q6Q4Q7
m=255
MITSUBISHI
Q8
Qm Q0 Q1
Full Page counter rolls over
and continues to count.
BL=1
BL=2
BL=4
BL=8
BL=FP
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Preliminary Spec.
Some contents are subject to change without notice.
268435456-BIT (4194304 - WORD BY 64-BIT)SynchronousDRAM