Mitsubishi M5M5V4R08J-20, M5M5V4R08J-15, M5M5V4R08J-12 Datasheet
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
DESCRIPTION
The M5M5V4R08J is a family of 524288-word by 8-bit static
RAMs, fabricated with the high performance CMOS silicon
gate process and designed for high speed application.
The M5M5V4R08J is offered in a 36-pin plastic small outline
J-lead package(SOJ).
These device operate on a single 3.3V supply, and are directly
TTL compatible. They include a power down feature as well.
FEATURES
• Fast access time M5M5V4R08J-12 •••• 12ns(max)
M5M5V4R08J-15 •••• 15ns(max)
M5M5V4R08J-20 •••• 20ns(max)
• Low power dissipation Active •••••••••• 363mW(typ)
Stand by ••••••• 3.3mW(typ)
• Single +3.3V power supply
• Fully static operation : No clocks, No refresh
• Common data I/O
• Easy memory expansion by S
• Three-state outputs : OR-tie capability
• OE prevents data contention in the I/O bus
• Directly TTL compatible : All inputs and outputs
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
MITSUBISHI LSIs
M5M5V4R08J-12,-15,-20
PIN CONFIGURATION (TOP VIEW)
address
inputs
chip select
input
datainputs/
outputs
(3.3V)
(0V)
data
inputs/
outputs
write control
input
address
inputs
1
A0
2
A1
3
A2
4
A3
5
A4
S
DQ1
DQ2
VCC
GND
DQ3
DQ4
W
A5
A6
A7
A8
A9
6
7
8
9
10
11
12
13
14
15
16
17
18
M5M5V4R08J
Outline 36P0K (SOJ)
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
1997.02.06 Rev.D
NC
A18
A17
A16
A15
OE
DQ8
DQ7
GND
VCC
DQ6
DQ5
address
inputs
output enable
input
data
inputs/
outputs
(0V)
(3.3V)
data
inputs/
outputs
A14
A13
A12
A11
address
inputs
A10
NC
APPLICATION
High-speed memory units
BLOCK DIAGRAM
A0
1
A1
2
A2
3
A3
address
inputs
A4
A5
14
A6
15
A7
16
A8
17
S
13
W
OE 31
4
5
6
ROW INPUT BUFFERS
ROW ADDRESS DECODERS
COLUMN I/O CIRCUITS
COLUMN ADDRESS
COLUMN
DECODERS
ADDRESS
DECODERS
COLUMN INPUT BUFFERS
PACKAGE
36pin 400mil SOJ
MEMORY ARRAY
512 ROWS
8192 COLUMNS
7
8
11
12
25
26
OUTPUT BUFFERS
29
30
9
27
DATA INPUT BUFFERS
10
28
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
VCC
GND
data
inputs/
outputs
(3.3V)
(0V)
20 21
22 23 241832 33
address inputs
MITSUBISHI
ELECTRIC
A16A15A14A13A12A11A10A9
34 35
A16
A17
1
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
FUNCTION
The operation mode of the M5M5V4R08J is determined by a
combination of the device control inputs S, W and OE. Each mode
is summarized in the function table.
A write cycle is executed whenever the low level W overlaps
with the low level S. The address must be set-up before the write
cycle and must be stable during the entire cycle.
The data is latched into a cell on the trailing edge of W or S,
whichever occurs first, requiring the set-up and hold time relative
to these edge to be maintained. The output enable input OE
directly controls the output stage. Setting the OE at a high level,
the output stage is in a high impedance state, and the data bus
FUNCTION TABLE
MITSUBISHI LSIs
M5M5V4R08J-12,-15,-20
contention problem in the write cycle is eliminated.
A read cycle is excuted by setting W at a high level and OE at a
low level while S are in an active state (S=L).
When setting S at high level, the chip is in a non-selectable
mode in which both reading and writing are disable. In this mode,
the output stage is in a high-impedance state, allowing OR-tie
with other chips and memory expansion by S.
Signal-S controls the power-down feature. When S goes high,
power dissapation is reduced extremely. The access time from S is
equivalent to the address access time.
S W OE
H
X X
Mode
Non selection Stand by
High-impedance
L Write ActiveDinL X
L Read
L ActiveHigh-impedance
H H
DoutH L
ABSOLUTE MAXIMUM RATINGS
Symbol
Vcc
VI
V
O
Pd
Topr
Tstg(bias)
T
stg
*Pulse width ≤ 20ns, In case of DC:-0.5V
Parameter
Supply voltage
Input voltage
Output voltage
Power dissipation
Operating temperature
Storage temperature(bias)
Storage temperature
With respect to GND
Ta=25 C
DC ELECTRICAL CHARACTERISTICS
Symbol Parameter
V
IH
High-level input voltage
V
IL
Low-level input voltage
VOH
High-level output voltage
VOL 0.4
Low-level output voltage
Input current
I
I
I
Output current in off-state
OZ
Active supply current
I
CC1
(TTL level)
Stand by current
I
CC2
(TTL level)
I
Stand by current
CC3
*Pulse width ≤ 20ns, in case of AC :-3.0V
IOH =-4mA
IOL= 8mA
VI= 0~Vcc
VI (S)= VIH
VO= 0~Vcc
VI (S)= VIL
other inputs VIH or VIL
Output-open(duty 100%)
VI (S)= VIH
VI (S)= Vcc≥0.2V
other inputs VI≤0.2V
or VI≥Vcc-0.2V
DQ
Icc
Active
Ratings
*
-2.0 ~ 4.6
*
-2.0 ~ VCC+0.5
*
-2.0 ~ VCC+0.5
1000
0 ~ 70
-10 ~ 85
-65 ~ 150
(Ta=0 ~ 70 C, Vcc=3.3V unless otherwise noted)
+10%
-5%
Condition
UnitConditions
V
V
V
mW
C
C
C
Limits
Min
2.0
Vcc+0.3
-0.3*
2.4
12ns cycle
15ns cycle
AC
20ns cycle
DC
110 120
12ns cycle
AC
15ns cycle
20ns cycle
DC 60
1
MaxTyp
0.8
10
170
160
150
85
80
75
10
Unit
V
V
V
V
2
µA
µA
mA
mA
mA
MITSUBISHI
ELECTRIC
2
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