2001.06.11 Ver. 2.1
-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
M5M5V416CWG -70HI
DESCRIPTION
The M5M5V416C is a family of low voltage 4-Mbit static RAMs
organized as 262144-words by 16-bit, fabricated by Mitsubishi's
high-performance 0.18µm CMOS technology.
The M5M5V416C is suitable for memory applications where a
simple interfacing , battery operating and battery backup are the
important design objectives.
M5M5V416CWG is packaged in a CSP (chip scale package),
with the outline of 7.0mm x 8.5mm, ball matrix of 6 x 8 (48ball)
and ball pitch of 0.75mm. It gives the best solution for
a compaction of mounting area as well as flexibility of wiring
pattern of printed circuit boards.
Version,
Operating
temperature
I-version
-40 ~ +85°C
Part name
M5M5V416CWG -70HI
Power
Supply
2.7 ~ 3.0V
Access time
max.
70ns
FEATURES
- Single 2.7~3.0V power supply
- Small stand-by current: 0.1µA (2.85V, typ.)
- No clocks, No refresh
- Data retention supply voltage =2.0V
- All inputs and outputs are TTL compatible.
- Easy memory expansion by S1, S2, BC1 and BC2
- Common Data I/O
- Three-state outputs: OR-tie capability
- OE prevents data contention in the I/O bus
- Process technology: 0.18µm CMOS
- Package: 48ball 7.0mm x 8.5mm CSP
Stand-by current (Vcc=3.0V)
* Typical
Ratings (max.)
40°C25°C 40°C
0.40.2
* Typical parameter indicates the value for the center
of distribution, and not 100% tested.
85°C25°C
2021
Active
current
Icc1
(3.0V, typ.)
30mA
(10MHz)
5mA
(1MHz)
PIN CONFIGURATION
A
B
C
D
E
F
G
H
1 2 3 4 5 6
BC1
DQ5
A16
DQ12
GND
VCC
N C
Outline: 48FJA
NC: No Connection
GND
Pin Function
A0 ~ A17
DQ1 ~ DQ16
S1
S2
W
OE
BC1
BC2
Vcc
GND
Address input
Data input / output
Chip select input 1
Chip select input 2
Write control input
Output enable input
Lower Byte (DQ1 ~ 8)
Upper Byte (DQ9 ~ 16)
Power supply
Ground supply
MITSUBISHI ELECTRIC
2001.06.11 Ver. 2.1
-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
M5M5V416CWG -70HI
FUNCTION
The M5M5V416CWG is organized as 262144-words by
16-bit. These devices operate on a single +2.7~3.0V power
supply, and are directly TTL compatible to both input and
output. Its fully static circuit needs no clocks and no
refresh, and makes it useful.
The operation mode are determined by a combination of
the device control inputs BC1 , BC2 , S1, S2 , W and OE.
Each mode is summarized in the function table.
A write operation is executed whenever the low level W
overlaps with the low level BC1 and/or BC2 and the low
level S1 and the high level S2. The address(A0~A17) must
be set up before the write cycle and must be stable during
the entire cycle.
A read operation is executed by setting W at a high level
and OE at a low level while BC1 and/or BC2 and S1 and
S2 are in an active state(S1=L,S2=H).
When setting BC1 at the high level and other pins are in
an active stage , upper-byte are in a selectable mode in
which both reading and writing are enabled, and lower-byte
are in a non-selectable mode. And when setting BC2 at a
high level and other pins are in an active stage, lower-
BLOCK DIAGRAM
When setting BC1 and BC2 at a high level or S1 at a high
level or S2 at a low level, the chips are in a non-selectable
mode in which both reading and writing are disabled. In this
mode, the output stage is in a high-impedance state, allowing
OR-tie with other chips and memory expansion by BC1, BC2
and S1, S2.
The power supply current is reduced as low as 0.1µA(25°C,
typical), and the memory data can be held at +2V power
supply, enabling battery back-up operation during power
failure or power-down operation in the non-selected mode.
FUNCTION TABLE
S2
S1
BC1BC2
L X X
X
H X X
H
X H H X X
X
H XLL H Din
L
H HL H
L
H HL Active
L
H H L L
L
H L H
L
H H L Active
L
H L DinLL X
L
H L DoutHL L Read Dout Active
L
H L
L
OE
W
X X
X X
H H High-Z High-Z
H High-Z
Mode
Non selection
Non selection
Non selection
Write
Read
Write
Read
H
Write
H High-Z
DQ1~8
High-Z
High-Z
High-Z High-Z
High-Z
High-Z
High-Z ActiveHL
DQ9~16
High-Z
High-Z
High-Z
High-ZDout ActiveL
Din ActiveX
Din Active
Icc
Standby
Standby
Standby
Active
ActiveL DoutH High-Z
A0
A1
A16
A17
S1
S2
BC1
BC2
W
OE
MEMORY ARRAY
262144 WORDS
DQ
1
DQ
8
DQ
9
DQ
16
Vcc
GND
MITSUBISHI ELECTRIC
2
2001.06.11 Ver. 2.1
-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
M5M5V416CWG -70HI
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Units
V
cc
VI
VO
Pd
Ta
Tstg
Supply voltage
Input voltage
Output voltage
Power dissipation
Operating
temperature
Storage temperature
Conditions
With respect to GND
With respect to GND
With respect to GND
Ta=25°C
I-version
Ratings
-0.5* ~ +4.6
-0.3* ~ Vcc + 0.3
700
- 40 ~ +85
- 65 ~ +150
* -3.0V in case of AC (Pulse width 30ns)
<
=
DC ELECTRICAL CHARACTERISTICS
-
-
-
-
-
-
-
Limits
Vcc+0.2V
5
0.1
0.2 2
-
-
MaxTypMin
0.4
0.4
±1
±1
4030
10
4030
105
1
20
0.5
Symbol
VIH
VIL
VOH IOH= -0.5mA
VOL IOL=2mA
II
IO
Icc1
Icc2
Icc3
Icc4
Note 1: Direction for current flowing into IC is indicated as positive (no mark)
Note 2: Typical parameter indicates the value for the center of distribution at 2.85V, and is not 100% tested.
Parameter
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
Input leakage current
Output leakage current
Active supply current
( AC,MOS level )
Active supply current
( AC,TTL level )
Stand by supply current
( MOS level )
Stand by supply current
( TTL level )
Conditions
VI =0 ~ Vcc
BC1 and BC2=VIH or S1=VIH or S2=VIL or OE=VIH, VI/O=0 ~ Vcc
BC1 and BC2 0.2V, S1 0.2V, S2 Vcc-0.2V
other inputs 0.2V or Vcc-0.2V
Output - open (duty 100%)
BC1 and BC2=VIL , S1=V IL ,S2=VIH
other pins =V IH or VIL
Output - open (duty 100%)
S1 Vcc - 0.2V,
S2 Vcc - 0.2V,
other inputs = 0 ~ Vcc
S2 0.2V,
BC1 and BC2 Vcc - 0.2V
S1 0.2V, S2 Vcc - 0.2V
BC1 and BC2=VIH or S1=VIH or S2=VIL
Other inputs= 0 ~ Vcc
=
f= 1MHz
f= 1MHz
~ +25°C
~ +40°C
~ +85°C
* -1.0V in case of AC (Pulse width 30ns)
2.2
-0.2 *
2.4
-
V
mW
°C
°C
Units
V
µA
mA
µA
mA
<
=
CAPACITANCE
Symbol
CI
CO
Parameter
Input capacitance
Output capacitance
VI=GND, VI=25mVrms, f=1MHz
VO=GND,VO=25mVrms, f=1MHz
Conditions
MITSUBISHI ELECTRIC
Min
Limits
Max
Units
pF