4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
MITSUBISHI LSIs
123
45678
910111213
1415161718
19202122444342
4140393837
3635343332
3130292827
262524
23
A3S1DQ1
Vcc
GNDWEA2A1A0
DQ3
DQ4
DQ6
DQ7
DQ8
A15
A14
A13
A16
BC1OEBC2A5S2A8A9
A10
A11
DQ9
DQ10
DQ11
Vcc
GND
DQ13
DQ14
DQ16A6A7
A17
BC1
OEA4A3
BC2
S1A5DQ1S2Vcc
GND
WEA8A9
A10
A11
123
45678
910111213
1415161718
19202122444342
4140393837
3635343332
3130292827
262524
23
A2A1A0
DQ3
DQ4
DQ6
DQ7
DQ8
A15
A14
A13
A16
DQ9
DQ10
DQ11
Vcc
GND
DQ13
DQ14
DQ16A6A7
A17
M5M5V416BTP , RT -85L
M5M5V416BTP , RT -70L
M5M5V416BTP , RT -10L
M5M5V416BTP , RT -70H
M5M5V416BTP , RT -85H
M5M5V416BTP , RT -10H
M5M5V416BTP , RT -85LW
M5M5V416BTP , RT -70LW
M5M5V416BTP , RT -10LW
M5M5V416BTP , RT -85HW
M5M5V416BTP , RT -70HW
M5M5V416BTP , RT -10HW
M5M5V416BTP , RT -85LI
M5M5V416BTP , RT -70LI
M5M5V416BTP , RT -10LI
M5M5V416BTP , RT -85HI
M5M5V416BTP , RT -70HI
M5M5V416BTP , RT -10HI
-20 ~ +85°C
1
M5M5V416BTP,RT
DESCRIPTION
The M5M5V416B is a family of low voltage 4-Mbit static RAMs
organized as 262,144-words by 16-bit, fabricated by Mitsubishi's
high-performance 0.25µm CMOS technology.
The M5M5V416B is suitable for memory applications where a
simple interfacing , battery operating and battery backup are the
important design objectives.
M5M5V416BTP,RT are packaged in a 44-pin 400mil thin small
outline package. M5M5V416BTP (normal lead bend type package)
, M5M5V416BRT (reverse lead bend type package) , both types
are very easy to design a printed circuit board.
From the point of operating temperature, the family is divided into
three versions; "Standard", "W-version", and "I-version". Those are
summarized in the part name table below.
Version,
Operating
Part name
temperature
Standard
0 ~ +70°C
W-version
I-version
-40 ~ +85°C
PIN CONFIGURATION
Power
Supply
2.7 ~ 3.6V
2.7 ~ 3.6V
2.7 ~ 3.6V
2.7 ~ 3.6V
2.7 ~ 3.6V
2.7 ~ 3.6V
Access time
max.
70ns
85ns
100ns
70ns
85ns
100ns
70ns
85ns
100ns
70ns
85ns
100ns
70ns
85ns
100ns
70ns
85ns
100ns
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
FEATURES
Single +2.7~+3.6V power supply
Small stand-by current: 0.3µA(3V,typ.)
No clocks, No refresh
Data retention supply voltage=2.0V to 3.6V
All inputs and outputs are TTL compatible.
Easy memory expansion by S1, S2, BC1 and BC2
Common Data I/O
Three-state outputs: OR-tie capability
OE prevents data contention in the I/O bus
Process technology: 0.25µm CMOS
Package: 44 pin 400mil TSOP (II)
Stand-by current Icc (PD), Vcc=3.0V
typical *
Ratings (max.)
70°C 85°C25°C25°C40°C40°C
---
0.3µA
---
0.3µA
---
0.3µA
---
1µA
---
1µA
---
1µA
1µA
1µA3µA
1µA3µA
---
---
3µA
------
------
20µA
10µA
20µA
10µA
20µA
10µA
40µA
20µA
40µA
20µA
* "typical" parameter is sampled, not 100% tested.
A4
Active
current
Icc1
(3.0V, typ.)
---
---
40mA
(10MHz)
5mA
(1MHz)
DQ2
DQ5
A12
DQ15
DQ12
DQ15
DQ12
44P3W-H44P3W-J
MITSUBISHI ELECTRIC
DQ2
DQ5
A12
Pin
A0 ~ A17
DQ1 ~ DQ16
S1
S2
W
OE
BC1
BC2
Vcc
GND
Outline: 44P3W-H/J
NC: No Connection
Function
Address input
Data input / output
Chip select input 1
Chip select input 2
Write control input
Output enable input
Lower Byte (DQ1 ~ 8)
Upper Byte (DQ9 ~ 16)
Power supply
Ground supply
revision-P04, ' 98.12.16
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
MITSUBISHI LSIs
CLOCK
GENERATOR
S2
-
S1
Non selection
Non selection
M5M5V416BTP,RT
FUNCTION
The M5M5V416BTP,RT are organized as 262,144-words
by 16-bit. These devices operate on a single +2.7~3.6V
power supply, and are directly TTL compatible to both
input and output. Its fully static circuit needs no clocks
and no refresh, and makes it useful.
The operation mode are determined by a combination of
the device control inputs BC1 , BC2 , S1, S2 , W and OE.
Each mode is summarized in the function table.
A write operation is executed whenever the low level W
overlaps with the low level BC1 and/or BC2 and the low
level S1 and the high level S2. The address(A0~A17) must
be set up before the write cycle and must be stable during
the entire cycle.
A read operation is executed by setting W at a high level
and OE at a low level while BC1 and/or BC2 and S1 and
S2 are in an active state(S1=L,S2=H).
When setting BC1 at the high level and other pins are in
an active stage , upper-byte are in a selectable mode in
which both reading and writing are enabled, and lower-byte
are in a non-selectable mode. And when setting BC2 at a
high level and other pins are in an active stage, lowerbyte are in a selectable mode and upper-byte are in a
non-selectable mode.
BLOCK DIAGRAM
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
When setting BC1 and BC2 at a high level or S1 at a high
level or S2 at a low level, the chips are in a non-selectable
mode in which both reading and writing are disabled. In this
mode, the output stage is in a high-impedance state, allowing
OR-tie with other chips and memory expansion by BC1, BC2
and S1, S2.
The power supply current is reduced as low as 0.3µA(25°C,
typical), and the memory data can be held at +2V power
supply, enabling battery back-up operation during power
failure or power-down operation in the non-selected mode.
FUNCTION TABLE
S2
S1
BC1 BC2
LXXHigh-ZXX
H
LXXHigh-ZXX
L
HXXHigh-Z
H
XHHXXStandby
X
HXLLHDinHigh-Z Active
L
HHLH
L
HHLActive
L
HHLL
L
HLH
L
HHLActive
L
HLDinLLX
L
HLDoutHLL
L
HL
L
OEDQ1~8
W
XX
HHHigh-Z High-Z
HHigh-Z
Mode
Non selection
Non selection
Write
Read
Write
Read
H
Write
Read
HHigh-Z
High-Z High-Z
High-Z
High-Z
High-ZActiveHL
DQ9~16Icc
High-Z
High-Z
High-Z Standby
High-ZDoutActiveL
DinActiveX
DinActive
DoutActive
Standby
Standby
ActiveLDoutHHigh-Z
A0
A1
A16
A17
BC1
BC2
W
OE
MEMORY ARRAY
262144 WORDS
x 16 BITS
DQ
1
DQ
8
DQ
9
DQ
16
Vcc
GND
MITSUBISHI ELECTRIC
2
revision-P04, ' 98.12.16
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
MITSUBISHI LSIs
3
10
=2mA
f= 10MHz
0 ~ Vcc
f= 10MHz
Typ
<=<=>
=
<
=
Other inputs=0~Vcc
>=>
=
<
=
< 1 >
< 3 >
10
< 2 >
>
=
M5M5V416BTP,RT
ABSOLUTE MAXIMUM RATINGS
Symbol
V
cc
VI
VO
Pd
Ta
Tstg
Parameter
Supply voltage
Input voltage
Output voltage
Power dissipation
Operating
temperature
Storage temperature
DC ELECTRICAL CHARACTERISTICS
Symbol
VIH
VIL
VOH1IOH= -0.5mA
VOH2IOH= -0.05mA
VOLIOL
II
IO
Icc1
Icc2
Icc3
Icc4
Note 1: Direction for current flowing into IC is indicated as positive (no mark)
Note 2: Typical value is for Vcc=3.0V and Ta=25°C
Parameter
High-level input voltage
Low-level input voltage
High-level output voltage 1
High-level output voltage 2
Low-level output voltage
Input leakage current
Output leakage current
Active supply current
( AC,MOS level )
Active supply current
( AC,TTL level )
Stand by supply current
( AC,MOS level )
Stand by supply current
( AC,TTL level )
VI =0 ~ Vcc
BC1 and BC2=VIH or S1=VIH or S2=VIH or OE=VIH, VI/O=0 ~ Vcc
BC1 and BC2 0.2V, S1 0.2V, S2 Vcc-0.2V
other inputs 0.2V or Vcc-0.2V
Output - open (duty 100%)
BC1 and BC2=VIL , S=V IL ,S2=VIH
other pins =V IH or VIL
Output - open (duty 100%)
S1 Vcc - 0.2V,
other inputs = 0 ~ Vcc
S2 0.2V,
other inputs = 0 ~ Vcc
BC1 and BC2 Vcc - 0.2V
S1 0.2V, S2 Vcc - 0.2V
BC1 and BC2=VIH or S1=VIH or S2=VIL
Other inputs= 0 ~ Vcc
Conditions
With respect to GND
With respect to GND
With respect to GND
Ta=25°C
Standard
W-version
I-version
(-L, -H)
(-LW, -HW)
(-LI, -HI)
Conditions
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
Address setup time
Address setup time with respect to W
Byte control 1 setup time
Byte control 2 setup time
Chip select 1 setup time
Chip select 2 setup time
Data setup time
Data hold time
Write recovery time
Output disable time from W low
Output disable time from OE high
Output enable time from W high
Output enable time from OE low
Parameter
70L,70H,70LW
MaxMinMaxMinMaxMin
70
55
0
65
65
65
65
65
35
0
0
25
25
5
5
Limits
85L,85H,85LW
85
60
0
70
70
70
70
70
35
0
0
30
30
5
5
MITSUBISHI ELECTRIC
10L,10H,10LW
100
75
0
85
85
85
85
85
40
0
0
5
5
35
35
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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