Mitsubishi M5M54R16ATP-15, M5M54R16ATP-12, M5M54R16ATP-10, M5M54R16AJ-15, M5M54R16AJ-12 Datasheet

The M5M54R16A is a family of 262144-word by 16-bit
static RAMs, fabricated with the high performance CMOS
process and designed for high speed application. These
devices operate on a single 3.3V supply, and are directly
TTL compatible.
They include a power down feature as well. In write
and read cycles, the lower and upper bytes are able
to be controled either togethe or separately by LB
and UB.

PRELIMINARY

Notice: This is not a final specification.

The operation mode of the M5M54R16A is determined
by a combination of the device control inputs S, W, OE,
LB, and UB. Each mode is summarized in the function
table.
A write cycle is executed whenever the low level W
overlaps with low level LB and/or low level UB and low
level S. The address must be set-up before write cycle
and must be stable during the entire cycle.
The data is latched into a cell on the traling edge of
W, LB, UB or S, whichever occurs first, requiring the
set-up and hold time relative to these edge to be
maintained. The output enable input OE directly
controls the output stage. Setting the OE at a high level,
the output stage is in a high impedance state, and the
data bus contention problem in the write cycle is
eliminated.
A read cycle is excuted by setting W at a high level
and OE at a low level while LB and/or UB and S are in
an active

When setting LB at a high level and other pins are in
an active state, upper-Byte are in a selectable mode
in which both reading and writing are enable, and
lower-Byte are in a non-selectable mode. And when
setting UB at a high level and other pins are in an
active state, lower-Byte are in a selectable mode in
which both reading and writing are enable, and upper­Byte are in a non-selectable mode.
When setting LB and UB at a high level or S at high
level, the chip is in a non-selectable mode in which
both reading and writing are disabled. In this mode,
the output stage is in a high-impedance state,
allowing OR-tie with other chips and memory
expansion by LB, UB and S.
Signal-S controls the power-down feature. When S
goes high, power dissapation is reduced extremely.
The access time from S is equivalent to the address
access time.

(3.3V)

(0V)

(3.3V)

(0V)

Some parametric limits are subject to change.

DESCRIPTION

1998.11.30 Ver.B

MITSUBISHI LSIs

M5M54R16AJ,ATP-10,-12,-15

4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM

PIN CONFIGURATION (TOP VIEW)

FEATURES

•Fast access time M5M54R16AJ,ATP-10 ... 10ns(max)
M5M54R16AJ,ATP-12 ... 12ns(max)
M5M54R16AJ,ATP-15 ... 15ns(max)

•Single +3.3V power supply

•Fully static operation : No clocks, No refresh

•Common data I/O

•Easy memory expansion by S

•Three-state outputs : OR-tie capability

•OE prevents data contention in the I/O bus

•Directly TTL compatible : All inputs and outputs

•Separate control of lower and upper bytes by LB and UB

ADDRESS

INPUTS

CHIP SELECT
INPUT

DATA

INPUTS/

OUTPUTS

DATA

INPUTS/

OUTPUTS

WRITE
CONTROL INPUT

ADDRESS

INPUTS

A0

1
2

A1
A2

3

A3

4

A4

5
6

S

DQ1
DQ2

DQ3

DQ4

VCC

GND
DQ5

DQ6
DQ7

DQ8

A5
A6

A7
A8

A9

7
8

9

10
11

12
13
14

15
16

17

W

18
19
20

21
22

Outline 44P0K

44

A17

A16

A15

OUTPUT

OE

ENABLE INPUT

UB

LB
DQ16

DQ15
DQ14

DQ13

GND

VCC

DQ12
DQ11

DQ10

DQ9

N.C
A14
A13

A12
A11
A10

ADDRESS
INPUTS

BYTE

CONTROL

INPUTS

DATA
INPUTS/

OUTPUTS

DATA
INPUTS/
OUTPUTS

ADDRESS

INPUTS

43
42

41
40

39
38

37
36

35
34

33
32

31
30
29

28
27
26

25
24

23

APPLICATION

High-speed memory system

FUNCTION

MITSUBISHI
ELECTRIC

PACKAGE

M5M54R16AJ .......... 44pin 400mil SOJ

M5M54R16ATP .......... 44pin 400mil TSOP(II)

state. (LB and/or UB=L, S=L)

1

FUNCTION TABLE

UB

2324252627

42

641174039

789101314151638293031323536

37

113312

34

43

44

MITSUBISHI LSIs

M5M54R16AJ,ATP-10,-12,-15

4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM

OE

W

L L

H Read cycle All Bytes

LLH
L L

H

L L
L X

L L X
L

H
X

L
H

X X

BLOCK DIAGRAM

1

A0

2

A1

3

A2

4

A3

5

ADDRESS

INPUTS

CHIP
SELECT INPUT

WRITE
CONTROL INPUT

OUTPUT
ENABLE INPUT

UPPER BYTE
CONTROL INPUT

LOWER BYTE
CONTROL INPUT

A4

A5
A6
A7

A8

A9

S

W

OE

UB

LB

18
19
20
21

22

LB

L

L

L

X

H
X
X

L

H
L

L
H

L
X
H

Read cycle Upper Bytes

H

Read cycle Lower Bytes

L

Write cycle Upper Bytes

L
H

Write cycle Lower Bytes
X
H

X

Mode

Write cycle All Bytes

Output disable

Non selection Stand by

MEMORY ARRAY

1024 ROWS

4096 COLUMNS

COLUMN I/O CIRCUITS

COLUMN ADDRESS
DECODERS

COLUMN INPUT BUFFERS

DQ1~8 DQ9~16

D

OUT

High-impedance Active

D

OUT

D

IN

High-impedance

IN

High-impedance
High-impedance

D

OUT

D

OUT

High-impedance

D

IN

D

IN

High-impedanceD
High-impedance

High-impedance

Active

Active
Active

Active
Active

Active

DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16

V

CC

GND

IccS

DATA
INPUTS/

OUTPUTS

DATA
INPUTS/

OUTPUTS

(3.3V)

(0V)

A14

A13A12A11A10

ADDRESS INPUTS

MITSUBISHI
ELECTRIC

A15

A16

A17

2

ABSOLUTE MAXIMUM RATINGS

Output voltage

(1) MEASUREMENT CONDITION

=0.0V

Output loads

Fig.2 Output load for t , t

Fig.1 Output load

MITSUBISHI LSIs

M5M54R16AJ,ATP-10,-12,-15

4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM

Symbol UnitConditions
V cc
VI

Supply voltage

Input voltage

Parameter

With respect to GND

VO

d

P
Topr
Tstg(bias)

Power dissipation
Operating temperature

Storage temperature(bias)

Ta=25°C

Tstg

*Pulse width ≤3ns, In case of DC: - 0.5V

DC ELECTRICAL CHARACTERISTICS

Symbol Parameter

V

IH

High-level input voltage

V

VOH
VOL

I
IOZ

I

I

ICC3

Low-level input voltage

IL

High-level output voltage
Low-level output voltage
Input current

I

Output current in off-state

Active supply current

CC1

(TTL level)

Stand-by supply current

CC2

(TTL level)

Stand-by current
(MOS level)

IOH = - 4mA
IOL= 8mA

= 0 ~ Vcc

VI
VI (S)= VIH
VO= 0 ~ Vcc

VI (S)= VIL
other inputs VIH or VIL
Output-open(duty 100%)

VI (S)= VIH

VI (S)= Vcc - 0.2V
other inputs VI≤0.2V
or VI≥Vcc - 0.2V

Ratings

*

- 2.0 ~ 4.6

*

- 2.0 ~ Vcc+0.5

*

- 2.0 ~ Vcc
1000

0 ~ 70

- 10 ~ 85

- 65 ~ 150Storage temperature

(Ta=0~70°C, Vcc=3.3V ,unless otherwise noted)

+10%

-5%

Condition

V
V

V

mW

°C
°C

°C

Limits

Min

2.0

2.4

AC(10ns cycle)
AC(12ns cycle)

AC(15ns cycle)
DC

AC(10ns cycle)
AC(12ns cycle)
AC(15ns cycle)

DC

MaxTyp

Vcc+0.3

0.8

0.4
2

2

260
250
230

120

90
70

60
40

10

Unit

V
V

V
V

uA
uA

mA

mA

mA

Note 1: Direction for current flowing into an IC is positive (no mark).

CAPACITANCE

(Ta=0~70°C , Vcc=3.3V ,unless otherwise noted)

Symbol Parameter

CI

Input capacitance

CO

Output capacitance

+10%

-5%

Test Condition Unit

VI =GND,Vi =25mVrms,f=1MHz
Vo =GND,Vo =25mVrms,f=1MHz

Limit

Note 2: CI,CO are periodically sampled and are not 100% tested.

Z0=50Ω

RL=50Ω
VL=1.5V

+10%

-5%

DQ

DQ

255Ω

AC ELECTRICAL CHARACTERISTICS (Ta= 0~70 °C ,VCC=3.3V ,unless otherwise noted)

Input pulse levels ................................... VIH=3.0V,VIL

Input rise and fall time ................................................... 3ns

Input timing reference levels ...................... VIH=1.5V,VIL=1.5V

Output timing reference levels ................ VOH=1.5V, VOL=1.5V

....................................................... Fig1 ,Fig2

OUTPUT

MITSUBISHI
ELECTRIC

MaxTypMin

78pF

pF

5.0V

480Ω

5pF
Including

( )

scope and JIG

en dis

3