Mitsubishi M5M54R08J-15, M5M54R08J-12 Datasheet
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
DESCRIPTION
The M5M54R08J is a family of 524288-word by 8-bit static
RAMs, fabricated with the high performance CMOS silicon gate
process and designed for high speed application.
The M5M54R08J is offered in a 36-pin plastic small outline Jlead package(SOJ).
These device operate on a single 5V supply, and are directly
TTL compatible. They include a power down feature as well.
FEATURES
• Fast access time M5M54R08J-12 •••• 12ns(max)
M5M54R08J-15 •••• 15ns(max)
• Low power dissipation Active
Stand by •••••••••• 5mW(typ)
• Single +5V power supply
• Fully static operation : No clocks, No refresh
• Common data I/O
• Easy memory expansion by S
• Three-state outputs : OR-tie capability
• OE prevents data contention in the I/O bus
• Directly TTL compatible : All inputs and outputs
•••••••••• 550mW(typ)
M5M54R08J-12,-15
PIN CONFIGURATION (TOP VIEW)
1
A0
2
address
inputs
chip select
input
data inputs/
outputs
(5V)
(0V)
data
inputs/
outputs
write control
input
address
inputs
A1
A2
A3
A4
DQ1
DQ2
VCC
GND
DQ3
DQ4
W
A5
A6
A7
A8
A
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
9
M5M54R08J
MITSUBISHI LSIs
1997.11.20 Rev.F
36
NC
35
A18
17
A
A16
A15
output enable
input
DQ7
(0V)
(5V)
5
address
inputs
data
inputs/
outputs
data
inputs/
outputs
address
inputs
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
OES
DQ8
GND
VCC
DQ6
DQ
A14
A13
A12
A11
A10
NC
APPLICATION
High-speed memory units
BLOCK DIAGRAM
A0
1
A1
2
A2
3
A3
address
inputs
A4
A
5
14
A6
15
A7
16
A8
17
S
W 13
OE 31
4
5
6
ROW INPUT BUFFERS
ROW ADDRESS DECODERS
COLUMN I/O CIRCUITS
COLUMN ADDRESS
COLUMN
DECODERS
ADDRESS
DECODERS
COLUMN INPUT BUFFERS
PACKAGE
36pin 400mil SOJ
MEMORY ARRAY
512 ROWS
8192 COLUMNS
Outline 36P0K (SOJ)
OUTPUT BUFFERS
DATA INPUT BUFFERS
11
12
25
26
29
30
10
8
9
27
28
DQ17
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
VCC
GND
data
inputs/
outputs
(5V)
(0V)
20 21
address inputs
22 23 241832 33
MITSUBISHI
ELECTRIC
A16A15A14A13A12A11A10A9
34 35
A16
A17
1
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
FUNCTION
The operation mode of the M5M54R08J is determined by a
combination of the device control inputs S, W and OE. Each
mode is summarized in the function table.
A write cycle is executed whenever the low level W overlaps
with the low level S. The address must be set-up before the
write cycle and must be stable during the entire cycle.
The data is latched into a cell on the trailing edge of W or S,
whichever occurs first, requiring the set-up and hold time
relative to these edge to be maintained. The output enable
input OE directly controls the output stage. Setting the OE at a
high level, the output stage is in a high impedance state, and
the data bus
FUNCTION TABLE
MITSUBISHI LSIs
M5M54R08J-12,-15
contention problem in the write cycle is eliminated.
A read cycle is excuted by setting W at a high level and
OE at a low level while S are in an active state (S=L).
When setting S at high level, the chip is in a nonselectable mode in which both reading and writing are
disable. In this mode, the output stage is in a highimpedance state, allowing OR-tie with other chips and
memory expansion by S.
Signal-S controls the power-down feature. When S goes
high, power dissapation is reduced extremely. The access
time from S is equivalent to the address access time.
S
H
W OE
XX
Mode
Non selection Stand by
High-impedance
L Write ActiveDinLX
L Read
L ActiveHigh-impedance
HH
DoutHL
ABSOLUTE MAXIMUM RATINGS
Symbol
V
cc
VI
V
O
Pd
Topr
T
stg(bias)
T
stg
*Pulse width ≤ 20ns, In case of DC:-0.5V
Parameter
Supply voltage
Input voltage
Output voltage
Power dissipation
Operating temperature
Storage temperature
Storage temperature
With respect to GND
Ta=25 C
(bias)
DC ELECTRICAL CHARACTERISTICS
Symbol Parameter
V
High-level input voltage
IH
V
Low-level input voltage
IL
High-level output voltage
VOH
VOL 0.4
Low-level output voltage
Input current
I
I
I
Output current in off-state
OZ
I
I
I
Active supply current
CC1
(TTL level)
Stand by current
CC2
(TTL level)
Stand by current
CC3
I
OH =-4mA
I
OL= 8mA
V
= 0~Vcc
I
VI (S)= VIH
VO= 0~Vcc
I (S)= VIL
V
other inputs VIH or VIL
Output-open(duty 100%)
VI (S)= VIH
VI (S)= Vcc≥0.2V
other inputs V
or V
I≥Vcc-0.2V
DQ
Icc
Active
Ratings
*
-3.5 ~ 7
*
-3.5 ~ VCC+0.3
*
-3.5 ~ VCC+0.3
1000
0 ~ 70
-10 ~ 85
-65 ~ 150
UnitConditions
V
V
V
mW
C
C
C
(Ta=0 ~ 70 C, Vcc=5V±10% unless otherwise noted)
Condition
Limits
Min
2.2
-0.3
2.4
12ns cycle
AC
15ns cycle
DC
110
12ns cycle
AC
15ns cycle
DC
I≤0.2V
1
MaxTyp
Vcc+0.3
0.8
2
10
170
160
120
85
80
60
10
Unit
V
V
V
V
µA
µA
mA
mA
mA
MITSUBISHI
ELECTRIC
2
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