Mitsubishi M5M54R01J-15, M5M54R01J-12 Datasheet
4194304-BIT (4194304-WORD BY 1-BIT) CMOS STATIC RAM
DESCRIPTION
The M5M54R01J is a family of 4194304-word by 1-bit static
RAMs, fabricated with the high performance CMOS silicon gate
process and designed for high speed application.
The M5M54R01J is offered in a 32-pin plastic small outline Jlead package(SOJ).
These device operate on a single 5V supply, and are directly
TTL compatible. They include a power down feature as well.
FEATURES
• Fast access time M5M54R01J-12 •••• 12ns(max)
M5M54R01J-15 •••• 15ns(max)
• Low power dissipation Active
Stand by •••••••••• 5mW(typ)
• Single +5V power supply
• Fully static operation : No clocks, No refresh
• Test mode is available
• Easy memory expansion by S
• Three-state outputs : OR-tie capability
• OE prevents data contention in the I/O bus
• Directly TTL compatible : All inputs and outputs
•••••••••• 450mW(typ)
M5M54R01J-12,-15
PIN CONFIGURATION (TOP VIEW)
1
A0 32
2
(5V)
(0V)
A1
3
A2
4
A3
5
A4
6
A5
7
8
VCC
9
GND
10
D
11
W
12
A6
13
A7
14
A8
15
A9
16
10
A
Outline 32P0K(SOJ)
M5M54R01J
address
inputs
chip select
input
datainputs
write control
input
address
inputs
MITSUBISHI LSIs
1997.11.20 Rev.F
A21
31
A20
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OES
A14
A
A12
B1/B4
A19
18
A
A17
A
16
output enable
input
(0V)
GND
(5V)
VCC
dataoutputs
Q
A15
13
A11
address
inputs
address
inputs
byte control
input
APPLICATION
High-speed memory units
BLOCK DIAGRAM
A0
1
A1
2
A2
3
A3
address
inputs
B1/B4 17
A4
A
5
A6
12
A7
13
A8
14
S
W
11
OE 26
4
5
6
7
ROW INPUT BUFFERS
ROW ADDRESS DECODERS
COLUMN
ADDRESS
DECODERS
16 18
PACKAGE
32pin 400mil SOJ
MEMORY ARRAY
512 ROWS
8192 COLUMNS
COLUMN I/O CIRCUITS
COLUMN ADDRESS
DECODERS
COLUMN INPUT BUFFERS
19 20 211522 27
A16A15A14A13A12A11A10A9
address inputs
29
A1728A18
30
A19
32
A2031A21
data
Q
23
outputs
OUTPUT BUFFERS
data
D
10
DATA INPUT BUFFERS
8
24
25
inputs/
VCC
(5V)
9
GND
(0V)
MITSUBISHI
ELECTRIC
1
4194304-BIT (4194304-WORD BY 1-BIT) CMOS STATIC RAM
FUNCTION
The operation mode of the M5M54R01J is determined by a
combination of the device control inputs S, W and OE. Each
mode is summarized in the function table.
A write cycle is executed whenever the low level W overlaps
with the low level S. The address must be set-up before the
write cycle and must be stable during the entire cycle.
The data is latched into a cell on the trailing edge of W or S,
whichever occurs first, requiring the set-up and hold time
relative to these edge to be maintained. The output enable
input OE directly controls the output stage. Setting the OE at a
high level, the output stage is in a high impedance state, and
the data bus
contention problem in the write cycle is eliminated.
FUNCTION TABLE
MITSUBISHI LSIs
M5M54R01J-12,-15
A read cycle is excuted by setting W at a high level and OE
at a low level while S are in an active state (S=L).
When setting S at high level, the chip is in a non-selectable
mode in which both reading and writing are disable. In this
mode, the output stage is in a high-impedance state, allowing
OR-tie with other chips and memory expansion by S.
Signal-S controls the power-down feature. When S goes
high, power dissapation is reduced extremely. The access
time from S is equivalent to the address access time.
The RAM works with an organization of 4194304-word by 1
bit,when B1/B4 is low of floating. And an organization of 1048
576-word by 4bit is also obtained for reducing the test time,
when B1/B4 is high.
S
H
L
L
L
W
OE
X
X
LX
HL
HH
Mode
Non selection
High-impedance
Write ActiveDin
Read
High-impedance
High-impedance
ABSOLUTE MAXIMUM RATINGS
Symbol
V
cc
VI
V
O
Pd
Topr
T
stg(bias)
T
stg
*Pulse width ≤ 20ns, In case of DC:-0.5V
Parameter
Supply voltage
Input voltage
Output voltage
Power dissipation
Operating temperature
Storage temperature
Storage temperature
With respect to GND
Ta=25 C
(bias)
DC ELECTRICAL CHARACTERISTICS
Symbol Parameter
V
IH
High-level input voltage
V
IL
Low-level input voltage
VOH
High-level output voltage
VOL 0.4
Low-level output voltage
Input current
I
I
I
Output current in off-state
OZ
Active supply current
I
CC1
(TTL level)
Stand by current
I
CC2
(TTL level)
I
Stand by current
CC3
OH =-4mA
I
I
OL= 8mA
V
= 0~Vcc
I
VI (S)= VIH
VO= 0~Vcc
I (S)= VIL
V
other inputs VIH or VIL
Output-open(duty 100%)
VI (S)= VIH
VI (S)= Vcc≥0.2V
other inputs V
or V
I≥Vcc-0.2V
D
Q
High-impedance
Icc
Stand by
High-impedance
V
V
V
mW
C
C
C
Active
Active
Dout
High-impedance
Ratings
*
-3.5 ~ 7
*
-3.5 ~ VCC+0.3
*
-3.5 ~ VCC+0.3
1000
0 ~ 70
-10 ~ 85
-65 ~ 150
UnitConditions
(Ta=0 ~ 70 C, Vcc=5V±10% unless otherwise noted)
Condition
Limits
Min
2.2
-0.3
2.4
12ns cycle
AC
15ns cycle
DC
90
12ns cycle
AC
15ns cycle
DC
I≤0.2V
1
MaxTyp
Vcc+0.3
0.8
2
10
160
150
100
75
70
50
10
Unit
V
V
V
V
µA
µA
mA
mA
mA
MITSUBISHI
ELECTRIC
2
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