Mitsubishi M5M54R01AJ-15, M5M54R01AJ-12 Datasheet

1998.11.30 Ver.B

The M5M54R01AJ is a family of 4194304-word by 1-bit
static RAMs, fabricated with the high performance CMOS
silicon gate process and designed for high speed
application.
These devices operate on a single 3.3V supply, and are
directly TTL compatible. They include a power down
feature as well.

address

123456789101112131415

16

32313029282726252423222120

19

18

17

address

address

address

byte control

address

address

PRELIMINARY

Notice: This is not a final specification.
Some parametric limits are subject to change

MITSUBISHI LSIs

M5M54R01AJ-12,-15

4194304-BIT (4194304-WORD BY 1-BIT) CMOS STATIC RAM

DESCRIPTION

FEATURES

•Fast access time M5M54R01AJ-12 ... 12ns(max)

M5M54R01AJ-15 ... 15ns(max)

•Single +3.3V power supply

•Fully static operation : No clocks, No refresh

•Easy memory expansion by S

•Three-state outputs : OR-tie capability

•OE prevents data contention in the I/O bus

•Directly TTL compatible : All inputs and outputs

APPLICATION

High-speed memory units

PIN CONFIGURATION (TOP VIEW)

A0
A1

A2

inputs

A3

A4

(0V)

A5

VCC

GND

D

W

A6

chip select

input

(3.3V)

datainputs

write control

input

A7
A8

inputs

A9
A10

Outline 32P0K

PACKAGE

M5M54R01AJ : 32pin 400mil SOJ

A21
A20

A19
A18

A17

A16

output enable

OES

input

(0V)

GND

(3.3V)

VCC
Q

A15

A14
A13
A12

A11

B1/B4

inputs

dataoutputs

inputs

input

BLOCK DIAGRAM

A0

1

A1

2

A2

3

A3

4

A4

inputs

B1/B4 17

A5
A6

12

A7

13

A8

14

A9

S 7

W

11

OE 26

5
6

COLUMN
ADDRESS
DECODERS

16 18

MEMORY ARRAY

1024 ROWS

4096 COLUMNS

COLUMN I/O CIRCUITS

COLUMN ADDRESS

DECODERS

COLUMN INPUT BUFFERS

19 20 211522 27

A16A15A14A13A12A11A10

A1728A18

inputs

MITSUBISHI
ELECTRIC

29

A1930A2031A21

32

23

10

8
24

25

data

Q

outputs

data

D

inputs/

VCC

(3.3V)

9

GND

(0V)

1

The operation mode of the M5M54R01AJ is determined by a
combination of the device control inputs S, W and OE. Each mode is
summarized in the function table.
A write cycle is executed whenever the low level W overlaps with
the low level S. The address must be set-up before the write cycle
and must be stable during the entire cycle.
The data is latched into a cell on the trailing edge of W or S,
whichever occurs first, requiring the set-up and hold time relative to
these edge to be maintained. The output enable input OE directly
controls the output stage. Setting the OE at a high level, the output
stage is in a high impedance state, and the data bus
contention problem in the write cycle is eliminated.

A read cycle is excuted by setting W at a high level and OE at a
low level while S are in an active state (S=L).
When setting S at high level, the chip is in a non-selectable mode
in which both reading and writing are disable. In this mode, the
output stage is in a high-impedance state, allowing OR-tie with
other chips and memory expansion by S.
Signal-S controls the power-down feature. When S goes high,
power dissapation is reduced extremely. The access time from S is
equivalent to the address access time.
The RAM works with an organization of 4194304-word by 1bit,
when B1/B4 is low of floating. And an organization of 1048576-word
by 4bit is also obtained for reducing the test time,when B1/B4 is
high. The pin configuration and function is as same as
M5M54R04AJ.

FUNCTION

FUNCTION TABLE

B1/B4

S W OE

H

L

L
L
L

X X

L

L X

L Read

H L

L ActiveHigh-impedance

H H

MITSUBISHI LSIs

M5M54R01AJ-12,-15

4194304-BIT (4194304-WORD BY 1-BIT) CMOS STATIC RAM

Mode

Non selection Stand by

High-impedance

D

Write ActiveDin

Q
High-impedance
High-impedance

High-impedance

High-impedance

Icc

ActiveDout

ABSOLUTE MAXIMUM RATINGS

Symbol

Vcc
VI
V

O

Pd
Topr
Tstg(bias)
T

stg

* Pulse width≤3ns, In case of DC: - 0.5V

Parameter
Supply voltage
Input voltage
Output voltage

Power dissipation
Operating temperature

Storage temperature(bias)
Storage temperature

With respect to GND

Ta=25°C

DC ELECTRICAL CHARACTERISTICS (Ta=0 ~ 70°C, Vcc=3.3V ,unless otherwise noted)

Symbol Parameter

V

IH

High-level input voltage

V

Low-level input voltage

IL

VOH

High-level output voltage

VOL 0.4

Low-level output voltage
Input current

I

I

I

Output current in off-state

OZ

Active supply current

I

CC1

(TTL level)

Stand by current

I

CC2

(TTL level)

I

Stand by current

CC3

Note 1: Direction for current flowing into an IC is positive (no mark).

I

= - 4mA

OH

IOL = 8mA
VI= 0 ~ Vcc

VI(S)=VIH
VI/O= 0 ~ Vcc

VI(S)=VIL
other inpus=VIH or VIL
Output-open(duty 100%)

VI(S)=VIH

VI(S)=Vcc≥0.2V
other inputs VI≤0.2V
or VI ≥Vcc - 0.2V

Condition

MITSUBISHI
ELECTRIC

Ratings

*

- 2.0 ~ 4.6
*

- 2.0 ~ VCC+0.5
*

- 2.0 ~ VCC

1000
0 ~ 70

- 10 ~ 85

- 65 ~ 150

+10%

- 5%

UnitConditions

V
V

V

mW

°C
°C

°C

Limits

Min

2.0

MaxTyp

Vcc+0.3

0.8

2.4

AC

DC

AC

12ns cycle
15ns cycle

12ns cycle
15ns cycle

180
160

90

70
60

DC 40

10

Unit

V
V

V

V

uA

2
2

uA

mA

mA

mA

2