Mitsubishi M5M512R88DJ-15, M5M512R88DJ-12, M5M512R88DJ-10 Datasheet

M5M512R88DJ-10,-12,-15

PRELIMINARY

Notice: This is not a final specification.

The M5M512R88DJ is a family of 131072-word by 8-bit
static RAMs, fabricated with the high performance CMOS
silicon gate process and designed for high speed
application.
These devices operate on a single 3.3V supply, and are
directly TTL compatible. They include a power down
feature as well.

BLOCK DIAGRAM

123456789101112131415

16

32313029282726252423222120

19

18

17

Some parametric limits are subject to change

DESCRIPTION

1998.6.18 Ver.A

MITSUBISHI LSIs

1048576-BIT (131072-WORD BY 8-BIT) CMOS STATIC RAM

PIN CONFIGURATION (TOP VIEW)

FEATURES

•Fast access time M5M512R88DJ-10 ... 10ns(max)

M5M512R88DJ-12 ... 12ns(max)
M5M512R88DJ-15 ... 15ns(max)

•Low power dissipation Active .................... 297mW(typ)

•Single +3.3V power supply

•Fully static operation : No clocks, No refresh

•Common data I/O

•Easy memory expansion by S

•Three-state outputs : OR-tie capability

•OE prevents data contention in the I/O bus

•Directly TTL compatible : All inputs and outputs

APPLICATION

High-speed memory units

A0

inputs

chip select

input

inputs/

data
outputs

(3.3V)

(0V)

data
inputs/

outputs

write control

input

inputs

A1
A2

A3

S
DQ1
DQ2

VCC

GND

DQ3
DQ4

W

A4

A5

A6

A7

Outline 32P0K

PACKAGE

M5M512R88DJ : 32pin 400mil SOJ

A16
A15
A14

A13

output enable

input

OE

DQ8
DQ7

(0V)

GND

(3.3V)

VCC
DQ6
DQ5
A12

A11
A10
A9
A8

inputs

data
inputs/

outputs

data
inputs/

outputs

inputs

A0

1

A1

2

A2

inputs

A3
A4

13

A5

14

A6

15

A7

16

A8

17

S 5

W 12

OE 28

3
4

MEMORY ARRAY

2048 COLUMNS

COLUMN I/O CIRCUITS

COLUMN ADDRESS

COLUMN

DECODERS

ADDRESS
DECODERS

COLUMN INPUT BUFFERS

19 20

512 ROWS

21

29 301831 32

inputs

MITSUBISHI
ELECTRIC

DQ16
DQ2

7

DQ3

10

DQ4

11

DQ5

22

DQ6

23

DQ7

26

DQ8

27

data
inputs/

outputs

8

VCC

GND

(3.3V)

(0V)

1

24

9

25

A16A15A14A13A12A11A10A9

M5M512R88DJ-10,-12,-15

Output voltage

The operation mode of the M5M512R88DJ is determined by
a combination of the device control inputs S, W and OE.
Each mode is summarized in the function table.
A write cycle is executed whenever the low level W
overlaps with the low level S. The address must be set-up
before the write cycle and must be stable during the entire
cycle.
The data is latched into a cell on the trailing edge of W or
S, whichever occurs first, requiring the set-up and hold time
relative to these edge to be maintained. The output enable
input OE directly controls the output stage. Setting the OE at
a high level, the output stage is in a high impedance state,
and the data bus

A read cycle is excuted by setting W at a high level and
OE at a low level while S are in an active state (S=L).
When setting S at high level, the chip is in a non­selectable mode in which both reading and writing are
disable. In this mode, the output stage is in a high­impedance state, allowing OR-tie with other chips and
memory expansion by S.
Signal-S controls the power-down feature. When S goes
high, power dissapation is reduced extremely. The access
time from S is equivalent to the address access time.

FUNCTION

FUNCTION TABLE

S W OE

H

X X

L

L X

L Read

H L

L ActiveHigh-impedance

H H

Mode

Non selection Stand by
Write ActiveDin

High-impedance

MITSUBISHI LSIs

1048576-BIT (131072-WORD BY 8-BIT) CMOS STATIC RAM

contention problem in the write cycle is eliminated.

DQ

Icc

ActiveDout

ABSOLUTE MAXIMUM RATINGS

Symbol

Vcc
VI
V

O

Pd
Topr
Tstg(bias)
T

stg

* Pulse width≤5ns, In case of DC: - 0.5V

Parameter
Supply voltage
Input voltage

Power dissipation
Operating temperature

Storage temperature(bias)
Storage temperature

With respect to GND

Ta=25°C

DC ELECTRICAL CHARACTERISTICS (Ta=0 ~ 70°C, Vcc=3.3V ,unless otherwise noted)

Symbol Parameter

V

IH

High-level input voltage

V

Low-level input voltage

IL

VOH

High-level output voltage

VOL 0.4

Low-level output voltage
Input current

I

I

I

Output current in off-state

OZ

Active supply current

I

CC1

(TTL level)

Stand by current

I

CC2

(TTL level)

I

Stand by current

CC3

Note 1: Direction for current flowing into an IC is positive (no mark).

I

= - 4mA

OH

IOL = 8mA
VI= 0 ~ Vcc

VI(S)=VIH
VI/O= 0 ~ Vcc

VI(S)=VIL
other inpus=VIH or VIL
Output-open(duty 100%)

VI(S)=VIH

VI(S)=Vcc≥0.2V
other inputs VI≤0.2V
or VI ≥Vcc - 0.2V

Condition

MITSUBISHI
ELECTRIC

Ratings

*

- 2.0 ~ 4.6
*

- 2.0 ~ VCC+0.5
*

- 2.0 ~ VCC

1000
0 ~ 70

- 10 ~ 85

- 65 ~ 150

+10%

- 5%

10ns cycle
12ns cycle

AC

15ns cycle

DC

10ns cycle
12ns cycle

AC

15ns cycle

DC 30

UnitConditions

Min

2.0

2.4

V
V

V

mW

°C
°C

°C

Limits

90

MaxTyp

Vcc+0.3

0.8

180
170

160

100

60
55

50

10

Unit

V
V

V

V

uA

2
2

uA

mA

mA

mA

2