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M5M51016RT-70L
Datasheet
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Mitsubishi M5M51016RT-70LL, M5M51016RT-70L, M5M51016RT-10LL-I, M5M51016RT-10L-I, M5M51016BTP-10LL-I Datasheet

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MITSUBISHI LSIs
1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM
MITSUBISHI ELECTRIC
M5M51016BTP,RT-70L,-10L-I,
-70LL,-10LL-I
9 Jul ,1997
MITSUBISHI LSIs
1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM
M5M51016BTP,RT-70L,-10L-I,
-70LL,-10LL-I
1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16 17 18 19
A12
NC
A7 A6 A5 A4 A3 A2 A1 A0 CS
(0V)GND
OE NC DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8
ADDRESS
INPUTS
CHIP SELECT
INPUT
OUTPUT ENABLE
INPUT
DATA
INPUTS/
OUTPUTS
BC1
NC
BC2
A14 A15 A13 W A8 A9 A11 A10
GND(0V)
NC
VCC(5V)
DQ16 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9
BYTE CONTROL INPUTS
ADDRESS INPUTS
WRITE CONTROL
INPUTS
ADDRESS INPUTS
DATA INPUTS/ OUTPUTS
1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16 17 18 19
A12
NC
A7 A6 A5 A4 A3 A2 A1 A0 CS GND(0V)
OE NC DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
DQ8
BC1
NC
BC2 A14 A15 A13
W
A8 A9 A11 A10
(0V)GND
NC DQ16 DQ15
DQ14
DQ13 DQ12 DQ11 DQ10 DQ9
(5V)VCC
DATA
INPUTS/
OUTPUTS
ADDRESS
INPUTS
ADDRESS
INPUTS
BYTE
CONTROL
INPUTS
WRITE
CONTROL
INPUTS
ADDRESS INPUTS
CHIP SELECT INPUT
OUTPUT ENABLE INPUT
DATA INPUTS/ OUTPUTS
Outline 44P3W - H (400mil TSOP Normal Bend)
PIN CONFIGURATION (TOP VIEW)
NC : NO CONNECTION
DESCRIPTION
The M5M51016BTP, RT are a 1048576-bit CMOS static RAM organized as 65536 word by 16-bit which are fabricated using high-performance triple polysilicon CMOS technology. The use of resistive load NMOS cells and CMOS periphery result in a high density and low power static RAM. They are low stand-by current and low operation current and ideal for the battery back-up application. The M5M51016BTP,RT are packaged in a 44-pin thin small outline package which is a high reliability and high density surface mount device (SMD). Two types of devices are available. M5M51016BTP(normal lead bend type package), M5M51016BRT (reverse lead bend type package). Using both types of devices, it becomes very easy to design a printed circuit board.
FEATURES
M5M51016BTP,RT-70LL
Single +5.0V power supply Low stand-by current 0.3µA (typ.) Directly TTL compatible : All inputs and outputs Easy memory expansion and power down by CS, BC1 & BC2 Data hold on +2V power supply Three-state outputs : OR-tie capability OE prevents data contention in the I/O bus Common data I/O Package M5M51016BTP,RT
APPLICATION
Small capacity memory units
M5M51016BTP,RT-70L
Type name
Access time
(max)
Active
(max)
stand-by
(max) 200µA
(VCC = 5.5V) 40µA
(VCC = 5.5V)
0.3µA (VCC = 3.0V, typ)
30mA
(1MHz)
Power supply current
100ns
70ns
44pin 400mil TSOP(II)
..............................
M5M51016BTP
M5M51016BRT
1
Outline 44P3W - J (400mil TSOP Reverse Bend)
9 Jul ,1997
100ns
M5M51016BTP,RT-10L
M5M51016BTP,RT-10LL
70ns
MITSUBISHI LSIs
1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM
MITSUBISHI ELECTRIC
M5M51016BTP,RT-70L,-10L-I,
-70LL,-10LL-I
9 Jul ,1997
CS BC1 BC2 W OE Mode
Non selection
DQ1~8 DQ9~16
Stand-byHigh-Z
ICC
L X X X X High-Z
Non selection Stand-byHigh-ZX H H X X High-Z
Upper-Byte Write ActiveHigh-Z
H H L L X
Din
Upper-Byte Read ActiveHigh-ZH H L H L Dout
ActiveHigh-ZH H L H H High-Z ActiveDin
H L H L X High-Z
ActiveDoutH L H H L High-Z
Lower-Byte Write Lower-Byte Read
ActiveHigh-Z
H
L H H High-ZH
ActiveH L L XL
Din Din
Word Write
ActiveH L H LL Dout Dout
Word Read
ActiveHigh-Z
H
L H H High-ZL
The operation mode of the M5M51016B series are determined by a combination of the device control inputs BC1, BC2, CS, W and OE. Each mode is summarized in the function table. A write cycle is executed whenever the low level W overlaps with the low level BC1 and/or BC2 and the high level CS. The address must be set up before the write cycle and must be stable during the entire cycle. The data is latched into a cell on the trailing edge of W, BC1, BC2 or CS, whichever occurs first, requiring the set-up and hold time relative to these edge to be maintained. The output enable input OE directly controls the output stage. Setting the OE at a high level, the output stage is in a high-impedance state, and the databus contention problem in the write cycle is eliminated. A read cycle is executed by setting W at a high level and OE at a low level while BC1 and/or BC2 and CS are in an active state. (BC1 and/or BC2=L,CS=H) When setting BC1 at a high level and the other pins are in an active state, upper-Byte are in a selectable mode in which both reading and writing are enabled, and lower-Byte are in a non-selectable mode.And when setting BC2 at a high level and the other pins are in an active state, lower-Byte are in a selectable mode and upper -Byte are in a non-selectable mode.
When setting BC1 and BC2 at a high level or CS at a low level, the chips are in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips and memory expansion by BC1, BC2 and CS. The power supply current is reduced as low as the stand-by current which is specified as ICC3 or ICC4, and the memory data can be held at +2V power supply, enabling battery back-up operation during powerfailure or power-down operation in the non-selected mode.
A1 9 A3
7
A6
4
A7
3
A12 A14
A1540
A13 39
A8
ADDRESS INPUT
BUFFER
ROW DECODER
A0 10
A4 6 A2 8 A5 5
A9 36
A10 34 A11 35
ADDRESS
INPUT
BUFFER
COLUMN
DECODER
BLOCK
DECODER 11 43 42
CS
BC1 BC2
W
OE
DQ1
DQ2
DQ3 18 DQ4 19
DQ5 20 DQ6 21 DQ7 22 DQ8
DQ9 25
DQ10 26
DQ11 27
DQ12 28
DQ13 29
DQ14 30
DQ15 31
DQ16
OUTPUT BUFFEROUTPUT BUFFER
INPUT
DATA
CONTROL
INPUT
DATA
CONTROL
SENSE AMP. SENSE AMP.
CLOCK GENERATOR
65536 WORDS x16 BITS
( 1024 ROWS x 256 COLUMNS x 4 BLOCKS )
ADDRESS
CHIP SELECT
INPUT
BYTE
CONTROL
INPUTS
WRITE CONTROL
INPUT
OUTPUT ENABLE
INPUT
DATA INPUTS/
OUTPUTS
Vcc
GND(0V) 12 GND(0V)
INPUTS
BLOCK DIAGRAM
2
FUNCTION
(High-Z=High-impedance)
ADDRESS
INPUT
BUFFER
2
MITSUBISHI LSIs
1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM
MITSUBISHI ELECTRIC
M5M51016BTP,RT-70L,-10L-I,
-70LL,-10LL-I
9 Jul ,1997
ABSOLUTE MAXIMUM RATINGS
Parameter Supply voltage Input voltage
Output voltage Power dissipation Operating temperature Storage temperature
Unit
V V V
W
Conditions
With respect to GND
Ta=25 1
– 40 ~ 85 – 65 ~ 150
RatingsSymbol Vcc VI VO
Pd
Topr Tstg
DC ELECTRICAL CHARACTERISTICS
(Ta= - 40 ~85 , Vcc=5.0V 10 %, unless otherwise noted)
– 0.3 ~ 7
0 ~ Vcc
* –3.0V in case of AC ( Pulse width 50ns )
3
VIH VIL
VOH1
Symbol Parameter
V V V
Max
Vcc+0.3V
0.8
Typ
Limits
Min
2.2
– 0.3*
2.4
Test conditions Unit
High-level input voltage
Low-level input voltage
High-level output voltage 1
VOL
I
I
ICC1W
V
µA µA
0.4Low-level output voltage
Input current Output current in off-state
IO
mA
95
IOH = – 1mA IOH = – 0.1mA IOL = 2mA
VI =0 ~ Vcc BC1 and BC2 = VIH or CS = VIL or
OE = VIH, VI/O = 0 ~ Vcc
1
Min cycle
1MHz
mA
30
VOH2
High-level output voltage 2 Vcc–0.5V
V
Active supply current (AC,MOS level)
Word operation (16bit)
ICC2W
<
– 0.3* ~ Vcc + 0.3
C
o
C
o
C
o
C
o
+
_
1
+
_
ICC1B
mA
Min cycle
1MHz
mA
Active supply current (AC,MOS level)
Byte operation (8bit)
15
70
CC3I
3
Stand-by current
mA
* –3.0V in case of AC ( Pulse width 30ns )
Stand-by current
200
-L
-LL
40
CC4
I
2) BC1,BC2 Vcc - 0.2V,
other inputs = 0~Vcc
BC1 and BC2 = VIH or CS = VIL,
other inputs = 0~Vcc
1) CS 0.2V, other inputs = 0~Vcc
CS Vcc - 0.2V
<
>
>
µA
µA
<
+
_
CAPACITANCE
Symbol
Parameter
Test conditions
pF
pF
Unit
Max
6
8
TypMin
Limits
VI=GND, VI=25mVrms, f=1MHz
VO=GND,VO=25mVrms, f=1MHz
Input capacitance ( except BC1,BC2)
Output capacitance
CI
CO
(Ta= - 40 ~ 85 , Vcc=5.0V 10 %, unless otherwise noted)
Note 1: Direction for current flowing into an IC is positive (no mark).
2: Typical value is Vcc = 5.0V, Ta = 25
pF
9VI=GND, VI=25mVrms, f=1MHzInput capacitance ( BC1,BC2 )
CIBC
C
o
C
o
+
_
Active supply current (AC,TTL level)
Word operation (16bit)
Min cycle
1MHz
mA
Min cycle
1MHz
mA
Active supply current (AC,TTL level)
Byte operation (8bit)
(BC1 = VIH and BC2 = VIL) or (BC1 = VIL and BC2 = VIH),
CS = VIH other inputs = VIH or VIL Output-open(duty 100%)
15
70
ICC2B
BC1 and BC2 = VIL, CS = VIH
other inputs = VIH or VIL
Output-open(duty 100%)
BC1 and BC2 0.2V, CS Vcc - 0.2V
other inputs 0.2V or Vcc - 0.2V
Output-open(duty 100%)
<
>
<
(BC1 Vcc - 0.2V and BC2 0.2V) or (BC1 0.2V and BC2 Vcc - 0.2V), CS Vcc - 0.2V other inputs 0.2V or Vcc - 0.2V
Output-open(duty 100%)
> <
< >
>
<
100
30
mA
mA
63 7
35
38
66
10
MITSUBISHI LSIs
1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM
MITSUBISHI
ELECTRIC
M5M51016BTP,RT-70L,-10L-I,
-70LL,-10LL-I
9 Jul ,1997
(2) READ CYCLE
(3) WRITE CYCLE
Symbol
Parameter
tCR Read cycle time
Address access time
Unit
ns ns ns ns ns ns ns ns ns ns ns ns
tCW
tw(W)
tsu(A)
ten(OE)
tsu(BC1) tsu(BC2 ) tsu(CS) tsu(D) th(D) trec(W) tdis(W) tdis(OE) ten(W)
Symbol Parameter
Write cycle time Write pulse width
Unit
ns ns ns ns ns ns ns ns ns ns ns ns ns
Max
Min
MaxMin
Limits
ta(BC1) ta(BC2) ta(CS) ta(OE) tdis(BC1) tdis(BC2) tdis(CS) tdis(OE) ten(BC1) ten(BC2)
ta(A)
Limits
ten(CS) ten(OE)
ns ns
tsu(A-WH)
ns
tv(A)
100
Address set up time 0 Address set up time with respect to W
85
75
Data set up time 40 Data hold time 0
Byte control 1 setup time 85
Chip select set up time
85
5
Byte control 2 setup time
85
Write recovery time
0
Output enable time from W high
5Output enable time from OE low
Output disable time from W low Output disable time from OE high
Output enable access time
Output disable time after CS low
100
Byte control 1 access time
Chip select access time
Output enable time after CS high
Data valid time after address
Byte control 2 access time
Output disable time after BC1 high Output disable time after BC2 high
Output disable time after OE high Output enable time after BC1 low Output enable time after BC2 low
Output enable time after OE low
50
35
100 100
100
10
10
100
35 35
35 10 10
5
35
35
AC ELECTRICAL CHARACTERISTICS (Ta = - 40 ~ 85 , VCC = 5.0V 10 %, unless otherwise noted )
(1) MEASUREMENT CONDITIONS
Input pulse level Input rise and fall time Reference level
Transition is measured 500mV from steady state voltage. ( for ten, tdis )
Output loads
VIH = 2.4V, VIL = 0.6V 5ns VOH = 1.5V, VOL = 1.5V Fig.1,CL =100pF(-10L,-10LL) CL = 30pF (-70L,-70LL) CL = 5pF ( for ten, tdis )
......................
..............
........................
............................
ns
M5M51016B
-10L,-10LL
M5M51016B
-10L,-10LL
4
C
o
+
_
MaxMin
70
70
10
10
25
10 10
5
M5M51016B
-70L,-70LL
70 70 70
35
25 25 25
MaxMin
70
5
25 25
5
M5M51016B
-70L,-70LL
55
65
0 65 65
65
30 0 0
Fig.1 Output load
CL ( Including scope and JIG )
990Ω
1.8kΩ
VCC
DQ
+
_
MITSUBISHI LSIs
1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM
MITSUBISHI ELECTRIC
M5M51016BTP,RT-70L,-10L-I,
-70LL,-10LL-I
9 Jul ,1997
ten (W)
Read cycle
Write cycle (W control mode)
(4) TIMING DIAGRAMS
DATA VALID
(Note 3)
(Note 3)
ta(A)
ta (BC1) or ta (BC2)
ten (BC2)
tv (A)
ta (CS)
ten (CS)
tdis (BC1) or tdis (BC2)
tdis (CS)
ta (OE)
ten (OE)
tdis (OE)
(Note 3)
(Note 3)
(Note 3)
(Note 3)
tCR
th (D)
tsu (D)
DQ1~16
BC1 and/or BC2
tsu (BC1) or tsu (BC2)
CS
OE
tsu (CS)
tsu (A-WH)
ten(OE)
tdis (OE)
(Note 3)
(Note 3)
(Note 3)
(Note 3)
W
tw (W)
trec (W)
tsu (A)
tdis (W)
tCW
ten (BC1)
W = "H" level
A0~15
DQ1~16
BC1 and/or BC2
CS
OE
A0~15
DATA IN STABLE
5
MITSUBISHI LSIs
1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM
MITSUBISHI ELECTRIC
M5M51016BTP,RT-70L,-10L-I,
-70LL,-10LL-I
9 Jul ,1997
Write cycle ( BC control mode)
Note 3: Hatching indicates the state is "don't care".
4: Writing is executed while CS high overlaps BC1 and/or BC2 low and W low.
6: Don't apply inverted phase signal externally when DQ pin is output mode.
Write cycle (CS control mode)
tsu (BC1) or tsu (BC2)
(Note 3) (Note 3)
trec (W)
th (D)
tCW
(Note 5)
(Note 3)
(Note 3)
tsu (A)
(Note 4)
tsu (D)
th (D)
tCW
(Note 5)
(Note 3)
(Note 3)
tsu (CS) trec (W)tsu (A)
(Note 4)
(Note 3) (Note 3)
tsu (D)
5: When the falling edge of W is simultaneously or prior to the falling edge of BC1 and/or BC2 or rising edge of CS, the outputs are maintained in the high impedance state.
DATA IN STABLE
DATA IN STABLE
DQ1~16
BC1 and/or BC2
CS
W
A0~15
DQ1~16
BC1 and/or BC2
CS
W
A0~15
6
MITSUBISHI LSIs
1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM
MITSUBISHI ELECTRIC
M5M51016BTP,RT-70L,-10L-I,
-70LL,-10LL-I
9 Jul ,1997
(Ta = - 40 ~ 85 , unless otherwise noted)
Symbol Parameter
V V
MaxTyp
Limits
Min
Test conditions Unit
µA
0.2V
t rec (PD)
4.5V
V
(3) POWER DOWN CHARACTERISTICS
BC control mode
CS control mode
POWER DOWN CHARACTERISTICS
2.0
(1) ELECTRICAL CHARACTERISTICS
100
2.2
0.8
0.2
-LL
-L
(Note 7)
0.3
20
Power down set up time Power down recovery time
(2) TIMING REQUIREMENTS (Ta = - 40 ~ 85 , unless otherwise noted )
VCC (PD) VI (BC)
VI (CS)
ICC (PD)
Power down supply voltage Byte control input BC1 & BC2
Chip select input CS
Power down supply current
4.5V VCC(PD) VCC(PD) 4.5V
VCC = 3V
tsu (PD) trec (PD)
Symbol Parameter
ns
MaxTyp
Limits
Min
Test conditions Unit
0 5
ms
4.5V
t su (PD)
0.2V
2.2V
t su (PD)
4.5V
4.5V
2.2V
t rec (PD)
VCC
BC1 & BC2
VCC
CS
7
C
o
<
<
1) CS 0.2V
CS VCC 0.2V,other inputs=0~3V
2) BC1 & BC2 Vcc 0.2V,
other inputs = 0 ~ 3V
>
>
<
Note7. ICC (PD) = 1µA in case of Ta = 25
C
o
C
o
BC1 & BC2 VCC 0.2V
>
CS 0.2V
<
VCC(PD)
2.2V VCC(PD)
2.0V VCC(PD) 2.2V
< <
<
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