Mitsubishi M5M51016RT-12VLL-I, M5M51016RT-12VL-I, M5M51016BTP-12VLL-I, M5M51016BTP-12VL-I Datasheet
9 Jul ,1997
MITSUBISHI LSIs
MITSUBISHI LSIs
M5M51016BTP,RT-12VL-I,
M5M51016BTP,RT-12VL-I,
1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM
1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM
9 Jul ,1997
-12VLL-I
-12VLL-I
DESCRIPTION
The M5M51016BTP, RT are a 1048576-bit CMOS static RAM
organized as 65536 word by 16-bit which are fabricated using
high-performance triple polysilicon CMOS technology. The use of
resistive load NMOS cells and CMOS periphery result in a high
density and low power static RAM.
They are low stand-by current and low operation current and ideal
for the battery back-up application.
The M5M51016BTP,RT are packaged in a 44-pin thin small
outline package which is a high reliability and high density surface
mount device (SMD). Two types of devices are available.
M5M51016BTP(normal lead bend type package), M5M51016BRT
(reverse lead bend type package). Using both types of devices, it
becomes very easy to design a printed circuit board.
FEATURES
Type name
M5M51016BTP,RT-12VL
M5M51016BTP,RT-12VLL
Access time
(max)
120ns
120ns
Single +3.0V power supply
Low stand-by current 0.3É A (typ.)
Directly TTL compatible : All inputs and outputs
Easy memory expansion and power down by CS, BC1 & BC2
Data hold on +2V power supply
Three-state outputs : OR-tie capability
OE prevents data contention in the I/O bus
Common data I/O
Package
M5M51016BTP,RT
..............................
Power supply current
Active
(max)
stand-by
(max)
120µA
(VCC = 3.6V)
12mA
(1MHz)
24µA
(VCC = 3.6V)
0.3µA
(VCC = 3.0V,
typ)
44pin 400mil TSOP(II)
APPLICATION
Small capacity memory units
PIN CONFIGURATION (TOP VIEW)
ADDRESS
INPUTS
CHIP SELECT
INPUT
OUTPUT ENABLE
(0V)GND
INPUT
DATA
INPUTS/
OUTPUTS
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
CS
OE
NC
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
1
2
3
4
5
6
7
8
M5M51016BTP
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
NC
43
BC1
42
BC2
41
A14
40
A15
39
A13
38
W
37
A8
36
A9
35
A11
34
A10
33
GND(0V)
32
NC
31
DQ16
30
DQ15
29
DQ14
28
DQ13
27
DQ12
26
DQ11
25
DQ10
24
DQ9
23
VCC(5V)
Outline 44P3W - H (400mil TSOP Normal Bend)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
CS
GND(0V)
OE
NC
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
BYTE
CONTROL
INPUTS
ADDRESS
INPUTS
WRITE
CONTROL
INPUTS
ADDRESS
INPUTS
DATA
INPUTS/
OUTPUTS
NC
BC1
BC2
A14
A15
A13
W
A8
A9
A11
A10
(0V)GND
NC
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
(5V)VCC
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
M5M51016BRT
Outline 44P3W - J (400mil TSOP Reverse Bend)
NC : NO CONNECTION
BYTE
CONTROL
INPUTS
ADDRESS
INPUTS
WRITE
CONTROL
INPUTS
ADDRESS
INPUTS
DATA
INPUTS/
OUTPUTS
ADDRESS
INPUTS
CHIP SELECT
INPUT
OUTPUT ENABLE
INPUT
DATA
INPUTS/
OUTPUTS
MITSUBISHI
ELECTRIC
1
MITSUBISHI LSIs
9 Jul ,1997
M5M51016BTP,RT-12VL-I,
-12VLL-I
1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM
FUNCTION
The operation mode of the M5M51016B series are determined by
a combination of the device control inputs BC1, BC2, CS, W and
OE. Each mode is summarized in the function table.
A write cycle is executed whenever the low level W overlaps with
the low level BC1 and/or BC2 and the high level CS. The address
must be set up before the write cycle and must be stable during
the entire cycle.
The data is latched into a cell on the trailing edge of W, BC1, BC2
or CS, whichever occurs first, requiring the set-up and hold time
relative to these edge to be maintained. The output enable input
OE directly controls the output stage. Setting the OE at a high
level, the output stage is in a high-impedance state, and the
databus contention problem in the write cycle is eliminated.
A read cycle is executed by setting W at a high level and OE at a
low level while BC1 and/or BC2 and CS are in an active state.
(BC1 and/or BC2=L,CS=H)
When setting BC1 at a high level and the other pins are in an
active state, upper-Byte are in a selectable mode in which both
reading and writing are enabled, and lower-Byte are in a
non-selectable mode.And when setting BC2 at a high level and the
other pins are in an active state, lower-Byte are in a selectable
mode and upper -Byte are in a non-selectable mode.
When setting BC1 and BC2 at a high level or CS at a low level,
the chips are in a non-selectable mode in which both reading and
writing are disabled.
In this mode, the output stage is in a high-impedance state,
allowing OR-tie with other chips and memory expansion by BC1,
BC2 and CS. The power supply current is reduced as low as the
stand-by current which is specified as ICC3 or ICC4, and the memory
data can be held at +2V power supply, enabling battery back-up
operation during powerfailure or power-down operation in the
non-selected mode.
CS BC1 BC2 W OE Mode
L X X X X High-Z
Non selection
DQ1~8 DQ9~16
Non selection Stand-byHigh-ZX H H X X High-Z
H H L L X
Upper-Byte Write ActiveHigh-Z
Upper-Byte Read ActiveHigh-ZH H L H L Dout
Din
ICC
Stand-byHigh-Z
ActiveHigh-ZH H L H H High-Z
H L H L X High-Z
L H H High-ZH
H
Lower-Byte Write
Lower-Byte Read
Word Write
Din Din
Word Read
L H H High-ZL
H
(High-Z=High-impedance)
ActiveDin
ActiveDoutH L H H L High-Z
ActiveHigh-Z
ActiveH L L XL
ActiveH L H LL Dout Dout
ActiveHigh-Z
BLOCK DIAGRAM
A1 9
A3
A6
A7
A12
41
A14
A1540
A13 39
A8
37
INPUT
BYTE
INPUT
INPUT
A9 36
A0 10
A4 6
A2 8
A5 5
A10 34
A11 35
CS
BC1
BC2
W
OE
11
43
42
38
13
ADDRESS
INPUTS
CHIP SELECT
CONTROL
INPUTS
WRITE CONTROL
OUTPUT ENABLE
DQ1
15
DQ2
7
4
3
2
ADDRESS INPUT
BUFFER
ADDRESS
INPUT
BUFFER
ADDRESS
INPUT
BUFFER
ROW DECODER
COLUMN
BLOCK
65536 WORDS x16 BITS
DECODER
DECODER
( 1024 ROWS
x 256 COLUMNS
x 4 BLOCKS )
CLOCK
GENERATOR
SENSE AMP. SENSE AMP.
OUTPUT BUFFEROUTPUT BUFFER
INPUT
DATA
CONTROL
INPUT
DATA
CONTROL
16
DQ3
17
18 DQ4
DQ5
19
20 DQ6
21 DQ7
22 DQ8
24
DQ9
25
DQ10
26
DQ11
27
DQ12
28
DQ13
29
DQ14
30
DQ15
31
DQ16
23
Vcc
33
GND(0V)
12 GND(0V)
DATA
INPUTS/
OUTPUTS
MITSUBISHI
ELECTRIC
2
ABSOLUTE MAXIMUM RATINGS
Parameter
Vcc
VI
VO
Pd
Topr
Tstg
* –3.0V in case of AC ( Pulse width 50ns )
Supply voltage
Input voltage
Output voltage
Power dissipation
Operating temperature
Storage temperature
<
MITSUBISHI LSIs
9 Jul ,1997
M5M51016BTP,RT-12VL-I,
-12VLL-I
1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM
Conditions
RatingsSymbol
– 0.3 ~ 4.6
With respect to GND
o
C
Ta=25 1
– 0.3* ~ Vcc + 0.3
0 ~ Vcc
– 40 ~ 85
– 65 ~ 150
Unit
V
V
V
W
o
C
o
C
DC ELECTRICAL CHARACTERISTICS
(Ta=– 40 ~ 85 , Vcc=2.7V ~ 3.6V, unless otherwise noted)
Symbol Parameter
VIH
VIL
VOH1
VOH2
High-level input voltage
Low-level input voltage
High-level output voltage 1
High-level output voltage 2
VOL
I
IO
ICC1W
ICC2W
ICC1B
I
Input current
Output current in off-state
Word operation (16bit)
Active supply current
(AC,TTL level)
Byte operation (8bit)
Active supply current
ICC2B
CC3
I
I
CC4
* –3.0V in case of AC ( Pulse width 30ns )
CAPACITANCE
Symbol
CI
(AC,TTL level)
Stand-by current
<
(Ta=– 40 ~ 85 , Vcc=2.7V ~ 3.6V, unless otherwise noted)
o
C
Parameter
Input capacitance ( except BC1,BC2)
CIBC
CO
Note 1: Direction for current flowing into an IC is positive (no mark).
Output capacitance
2: Typical value is Vcc = 3.3V, Ta = 25
o
C
o
C
Test conditions Unit
IOH = –1mA
IOH = – 0.1mA
IOL = 2mA
VI =0 ~ Vcc
BC1 and BC2 = VIH or CS = VIL or
OE = VIH, VI/O = 0 ~ Vcc
BC1 and BC2 = VIL, CS = VIH
other inputs = VIH or VIL
Output-open(duty 100%)
(BC1 = VIH and BC2 = VIL)
or (BC1 = VIL and BC2 = VIH),
CS = VIH
other inputs = VIH or VIL
Output-open(duty 100%)
<
1) CS 0.2V, other inputs = 0~Vcc
2) BC1,BC2 Vcc - 0.2V,
BC1 and BC2 = VIH or CS = VIL,
other inputs = 0~Vcc
>
>
CS Vcc - 0.2V
other inputs = 0~Vcc
Test conditions
VI=GND, VI=25mVrms, f=1MHz
VO=GND,VO=25mVrms, f=1MHz
Min
cycle
1MHz
Min
cycle
1MHz
-VL
-VLL
Min
2.0
– 0.3*
2.4
Vcc–0.5V
Limits
Typ
27
5
20
3
Limits
TypMin
Max
Vcc+0.3V
0.6
0.4Low-level output voltage
+
_
1
+
_
1
50
12
30
10
120
24
1Stand-by current
Max
6
9VI=GND, VI=25mVrms, f=1MHzInput capacitance ( BC1,BC2 )
8
V
V
V
V
V
µA
µA
mA
mA
mA
mA
µA
µA
mA
Unit
pF
pF
pF
MITSUBISHI
ELECTRIC
3
Loading...