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M5M51016BRT-12VL-I
Datasheet
7 pgs85.5 Kb0

Mitsubishi M5M51016BRT-12VLL-I, M5M51016BRT-12VL-I Datasheet

MITSUBISHI LSIs
1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM
MITSUBISHI ELECTRIC
9 Jul ,1997
M5M51016BTP,RT-12VL-I,
-12VLL-I
MITSUBISHI LSIs
1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM
M5M51016BTP,RT-12VL-I,
-12VLL-I
1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16 17 18 19
A12
NC
A7 A6 A5 A4 A3 A2 A1 A0 CS
(0V)GND
OE NC DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8
ADDRESS
INPUTS
CHIP SELECT
INPUT
OUTPUT ENABLE
INPUT
DATA
INPUTS/
OUTPUTS
BC1
NC
BC2
A14 A15 A13 W A8 A9 A11
A10 GND(0V) NC
VCC(5V)
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
BYTE CONTROL INPUTS
ADDRESS INPUTS
WRITE CONTROL
INPUTS
ADDRESS INPUTS
DATA INPUTS/ OUTPUTS
1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16 17 18 19
A12
NC
A7 A6 A5 A4 A3 A2 A1 A0 CS GND(0V)
OE NC DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
DQ8
BC1
NC
BC2 A14 A15 A13
W
A8 A9 A11 A10
(0V)GND
NC DQ16 DQ15
DQ14
DQ13 DQ12 DQ11 DQ10 DQ9
(5V)VCC
DATA
INPUTS/
OUTPUTS
ADDRESS
INPUTS
ADDRESS
INPUTS
BYTE
CONTROL
INPUTS
WRITE
CONTROL
INPUTS
ADDRESS INPUTS
CHIP SELECT INPUT
OUTPUT ENABLE INPUT
DATA INPUTS/ OUTPUTS
Outline 44P3W - H (400mil TSOP Normal Bend)
PIN CONFIGURATION (TOP VIEW)
NC : NO CONNECTION
DESCRIPTION
The M5M51016BTP, RT are a 1048576-bit CMOS static RAM organized as 65536 word by 16-bit which are fabricated using high-performance triple polysilicon CMOS technology. The use of resistive load NMOS cells and CMOS periphery result in a high density and low power static RAM. They are low stand-by current and low operation current and ideal for the battery back-up application. The M5M51016BTP,RT are packaged in a 44-pin thin small outline package which is a high reliability and high density surface mount device (SMD). Two types of devices are available. M5M51016BTP(normal lead bend type package), M5M51016BRT (reverse lead bend type package). Using both types of devices, it becomes very easy to design a printed circuit board.
FEATURES
M5M51016BTP,RT-12VLL
Single +3.0V power supply Low stand-by current 0.3É A (typ.) Directly TTL compatible : All inputs and outputs Easy memory expansion and power down by CS, BC1 & BC2 Data hold on +2V power supply Three-state outputs : OR-tie capability OE prevents data contention in the I/O bus Common data I/O Package M5M51016BTP,RT
APPLICATION
Small capacity memory units
M5M51016BTP,RT-12VL
Type name
Access time
(max)
Active
(max)
stand-by
(max) 120µA
(VCC = 3.6V) 24µA
(VCC = 3.6V)
0.3µA (VCC = 3.0V, typ)
12mA
(1MHz)
Power supply current
120ns
120ns
44pin 400mil TSOP(II)
..............................
M5M51016BTP
M5M51016BRT
1
Outline 44P3W - J (400mil TSOP Reverse Bend)
9 Jul ,1997
MITSUBISHI LSIs
1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM
MITSUBISHI ELECTRIC
9 Jul ,1997
M5M51016BTP,RT-12VL-I,
-12VLL-I
A1 9 A3
7
A6
4
A7
3
A12 A14
A1540
A13 39
A8
ADDRESS INPUT
BUFFER
ROW DECODER
A0 10
A4 6 A2 8 A5 5
A9 36
A10 34 A11 35
ADDRESS
INPUT
BUFFER
COLUMN
DECODER
BLOCK
DECODER 11 43 42
CS
BC1 BC2
W
OE
DQ1
DQ2
DQ3 18 DQ4 19
DQ5 20 DQ6 21 DQ7 22 DQ8
DQ9 25
DQ10 26
DQ11 27
DQ12 28
DQ13 29
DQ14 30
DQ15 31
DQ16
OUTPUT BUFFEROUTPUT BUFFER
INPUT
DATA
CONTROL
INPUT
DATA
CONTROL
SENSE AMP. SENSE AMP.
CLOCK GENERATOR
65536 WORDS x16 BITS
( 1024 ROWS x 256 COLUMNS x 4 BLOCKS )
ADDRESS
CHIP SELECT
INPUT
BYTE
CONTROL
INPUTS
WRITE CONTROL
INPUT
OUTPUT ENABLE
INPUT
DATA INPUTS/
OUTPUTS
Vcc
GND(0V) 12 GND(0V)
INPUTS
BLOCK DIAGRAM
2
ADDRESS
INPUT
BUFFER
2
CS BC1 BC2 W OE Mode
Non selection
DQ1~8 DQ9~16
Stand-byHigh-Z
ICC
L X X X X High-Z
Non selection Stand-byHigh-ZX H H X X High-Z
Upper-Byte Write ActiveHigh-Z
H H L L X
Din
Upper-Byte Read ActiveHigh-ZH H L H L Dout
ActiveHigh-ZH H L H H High-Z ActiveDin
H L H L X High-Z
ActiveDoutH L H H L High-Z
Lower-Byte Write Lower-Byte Read
ActiveHigh-Z
H
L H H High-ZH
ActiveH L L XL
Din Din
Word Write
ActiveH L H LL Dout Dout
Word Read
ActiveHigh-Z
H
L H H High-ZL
The operation mode of the M5M51016B series are determined by a combination of the device control inputs BC1, BC2, CS, W and OE. Each mode is summarized in the function table. A write cycle is executed whenever the low level W overlaps with the low level BC1 and/or BC2 and the high level CS. The address must be set up before the write cycle and must be stable during the entire cycle. The data is latched into a cell on the trailing edge of W, BC1, BC2 or CS, whichever occurs first, requiring the set-up and hold time relative to these edge to be maintained. The output enable input OE directly controls the output stage. Setting the OE at a high level, the output stage is in a high-impedance state, and the databus contention problem in the write cycle is eliminated. A read cycle is executed by setting W at a high level and OE at a low level while BC1 and/or BC2 and CS are in an active state. (BC1 and/or BC2=L,CS=H) When setting BC1 at a high level and the other pins are in an active state, upper-Byte are in a selectable mode in which both reading and writing are enabled, and lower-Byte are in a non-selectable mode.And when setting BC2 at a high level and the other pins are in an active state, lower-Byte are in a selectable mode and upper -Byte are in a non-selectable mode.
When setting BC1 and BC2 at a high level or CS at a low level, the chips are in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips and memory expansion by BC1, BC2 and CS. The power supply current is reduced as low as the stand-by current which is specified as ICC3 or ICC4, and the memory data can be held at +2V power supply, enabling battery back-up operation during powerfailure or power-down operation in the non-selected mode.
FUNCTION
(High-Z=High-impedance)
MITSUBISHI LSIs
1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM
MITSUBISHI ELECTRIC
9 Jul ,1997
M5M51016BTP,RT-12VL-I,
-12VLL-I
ABSOLUTE MAXIMUM RATINGS
CAPACITANCE
Symbol
Parameter
Test conditions
pF
pF
Unit
Max
6
8
TypMin
Limits
VI=GND, VI=25mVrms, f=1MHz
VO=GND,VO=25mVrms, f=1MHz
Input capacitance ( except BC1,BC2)
Output capacitance
CI
CO
Parameter Supply voltage Input voltage
Output voltage Power dissipation Operating temperature Storage temperature
Unit
V V V
W
Conditions
With respect to GND
Ta=25 1
– 40 ~ 85 – 65 ~ 150
RatingsSymbol Vcc VI VO
Pd
Topr Tstg
DC ELECTRICAL CHARACTERISTICS
(Ta=– 40 ~ 85 , Vcc=2.7V ~ 3.6V, unless otherwise noted)
– 0.3 ~ 4.6
– 0.3* ~ Vcc + 0.3
(Ta=– 40 ~ 85 , Vcc=2.7V ~ 3.6V, unless otherwise noted)
0 ~ Vcc
* –3.0V in case of AC ( Pulse width 50ns )
Note 1: Direction for current flowing into an IC is positive (no mark).
2: Typical value is Vcc = 3.3V, Ta = 25
3
pF
9VI=GND, VI=25mVrms, f=1MHzInput capacitance ( BC1,BC2 )
CIBC
VIH VIL
VOH1
Symbol Parameter
V V V
Max
Vcc+0.3V
0.6
Typ
Limits
Min
2.0
– 0.3*
2.4
Test conditions Unit
High-level input voltage
Low-level input voltage
High-level output voltage 1
CC3
VOL
I
I
ICC1W
I
V
µA µA
0.4Low-level output voltage
Input current Output current in off-state
IO
1Stand-by current
mA
* –3.0V in case of AC ( Pulse width 30ns )
mA
50
Stand-by current
120
-VL
-VLL
24
IOH = –1mA IOH = – 0.1mA IOL = 2mA
VI =0 ~ Vcc BC1 and BC2 = VIH or CS = VIL or
OE = VIH, VI/O = 0 ~ Vcc
2) BC1,BC2 Vcc - 0.2V,
other inputs = 0~Vcc
BC1 and BC2 = VIH or CS = VIL,
other inputs = 0~Vcc
1) CS 0.2V, other inputs = 0~Vcc
1 1
BC1 and BC2 = VIL, CS = VIH other inputs = VIH or VIL Output-open(duty 100%)
Min cycle
1MHz
mA
12
VOH2
High-level output voltage 2
CC4
I
CS Vcc - 0.2V
Vcc–0.5V
V
ICC1B
mA
Min cycle
1MHz
mA
Active supply current (AC,TTL level)
Word operation (16bit)
Active supply current (AC,TTL level)
Byte operation (8bit)
(BC1 = VIH and BC2 = VIL) or (BC1 = VIL and BC2 = VIH),
CS = VIH other inputs = VIH or VIL Output-open(duty 100%)
10
30
ICC2W
ICC2B
27
5
20
3
C
o
C
o
<
<
<
>
>
µA
µA
+
_
+
_
C
o
C
o
C
o
C
o
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