Mitsubishi M37516M6-XXXHP Datasheet

MITSUBISHI ELECTRIC CORPORATION

SPEC.NAME

Customer's
Std.Spec

Prepared by
Checked by
Approved by
DATE

H.Yamazoe
Y.Hayashi
M.Abe
31 May '99

R
E
V

INTEGRATED CIRCUIT

1. Type No. M37516M6-XXXHP

2. Function Single chip 8-bit microcomputer

3. Application Office automation,Household products etc.

4. Outline

4.1 Name 48P6D / 48P6Q (48pin 0.5mm pitch Plastic-molded LQFP)

4.2 Drawing No.

5. Circuit
Drawing No.

6. Pin Configuration See Page 2

7. Related Documents

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DESCRIPTION

The M37516M6-XXXHP is the 8-bit microcomputer based on the
740 family core technology.
The M37516M6-XXXHP is designed for the household products
and office automation equipment and includes serial I/O functions,
8-bit timer, A-D converter, and I2C-bus interface.

FEATURES

●Basic machine-language instructions ...................................... 71

● Minimum instruction execution time ................................... 0.5us

(at 8 MHz oscillation frequency)

● Memory size

ROM .............................................................................24 Kbytes

RAM .............................................................................. 640 bytes

● Programmable input/output ports ............................................ 40

● Interrupts ................................................. 17 sources, 16 vectors

● Timers .............................................................................8-bit ✕ 4

●Serial I/O1 .................... 8-bit ✕ 1(UART or Clock-synchronized)

● Serial I/O2 ................................... 8-bit ✕ 1(Clock-synchronized)

● Multi-master I2C-bus interface (option) ....................... 1 channel

● P WM ............................................................................... 8-bit ✕ 1

●A-D converter ............................................... 10-bit ✕ 8 channels

● Watchdog timer ............................................................ 16-bit ✕ 1

● Clock generating circuit ..................................... Built-in 2 circuits

(connect to external ceramic resonator or quartz-crystal oscillator)

●Power source voltage

In high-speed mode .................................................. 4.0 to 5.5 V

(at 8 MHz oscillation frequency)

In high-speed mode .................................................. 2.7 to 5.5 V

(at 4 MHz oscillation frequency)

In middle-speed mode............................................... 2.7 to 5.5 V

(at 8 MHz oscillation frequency)

In low-speed mode .................................................... 2.7 to 5.5 V

(at 32 kHz oscillation frequency)

● Power dissipation

In high-speed mode ..........................................................34 mW

(at 8 MHz oscillation frequency, at 5 V power source voltage)

In low-speed mode ..............................................................60uW

(at 32 kHz oscillation frequency, at 3 V power source voltage)

● Operating temperature range....................................–20 to 85 C

APPLICATION

Office automation equipment, FA equipment, Household products,
Consumer electronics, etc.

PIN CONFIGURATION (TOP VIEW)

CC

SS

37

5

4

38

3

39

40

2

1

41

0

42
43
44

45

7

46

6

47

5

48

P35/AN
P34/AN
P33/AN
P32/AN
P31/AN
P30/AN

V

V

AV

P4
P4
P4

REF

6

/AN

6

P3

36

7

/AN

7

P3

35

IN2

/S

0

P0

34

OUT2

/S

1

P0

33

CLK2

/S

2

P0

32

RDY2

/S

3

P0

31

4

P0

30

5

P0

29

6

P0

28

7

P0

27

M37516M6-XXXHP

1

2

4

5

6

7

8

CLK

/S

6

P2

D

X

/T

2

/SCL

5

P2

9

D

X

/R

2

/SDA

4

P2

10

1

/SCL

3

P2

3

1

CMP2

/INT

2

/PWM

/S

3

2

P4

/INT

/INT

4

3

P4

P4

0

/INT

1

P4

1

RDY1

/S

0

/CNTR

0

P4

/CNTR

7

P2

)

)

1

0

(LED

(LED

1

0

P1

P1

25

26

11

12

1

SS

/SDA

2

CNV

P2

24

P12(LED2)

23

P13(LED3)

22

P14(LED4)

21

P1

5

(LED5)

P16(LED6)

20
19
18
17
16
15

13

P17(LED7)
V

SS

X

OUT
IN

X
RESET

14

P20 /X

COUT

P21/X

CIN

Package type : 48P6D-A / 48P6Q-A (48-pin plastic-molded LQFP)

Fig. 1 M37516M6-XXXHP pin configuration

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FUNCTIONAL BLOCK

INT0–

CNTR0

CNTR

1

VREF

AVSS

R A M

R O M

C P U

A

X

Y

S

PC

H

PCL

PS

V

SS

18

RESET

15

V

CC

43 12

CNV

SS

44 45

X

IN

16

17

SI/O1(8)

Reset input

Clock generating circuit

Main-clock

input

Main-clock

output

A-D

converter

(10)

Timer Y( 8 )

Timer X( 8 )

Prescaler 12(8)

Prescaler X(8)

Prescaler Y(8)

Timer 1( 8 )

Timer 2( 8 )

Sub-clock

input

X

OUT

X

CIN

X

COUT

Sub-clock

output

Watchdog

timer

Reset

P2(8)

P3(8)

I/O port P2

I/O port P3

P4(8)

I/O port P4

I C

INT3

1

3

5

2

4

36

3835 37

39

6810 14791113

P1(8)

I/O port P1

19 21 23 2520 22 24 26

P0(8)

I/O port P0

2728293031 32 33 34

PWM

(8)

2

XCIN

XCOUT

484746

40

4142

SI/O2(8)

FUNCTIONAL BLOCK DIAGRAM

Fig. 2 Functional block diagram

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PIN DESCRIPTION

Table 1 Pin description

VCC, VSS

RESET
XIN

XOUT

P00/SIN2
P01/SOUT2
P02/SCLK2
P03/SRDY2
P04–P07

P10–P17
P20/XCOUT

P21/XCIN
P22/SDA1
P23/SCL1
P24/SDA2/RxD
P25/SCL2/TxD

P26/SCLK
P27/CNTR0/

SRDY1

P30/AN0–
P37/AN7

P40/CNTR1
P41/INT0
P42/INT1

P43/INT2/SCMP2

P44/INT3/PWM
P45–P47

NamePin
Power source
CNVSS inputCNVSS
Reset input
Clock input

Clock output

I/O port P0

I/O port P1

I/O port P2

I/O port P3

I/O port P4

Functions

•Apply voltage of 2.7 V – 5.5 V to Vcc, and 0 V to Vss.

•This pin controls the operation mode of the chip.

•Normally connected to VSS.

•Reset input pin for active “L.”

•Input and output pins for the clock generating circuit.

•Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set
the oscillation frequency.

•When an external clock is used, connect the clock source to the XIN pin and leave the XOUT
pin open.

•8-bit CMOS I/O port.

•I/O direction register allows each pin to be individually
programmed as either input or output.

•CMOS compatible input level.

•CMOS 3-state output structure.

•P10 to P17 (8 bits) are enabled to output large current for LED drive.

•8-bit CMOS I/O port.

•I/O direction register allows each pin to be individually
programmed as either input or output.

•CMOS compatible input level.

•P22 to P25 can be switched between CMOS compat­ible input level or SMBUS input level in the I2C-BUS
interface function.

•P20, P21, P24 to P27: CMOS3-state output structure.

•P24, P25: N-channel open-drain structure in the I2C­BUS interface function.

•P22, P23: N-channel open-drain structure.

•8-bit CMOS I/O port with the same function as port P0.

•CMOS compatible input level.

•CMOS 3-state output structure.

•8-bit CMOS I/O port with the same function as port P0.

•CMOS compatible input level.

•CMOS 3-state output structure.

Function except a port function

• Serial I/O2 function pins

• Sub-clock generating circuit I/O
pins (connect a resonator)

• I2C-BUS interface function pins

• I2C-BUS interface function pin/
Serial I/O1 function pins

• Serial I/O1 function pin

• Serial I/O1 function pin/
Timer X function pin

• A-D converter input pin

• Timer Y function pin

• Interrupt input pins

• Interrupt input pins

• SCMP2 output pin

• Interrupt input pin

• PWM output pin

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FUNCTIONAL DESCRIPTION
CENTRAL PROCESSING UNIT (CPU)

The M37516M6-XXXHP uses the standard 740 Family instruction
set. Refer to the table of 740 Family addressing modes and ma­chine instructions or the 740 Family Software Manual for details
on the instruction set.
Machine-resident 740 Family instructions are as follows:

The FST and SLW instructions cannot be used.
The STP, WIT, MUL, and DIV instructions can be used.

[CPU Mode Register (CPUM)] 003B16

The CPU mode register contains the stack page selection bit, etc.
The CPU mode register is allocated at address 003B16.

b7

b0

CPU mode register

(

CPUM : address

003B16)

Processor mode bits
b1 b0
0 0 : Single-chip mode
0 1 :
1 0 : Not available
1 1 :

Stack page selection bit
0 : 0 page
1 : 1 page

Not used (return “1” when read)

(Do not write “0” to this bit.)

C

switch bit

Port X

0 : I/O port function (stop oscillating)

CIN–XCOUT

1 : X

Main clock (X

0 : Oscillating
1 : Stopped

Main clock division ratio selection bits
b7 b6
0 0 : φ = f(X
0 1 : φ = f(X
1 0 : φ = f(X
1 1 : Not available

IN–XOUT

oscillating function

) stop bit

IN

)/2 (high-speed mode)

IN

)/8 (middle-speed mode)

CIN

)/2 (low-speed mode)

Fig. 3 Structure of CPU mode register

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MEMORY

0100

16

0000

16

0040

16

FF00

16

FFDC

16

FFFE

16

FFFF

16

023F

16

A000

16

A080

16

RAM
640 bytes

ROM
24 Kbytes

0440

16

SFR area

Not used

Interrupt vector area

Reserved ROM area

(128 bytes)

Zero page

Special page

Reserved ROM area

Reserved area

Special Function Register (SFR) Area

The Special Function Register area in the zero page contains con­trol registers such as I/O ports and timers.

RAM

RAM is used for data storage and for stack area of subroutine
calls and interrupts.

ROM

The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is user area for storing programs.

Interrupt Vector Area

The interrupt vector area contains reset and interrupt vectors.

Zero Page

Access to this area with only 2 bytes is possible in the zero page
addressing mode.

Special Page

Access to this area with only 2 bytes is possible in the special
page addressing mode.

Fig. 4 Memory map diagram

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000016
000116
000216
000316
000416
000516
000616
000716
000816

000916
000A16
000B16

000C16

000D16
000E16

000F16

001016

001116

001216

001316

001416

001516

001616

001716

001816

001916
001A16
001B16

001C16

001D16
001E16

001F16

Port P0 (P0)
Port P0 direction register (P0D)
Port P1 (P1)
Port P1 direction register (P1D)
Port P2 (P2)
Port P2 direction register (P2D)
Port P3 (P3)
Port P3 direction register (P3D)
Port P4 (P4)
Port P4 direction register (P4D)

Serial I/O2 control register1 (SIO2CON1)
Serial I/O2 control register2 (SIO2CON2)
Serial I/O2 register (SIO2)

Transmit/Receive buffer register (TB/RB)
Serial I/O1 status register (SIOSTS)

Serial I/O1 control register (SIOCON)
UART control register (UARTCON)

Baud rate generator (BRG)
PWM control register (PWMCON)
PWM prescaler (PREPWM)
PWM register (PWM)

002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16

Prescaler 12 (PRE12)
Timer 1 (T1)
Timer 2 (T2)
Timer XY mode register (TM)
Prescaler X (PREX)
Timer X (TX)
Prescaler Y (PREY)
Timer Y (TY)
Timer count source selection register (TCSS)

2C

data shift register (S0)

I

2

C address register (S0D)

I

2

C status register (S1)

I

2

I

C control register (S1D)

2C

clock control register (S2)

I

2

C start/stop condition control register (S2D)

I

A-D control register (ADCON)
A-D conversion low-order register (ADL)
A-D conversion high-order register (ADH)

MISRG
Watchdog timer control register (WDTCON)

Interrupt edge selection register (INTEDGE)
CPU mode register (CPUM)
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)

Fig. 5 Memory map of special function register (SFR)

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I/O PORTS

The I/O ports have direction registers which determine the input/
output direction of each individual pin. Each bit in a direction reg­ister corresponds to one pin, and each pin can be set to be input
port or output port.
When “0” is written to the bit corresponding to a pin, that pin be­comes an input pin. When “1” is written to that bit, that pin
becomes an output pin.
If data is read from a pin which is set to output, the value of the
port output latch is read, not the value of the pin itself. Pins set to
input are floating. If a pin set to input is written to, only the port
output latch is written to and the pin remains floating.

Table 2 I/O port function

Pin
P00/SIN2
P01/SOUT2
P02/SCLK2
P03/SRDY2

P04–P07
P10–P17
P20/XCOUT

P21/XCIN

P22/SDA1
P23/SCL1

P24/SDA2/RxD
P25/SCL2/TxD

P26/SCLK

P27/CNTR0/SRDY1

P30/AN0—
P37/AN7

P40/CNTR1
P41/INT0

P42/INT1

P43/INT2/SCMP2

P44/INT3/PWM

P45—P47

Name

Port P0

Port P1

Port P2

Port P3

Port P4

Input/Output

Input/output,
individual
bits

I/O Structure Non-Port Function

CMOS compatible
input level
CMOS 3-state output

CMOS compatible
input level
CMOS/SMBUS input
level (when selecting
I2C-BUS interface
function)
N-channel open-drain
output

CMOS compatible
input level
CMOS/SMBUS input
level (when selecting
I2C-BUS interface
function)
CMOS 3-state output
N-channel open-drain
output (when
selecting I2C-BUS
interface function)

CMOS compatible
input level

CMOS 3-state output

Serial I/O2 function I/O

Sub-clock generating
circuit

I2C-BUS interface func­tion I/O

I2C-BUS interface func­tion I/O

Serial I/O1 function I/O

Serial I/O1 function I/O

Serial I/O1 function I/O
Timer X function I/O

A-D conversion input
Timer Y function I/O
External interrupt input

External interrupt input
SCMP2 output

External interrupt input
PWM output

Related SFRs

Serial I/O2 control
register

CPU mode register

I2C control register

I2C control register
Serial I/O1 control
register

Serial I/O1 control
register

Serial I/O1 control
register
Timer XY mode register

A-D control register
Timer XY mode register

Interrupt edge selection
register

Interrupt edge selection
register
Serial I/O2 control
register

Interrupt edge selection
register
PWM control register

Ref.No.

(1)
(2)
(3)
(4)

(5)

(6)
(7)

(8)
(9)

(10)
(11)

(12)

(13)

(14)
(15)

(16)

(17)

(18)

(5)

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(1) Port P0

Data bus

0

Direction
register

Port latch

(2) Port P0

P01/S

Serial I/O2 transmit completion signal

1

OUT2

P-channel output disable bit

Serial I/O2 port selection bit

Direction
register

(3) Port P0

Serial I/O2 synchronous clock selection bit

2

P0

2/SCLK2

P-channel output disable bit

Serial I/O2 port selection bit

Direction
register

Data bus

Serial I/O2 clock output

Port latch

(5) Port P04-P07, P1, P45-P4

Direction
register

Data bus

Port latch

Serial I/O2 input

Serial I/O2 External clock input

7

Data bus

(4) Port P0

Data bus

(6) Port P2

Port XC switch bit

Data bus

Port latch

Serial I/O2 output

3

S

RDY2

output enable bit

Direction
register

Port latch

Serial I/O2 ready output

0

Direction
register

Port latch

(7) Port P2

Data bus

1

Port XC switch bit

Direction
register

Port latch

Sub-clock generating circuit input

(8) Port P2

2

I C-BUS interface enable bit

SDA/SCL pin selection bit

Data bus

2

SDA output

Direction
register

Port latch

Fig. 6 Port block diagram (1)

M37516M6-XXXHP GNOK-M37516M6-XXXHP-50 (MSETSU 2)

Port P2

SDA input

1

Port X

Oscillator

C

switch bit

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(9) Port P2

I2C-BUS interface enable bit

SDA/SCL pin selection bit

Data bus

3

Direction
register

Port latch

SCL output

SCL input

(10) Port P2

I2C-BUS interface enable bit

SDA/SCL pin selection bit

Serial I/O1 enable bit

Receive enable bit

Data bus

4

Direction
register

Port latch

SDA output

SDA input

Serial I/O1 input

(11) Port P2

Serial I/O1 enable bit

Transmit enable bit

I2C bus interface enable bit

SDA/SCL pin selection bit

Data bus

Serial I/O1 output

(13) Port P2

Serial I/O1 mode selection bit

S

RDY1

Data bus

5

P-channel output disable bit

Direction
register

Port latch

SCL output

7

Pulse output mode

Serial I/O1 enable bit

output enable bit

Direction
register

Port latch

SCL input

(12) Port P2

Serial I/O1 enable bit

Serial I/O1 clock selection bit

Serial I/O1 mode selection bit

Data bus

Serial I/O1 clock output

6

Serial I/O1 enable bit

Direction
register

Port latch

(14) Port P30–P3

Data bus

7
Direction

register

Port latch

A-D converter input

Analog input pin selection bit

External clock input

Serial ready output

(15) Port P4

Data bus

Pulse output mode

Timer output

0

Direction
register

Port latch

Pulse output mode

Timer output

CNTR

0

interrupt

CNTR1 interrupt input

input

(16) Port P41, P4

Data bus

2

Direction
register

Port latch

Interrupt input

Fig. 7 Port block diagram (2)

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(17) Port P4

3

Serial I/O2 I/O comparison
signal control bit

Direction
register

(18) Port P4

PWM output enable bit

4

Direction
register

Data bus

Serial I/O2 I/O comparison
signal output

Port latch

Fig. 8 Port block diagram (3)

Interrupt input

Data bus

Port latch

PWM output

Interrupt input

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INTERRUPTS

Interrupts occur by 17 sources among 17 sources: seven external,
nine internal, and one software.

Interrupt Control

Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software in­terrupt set by the BRK instruction. An interrupt occurs if the
corresponding interrupt request and enable bits are “1” and the in­terrupt disable flag is “0”.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
The BRK instruction cannot be disabled with any flag or bit. The I
(interrupt disable) flag disables all interrupts except the BRK in­struction interrupt.
When several interrupts occur at the same time, the interrupts are
received according to priority.

Interrupt Operation

By acceptance of an interrupt, the following operations are auto­matically performed:

1. The contents of the program counter and the processor status
register are automatically pushed onto the stack.

2. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.

3. The interrupt jump destination address is read from the vector
table into the program counter.

■Notes

When the active edge of an external interrupt (INT0–INT3, SCL/
SDA, CNTR0, CNTR1) is set, the corresponding interrupt request
bit may also be set. Therefore, take the following sequence:

1. Disable the interrupt

2. Change the interrupt edge selection register
(SCL/SDA interrupt pin polarity selection bit for SCL/SDA; the

timer XY mode register for CNTR0 and CNTR1)

3. Clear the interrupt request bit to “0”

4. Accept the interrupt.

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Table 3 Interrupt vector addresses and priority

Interrupt Source
Reset (Note 2)

INT0

SCL, SDA

INT1

INT2

INT3 / Serial I/O2

I2C
Timer X
Timer Y
Timer 1
Timer 2

Serial I/O1
reception

Serial I/O1
Transmission

CNTR0

CNTR1

A-D converter
BRK instruction

Notes 1: Vector addresses contain interrupt jump destination addresses.

2: Reset function in the same way as an interrupt with the highest priority.

Priority

1
2

3

4

5

6
7

8

9
10
11

12

13

14

15
16

17

Vector Addresses (Note 1)

High

FFFD16
FFFB16

FFF916

FFF716

FFF516

FFF316
FFF116

FFEF16

FFED16

FFEB16
FFE916

FFE716

FFE516

FFE316

FFE116
FFDF16

FFDD16

Low

FFFC16
FFFA16

FFF816

FFF616

FFF416

FFF216
FFF016

FFEE16
FFEC16
FFEA16

FFE816

FFE616

FFE416

FFE216

FFE016
FFDE16

FFDC16

Interrupt Request

Generating Conditions
At reset
At detection of either rising or

falling edge of INT0 input
At detection of either rising or

falling edge of SCL or SDA input
At detection of either rising or

falling edge of INT1 input
At detection of either rising or

falling edge of INT2 input
At detection of either rising or

falling edge of INT3 input
At completion of data transfer

At timer X underflow
At timer Y underflow
At timer 1 underflow
At timer 2 underflow
At completion of serial I/O1 data

reception
At completion of serial I/O1

transfer shift or when transmis­sion buffer is empty

At detection of either rising or
falling edge of CNTR0 input

At detection of either rising or
falling edge of CNTR1 input

At completion of A-D conversion
At BRK instruction execution

Remarks

Non-maskable
External interrupt

(active edge selectable)
External interrupt

(active edge selectable)
External interrupt

(active edge selectable)
External interrupt

(active edge selectable)
External interrupt

(active edge selectable)

STP release timer underflow

Valid when serial I/O is selected

Valid when serial I/O is selected

External interrupt
(active edge selectable)

External interrupt
(active edge selectable)

Non-maskable software interrupt

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Interrupt request bit

Interrupt enable bit

Interrupt disable flag (I)

Fig. 9 Interrupt control

b7 b0

b7 b0

BRK instruction

Interrupt edge selection register
(INTEDGE : address 003A

INT0 active edge selection bit
INT

1

active edge selection bit

INT

2

active edge selection bit

INT

3

active edge selection bit

Serial I/O2 / INT
Not used (returns “0” when read)

Interrupt request register 1
(IREQ1 : address 003C

INT0 interrupt request bit
SCL/SDA interrupt request bit

1

interrupt request bit

INT
INT

2

interrupt request bit

3

/ Serial I/O2 interrupt request bit

INT

2

I

C interrupt request bit
Timer X interrupt request bit
Timer Y interrupt request bit

0 : No interrupt request issued
1 : Interrupt request issued

16

)

3

interrupt source bit

16

)

Reset

0 : Falling edge active
1 : Rising edge active

0 : INT3 interrupt selected
1 : Serial I/O2 interrupt selected

b7 b0

Interrupt request

Interrupt request register 2
(IREQ2 : address 003D

Timer 1 interrupt request bit
Timer 2 interrupt request bit
Serial I/O1 reception interrupt request bit
Serial I/O1 transmit interrupt request bit

0

interrupt request bit

CNTR
CNTR

1

interrupt request bit
AD converter interrupt request bit
Not used (returns “0” when read)

0 : No interrupt request issued
1 : Interrupt request issued

16

)

b7 b0

Interrupt control register 1

(ICON1 : address 003E

INT0 interrupt enable bit
SCL/SDA interrupt enable bit

1

interrupt enable bit

INT
INT

2

interrupt enable bit

INT

3

/ Serial I/O2 interrupt enable bit

2

I

C interrupt enable bit
Timer X interrupt enable bit
Timer Y interrupt enable bit

16

)

b7 b0

Interrupt control register 2
(ICON2 : address 003F

Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
Serial I/O1 reception interrupt enable bit
Serial I/O1 transmit interrupt enable bit

0

CNTR
CNTR

1

AD converter interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit)

0 : Interrupts disabled
1 : Interrupts enabled

0 : Interrupts disabled
1 : Interrupts enabled

Fig. 10 Structure of interrupt-related registers (1)

M37516M6-XXXHP GNOK-M37516M6-XXXHP-50 (MSETSU 2)

16

)

interrupt enable bit
interrupt enable bit

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TIMERS

The M37516M6-XXXHP has four timers: timer X, timer Y, timer 1,
and timer 2.
The division ratio of each timer or prescaler is given by 1/(n + 1),
where n is the value in the corresponding timer or prescaler latch.
All timers are count down. When the timer reaches “0016”, an un­derflow occurs at the next count pulse and the corresponding
timer latch is reloaded into the timer and the count is continued.
When a timer underflows, the interrupt request bit corresponding
to that timer is set to “1”.

b7

Fig. 11 Structure of timer XY mode register

b0

Timer XY mode register
(TM : address 0023

Timer X operating mode bit

b1b0

0 0: Timer mode
0 1: Pulse output mode
1 0: Event counter mode
1 1: Pulse width measurement mode

CNTR0 active edge selection bit

0: Interrupt at falling edge

Count at rising edge in event

counter mode

1: Interrupt at rising edge

Count at falling edge in event

counter mode

Timer X count stop bit

0: Count start
1: Count stop

Timer Y operating mode bit

b5b4

0 0: Timer mode
0 1: Pulse output mode
1 0: Event counter mode
1 1: Pulse width measurement mode

1

active edge selection bit

CNTR

0: Interrupt at falling edge

Count at rising edge in event

counter mode

1: Interrupt at rising edge

Count at falling edge in event

counter mode

Timer Y count stop bit

0: Count start
1: Count stop

16

)

Timer 1 and Timer 2

The count source of prescaler 12 is the oscillation frequency
which is selected by timer 12 count source selection bit. The out­put of prescaler 12 is counted by timer 1 and timer 2, and a timer
underflow sets the interrupt request bit.

Timer X and Timer Y

Timer X and Timer Y can each select in one of four operating
modes by setting the timer XY mode register.

(1) Timer Mode

The timer counts the count source selected by Timer count source
selection bit.

(2) Pulse Output Mode

The timer counts the count source selected by Timer count source
selection bit. Whenever the contents of the timer reach “0016”, the
signal output from the CNTR0 (or CNTR1) pin is inverted. If the
CNTR0 (or CNTR1) active edge selection bit is “0”, output begins
at “ H”.
If it is “1”, output starts at “L”. When using a timer in this mode, set
the corresponding port P27 ( or port P40) direction register to out­put mode.

(3) Event Counter Mode

Operation in event counter mode is the same as in timer mode,
except that the timer counts signals input through the CNTR0 or
CNTR1 pin.
When the CNTR0 (or CNTR1) active edge selection bit is “0”, the
rising edge of the CNTR0 (or CNTR1) pin is counted.
When the CNTR0 (or CNTR1) active edge selection bit is “1”, the
falling edge of the CNTR0 (or CNTR1) pin is counted.

(4) Pulse Width Measurement Mode

If the CNTR0 (or CNTR1) active edge selection bit is “0”, the timer
counts the selected signals by the count source selection bit while
the CNTR0 (or CNTR1) pin is at “H”. If the CNTR0 (or CNTR1) ac­tive edge selection bit is “1”, the timer counts it while the CNTR0
(or CNTR1) pin is at “L”.

b7

b0

Timer count source selection register
(TCSS : address 0028

Timer X count source selection bit
0 : f(X

IN

)/16 (f(X

CIN

)/16 (f(X
)/2 (f(X

)/16 (f(X

)

CIN

CIN

CIN

CIN

)/16 at low-speed mode)

)/2 at low-speed mode)

)/16 at low-speed mode)

)/2 at low-speed mode)

)/16 at low-speed mode)

1 : f(XIN)/2 (f(X
Timer Y count source selection bit

0 : f(X

IN

1 : f(X

IN

Timer 12 count source selection bit
0 : f(X

IN

1 : f(X

CIN

Not used (returns “0” when read)

16

)

The count can be stopped by setting “1” to the timer X (or timer Y)
count stop bit in any mode. The corresponding interrupt request
bit is set each time a timer underflows.

■Note

When switching the count source by the timer 12, X and Y count
source bit, the value of timer count is altered in unconsiderable
amount owing to generating of a thin pulses in the count input
signals.
Therefore, select the timer count source before set the value to

Fig. 12 Structure of timer count source selection register

the prescaler and the timer.

M37516M6-XXXHP GNOK-M37516M6-XXXHP-50 (MSETSU 2)

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Data bus

f(XIN)/16

f(XIN)/2

Timer X count source selection bit

P2

7

/CNTR

0

Port P2

direction register

7

f(XIN)/16

f(XIN)/2

Timer Y count source selection bit

P40/CNTR

1

Port P4

direction register

CNTR
edge selection

“0”

“1”

Port P2
latch

Pulse output mode

CNTR
edge selection

“0”

“1”

Port P4

0

latch

Pulse output mode

0

active

bit

7

1

active

bit

0

Pulse width
measurement
mode

Event
counter
mode

CNTR
edge selection
bit

Pulse width
measure­ment mode

Event
counter
mode

CNTR
edge selection
bit

Timer mode
Pulse output mode

Timer X count stop bit

0

active

“1”

“0”

Timer mode
Pulse output mode

Timer Y count stop bit

1

active

“1”

“0”

Data bus

Prescaler X latch (8)

Prescaler X (8)

Q

Toggle flip-flop

Q

R

Data bus

Prescaler Y latch (8)

Prescaler Y (8)

Q

Toggle flip-flop

Q

R

Timer X latch (8)

Timer X (8)

To timer X interrupt
request bit

0

interrupt

To CNTR
request bit

T

Timer X latch write pulse
Pulse output mode

Timer Y latch (8)

Timer Y (8)

To timer Y interrupt
request bit

1

interrupt

To CNTR
request bit

T

Timer Y latch write pulse
Pulse output mode

Timer 2 latch (8)

Timer 2 (8)

f(XIN)/16

f(X

CIN

Prescaler 12 latch (8)

)

Prescaler 12 (8)

Timer 1 latch (8)

Timer 1 (8)

Timer 12 count source selection bit

Fig. 13 Block diagram of timer X, timer Y, timer 1, and timer 2

M37516M6-XXXHP GNOK-M37516M6-XXXHP-50 (MSETSU 2)

To timer 2 interrupt
request bit

To timer 1 interrupt
request bit

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SERIAL I/O1

Serial I/O1 can be used as either clock synchronous or asynchro­nous (UART) serial I/O. A dedicated timer is also provided for
baud rate generation.

Data bus

(1) Clock Synchronous Serial I/O Mode

Clock synchronous serial I/O mode can be selected by setting the
serial I/O mode selection bit of the serial I/O1 control register (bit
6 of address 001A16) to “1”.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the TB/RB.

Receive buffer register

P24/RXD

P26/SCLK

7/SRDY1

P2

P2

5/TXD

XIN

BRG count source selection bit

1/4

F/F

Falling-edge detector

Receive shift register

Transmit shift register

Transmit buffer register

Data bus

Fig. 14 Block diagram of clock synchronous serial I/O1

Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)

Serial output TxD

D

0

Address 0018

Shift clock

Serial I/O1 synchronous
clock selection bit
Frequency division ratio 1/(n+1)

Baud rate generator

Address 0018

D

1

16

Address 001C

Shift clock

D

2

Serial I/O1 control register

Clock control circuit

16

Clock control circuit

Transmit interrupt source selection bit

Serial I/O1 status register

16

D

3

Receive buffer full flag (RBF)

Receive interrupt request (RI)

1/4

Transmit shift completion flag (TSC)

Transmit interrupt request (TI)

Transmit buffer empty flag (TBE)

D

4

D

5

Address 001A

Address 0019

D

6

16

16

D

7

Serial input RxD

Receive enable signal S

RDY1

D

0

D

1

D

2

D

3

D

4

D

Write pulse to receive/transmit

16

buffer register (address 0018

)

TBE = 0

TBE = 1
TSC = 0

Notes

1: As the transmit interrupt (TI), either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has

ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register.

2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data

is output continuously from the TxD pin.

3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .

Fig. 15 Operation of clock synchronous serial I/O1 function

M37516M6-XXXHP GNOK-M37516M6-XXXHP-50 (MSETSU 2)

D

5

D

6

7

RBF = 1

TSC = 1
Overrun error (OE)
detection

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