Mitsubishi M37274MA-XXXSP Datasheet

MITSUBISHI MICROCOMPUTERS

M37274MA-XXXSP

PRELIMINARY

Notice: This is not a final specification.

Some paramentic limits are subject to change.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER

DESCRIPTION

The M37274MA-XXXSP is a single-chip microcomputer designed with
CMOS silicon gate technology. It is housed in a 52-pin shrink plastic
molded DIP.
In addition to their simple instruction sets, the ROM, RAM and I/O
addresses are placed on the same memory map to enable easy pro­gramming.
The M37274MA-XXXSP has a OSD function and a data slicer func­tion, so it is useful for a channel selection system for TV with a closed
caption decoder.

FEATURES

Number of basic instructions..................................................... 71

•

Memory size

•

Minimum instruction execution time

•

......................................... 0.5

Power source voltage...................................................5 V ± 10 %

•

Subroutine nesting ............................................. 128 levels (Max.)

•

Interrupts ....................................................... 18 types, 16 vectors

•

8-bit timers .................................................................................. 6

•

Programmable I/O ports (Ports P0, P1, P2, P30, P31) .............. 26

•

Input ports (Ports P40–P46, P63, P64, P70–P72) ...................... 12

•

Output ports (Ports P52–P55)...................................................... 4

•

12 V withstand ports.................................................................... 7

•

LED drive ports ........................................................................... 2

•

Serial I/O ............................................................ 8-bit ✕ 1 channel

•

Multi-master I2C-BUS interface ................................1 (2 systems)

•

A-D converter (8-bit resolution) .................................... 4 channels

•

PWM output circuit .........................................14-bit ✕ 1, 8-bit ✕ 7

•

Power dissipation

•

In high-speed mode .......................................................... 165mW

(at V
slicer on)

In low-speed mode...........................................................0.33mW

(at V

Data slicer

•

ROM correction function

•

ROM ....................................................... 40 K bytes

RAM ..........................................................768 bytes

ROM correction memory............................. 64 bytes

ROM for OSD .......................................11072 bytes

RAM for OSD..........................................1296 bytes

µ

s (at 8 MHz oscillation frequency)

CC = 5.5V, 8MHz oscillation frequency, CRT on, and Data

CC = 5.5V, 32kHz oscillation frequency)

and ON-SCREEN DISPLAY CONTROLLER

OSD function

•

Display characters ............................... 36 characters ✕ 12 lines

Kinds of characters...................................................... 256 kinds

(In EXOSD mode, they can be combined with 16 kinds of extra

fonts)

Character display area ........................ CC mode : 16 ✕ 26 dots

OSD mode : 16 ✕ 20 dots

EXOSD mode : 16 ✕ 26 dots

Kinds of character sizes ............................... CC mode : 2 types

OSD mode : 14 types

EXOSD mode : 6 types

It can be specified by a character unit (maximum 7 kinds).

Character font coloring, character background coloring

It can be specified by a screen unit (maximum 7 kinds).

Extra font coloring, raster coloring, border coloring

Kinds of character colors ............... CC mode : 7 kinds (R, G, B)

OSD mode : 7 kinds (R, G, B)

EXOSD mode : 5 kinds (R, G, B)

Display position

Horizontal ................................................................ 256 levels

Vertical .................................................................. 1024 levels

Attribute ......................CC mode : smooth italic, underline, flash

OSD mode : border
EXOSD mode : border,

extra font (16 kinds)
Automatic solid space function
Window function
Dual layer OSD function

APPLICATION

TV with a closed caption decoder

MITSUBISHI MICROCOMPUTERS

M37274MA-XXXSP

PRELIMINARY

Notice: This is not a final specification.

Some paramentic limits are subject to change.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER

PIN CONFIGURATION (TOP VIEW)

SYNC

H
V

SYNC

P40/AD4

P4

1

/INT2

P4

2

/TIM2

P4

3

/TIM3

P2

4

/AD3

P2

5

/AD2
P26/AD1
P2

7

/AD5

P0

0

/PWM4

P0

1

/PWM5

P0

2

/PWM6

7/SIN

P1

P44/INT1

P4

5/SOUT

P4

6/SCLK

AV

CC

HLF/AD6

P72/RVCO

P71/V

HOLD

P70/CV

IN

CNV

SS

X

IN

X

OUT

V

SS

1
2
3
4

5
6
7
8
9

M37274MA-XXXSP

10
11
12
13
14

15
16
17
18
19
20
21
22
23
24
25
26

52
51
50
49
48

47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27

and ON-SCREEN DISPLAY CONTROLLER

P52/R
P5

3

/G

4

/B

P5
P5

5

/OUT1

P0

4

/PWM0

P0

5

/PWM1
P06/PWM2
P07/PWM3

0

P2

1

P2
P2

2

P2

3

P1

0

/OUT2

1

/SCL1

P1

2

/SCL2

P1
P1

3

/SDA1
P1

4

/SDA2

5

P1
P16/INT3
P03/DA
P3

0

P31
RESET
P6

4

/OSC2/X

COUT

P63/OSC1/X
V

CC

CIN

Outline 52P4B

2

MITSUBISHI MICROCOMPUTERS

M37274MA-XXXSP

PRELIMINARY

Notice: This is not a final specification.

Some paramentic limits are subject to change.

3, P64

Input ports P6

Input ports P70–P72

29

OSC2

Clock output for OSD/

sub-clock output

28

OSC1

sub-clock input

Clock input for OSD/

A-D converter

19

HLF

22

CVIN

21

20

RVCO

Data slicer

VHOLD

Pins for data slicer

P7 (3)

23

CNVSS

26

VSS

27

VCC

CC

18

AV

30

RESET

Reset input

25

Clock output

XOUT

IN

24

X

Clock input

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER

and ON-SCREEN DISPLAY CONTROLLER

SYNC

Clock

generating

circuit

P6 (2)

selection circuit

Timer count source

TIM2

TIM3

T1 (8)

Timer 1

ROM

40 K bytes

counter

Program

counter

Progam

Data bus

RAM

768 bytes

PCL (8)

PCH (8)

T2 (8)

Timer 2

Address bus

T3 (8)

Timer 3

ROM

correction

Instruction

Control signal

T4 (8)

Timer 5

Timer 4

Stack

pointer

Index

register

Index

register

status

Processor

A (8)

Accumulator

8-bit

arithmetic

function

decoder

T5 (8)

S (8)

Y (8)

X (8)

PS (8)

register

and

logical unit

CRT circuit

Instruction

register (8)

T6 (8)

Timer 6

8-bit

PWM circuit

INT2
INT1

SI/O (8)

14bit

PWM

A-D

converter

INT3
OUT2

Multi-master

C-BUS interface

2

I

P5 (4)

P4 (7)

SOUT
SCLK
SIN

P0 (8)

P2 (8)

P1 (8)

P3 (2)

R
G
B

PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6

SCL1
SCL2

SDA1
SDA2

H
VSYNC

OUT1

1
2

Sync

52
51
50
49

Output port P5

3
4

0–P46

5
6

15
16
17

Input ports P4

11
12
13
33
48
47

I/O port P0

46
45

44
43
42
41

7
8

I/O port P2

9
10

40
39
38
37
36

I/O port P1

35
34
14

31
32

I/O ports

signal input

0, P31

P3

FUNCTIONAL BLOCK DIAGRAM of M37274MA-XXXSP

3

MITSUBISHI MICROCOMPUTERS

M37274MA-XXXSP

PRELIMINARY

Notice: This is not a final specification.

Some paramentic limits are subject to change.

FUNCTIONS

Number of basic instructions
Instruction execution time

Clock frequency
Memory size

Input/Output ports

Serial I/O
Multi-master I
A-D converter
PWM output circuit
Timers
Subroutine nesting
Interrupt

Clock generating circuit

Data slicer

2

C-BUS interface

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER

and ON-SCREEN DISPLAY CONTROLLER

Parameter Functions

71

µ

s (the minimum instruction execution time, at 8 MHz oscillation fre-

0.5
quency)

8 MHz (maximum)
ROM
RAM
ROM correction memory
OSD ROM
OSD RAM

0–P02,

P0
P0

4–P07

P03

P10, P15–P17

P11–P14

P2

0, P31

P3
P40–P44

P45, P46

P52–P55
P63
P64

P70–P72

Input

Input

Output

Input
Input

Input

I/O

I/O

I/O

I/O

I/O
I/O

40 K bytes

768 bytes

64 bytes

11072 bytes

1296 bytes

7-bit ✕ 1 (N-channel open-drain output structure, can be used as 8-bit

PWM output pins)

1-bit ✕ 1

(CMOS input/output structure, can be used as 14-bit PWM output pin)

4-bit ✕ 1 (CMOS input/output structure, can be used as OSD output pin,

INT input pin, serial input pin)

4-bit ✕ 1 (N-channel open-drain output structure, can be used as multi-

2

master I

8-bit ✕ 1 (CMOS input/output structure, can be used as A-D input pins)

2-bit ✕ 1 (CMOS input/output structure)

5-bit ✕ 1 (can be used as A-D input pins, INT input pins, external clock

input pins)

2-bit ✕ 1 (N-channel open-drain output structure when serial I/O is used,

can be used as serial I/O pins)

4-bit ✕ 1 (CMOS output structure, can be used as OSD output)

1-bit ✕ 1 (can be used as sub-clock input pin, OSD clock input pin)

1-bit ✕ 1 (CMOS output structure when LC is oscillating, can be used as

sub-clock output pin, OSD clock output pin)

3-bit ✕ 1 (can be used as data slicer input/output)

8-bit ✕ 1

1

6 channels (8-bit resolution)

14-bit ✕ 1, 8-bit ✕ 7

8-bit timer ✕ 6

128 levels (maximum)

External interrupt ✕ 3, Internal timer interrupt ✕ 6, Serial I/O interrupt ✕ 1,

OSD interrupt ✕ 1, Multi-master I

Data slicer interrupt ✕ 1, f(X

D conversion interrupt ✕ 1, BRK instruction interrupt ✕ 1

2 built-in circuits (externally connected to a ceramic resonator or a quartz-

crystal oscillator)

Built in

C-BUS interface)

2

IN)/4092 interrupt ✕ 1, VSYNC interrupt ✕ 1, A-

C-BUS interface interrupt ✕ 1,

4

MITSUBISHI MICROCOMPUTERS

M37274MA-XXXSP

PRELIMINARY

Notice: This is not a final specification.

Some paramentic limits are subject to change.

FUNCTIONS (continued)

Parameter

OSD function

Power source voltage
Power dissipation

Operating temperature range
Device structure
Package

In high-speed
mode

In low-speed
mode

In stop mode

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER

Number of display characters
Character display area

Kinds of characters

Kinds of character sizes

Kinds of character colors

Display position (horizontal, vertical)

OSD ON
OSD OFF
OSD OFF

Data slicer ON
Data slicer OFF
Data slicer OFF

36 characters ✕ 12 lines
CC mode: 16 ✕ 26 dots (dot structure: 16 ✕ 20 dots)
OSD mode: 16 ✕ 20 dots
EXOSD mode: 16 ✕ 26 dots
256 kinds
(In EXOSDmode, they can be combined with 16 kinds of extra fonts)
CC mode: 2 kinds
OSD mode: 14 kinds
EXOSD mode: 6 kinds
CC mode: 7 kinds (R, G, B)
OSD mode: 7 kinds (R, G, B)
EXOSD mode: 5 kinds (R, G, B)

256 levels (horizontal) ✕ 1024 levels (vertical)
5 V ± 10 %
165 mW typ. (at oscillation frequency f(X

82.5 mW typ. (at oscillation frequency f(X

0.33mW typ. (at oscillation frequency f(X

0.055 mW (maximum)
–10 °C to 70 °C
CMOS silicon gate process
52-pin shrink plastic molded DIP

and ON-SCREEN DISPLAY CONTROLLER

Functions

IN) = 8 MHz, fOSC = 13 MHz)
IN) = 8 MHz)
CIN) = 32 kHz, f(XIN) = stopped)

5

MITSUBISHI MICROCOMPUTERS

M37274MA-XXXSP

PRELIMINARY

Notice: This is not a final specification.

Some paramentic limits are subject to change.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER

PIN DESCRIPTION

Pin Name Functions

VCC,
AV

CC,

V

SS

CNVSS

_____

RESET

XIN
XOUT

P00/PWM4–
P0

2

/PWM6,

P0

3

/DA,

P0

4

/PWM0–

P0

7

/PWM3

Power source

CNV

SS

Reset input

Clock input
Clock output

I/O port P0

DA output
8-bit PWM output

P10/OUT2,
P1

1/SCL1,

P1

2/SCL2,

P1

3/SDA1,

P1

4/SDA2,

P1

5,

P1

6/INT3,

P1

7/SIN

I/O port P1

OSD output
Multi-master

2

I

C-BUS interface

External interrupt
input

Serial I/O data
input

P20–P23

I/O port P2
P24/AD3–
P2

6/AD1,

P27/AD5

0, P31

P3

P40/AD4,
P4

1/INT2,

P4

2/TIM2,

P4

3/TIM3,

P4

4/INT1,

P4

5/SOUT,
6/SCLK

P4

Analog input

I/O port P3

Input port P4

Analog input

External interrupt

input

External clock input

Serial I/O data

output

Serial I/O

synchronous clock

input/output
P52/R,P53/G,

P5

4

/B,

P5

5

/OUT1

Output port P5

OSD output

Input/

Output

Input

Input

Output

I/O

Output
Output

I/O

Output
Output

Input

Input

I/O

Input

I/O

Input
Input
Input

Input

Output

I/O

Output
Output

Apply voltage of 5 V ± 10 % (typical) to V

Connected to V

SS.

To enter the reset state, the reset input pin must be kept at a “L” for 2

CC conditions).

normal V
If more time is needed for the quartz-crystal oscillator to stabilize, this “L” condition should
be maintained for the required time.

This chip has an internal clock generating circuit. To control generating frequency, an
external ceramic resonator or a quartz-crystal oscillator is connected between pins X
X

OUT. If an external clock is used, the clock source should be connected to the XIN pin and

OUT pin should be left open.

the X
Port P0 is an 8-bit I/O port with direction register allowing each I/O bit to be individually

programmed as input or output. At reset, this port is set to input mode. The output structure
of P0

3 is CMOS output, that of P00–P02 and P04–P07 are N-channel open-drain output.

See notes at end of Table for full details of port P0 functions.
Pin P0

3 is also used as 14-bit PWM output pin DA. The output structure is CMOS output.

0–P02 and P04–P07 are also used as PWM output pins PWM4–PWM6 and PWM0–

Pins P0
PWM3 respectively. The output structure is N-channel open-drain output.

Port P1 is an 8-bit I/O port and has basically the same functions as port P0. The output
structure of P1

0 and P15–P17 is CMOS output, that of P11–P14 is N-channel open-drain

output.
Pin P1

0 is also used as OSD output pin OUT2. The output structure is CMOS output.
1 is used as SCL1, SCL2, SDA1 and SDA2 respectively, when multi-master I

Pin P1
BUS interface is used. The output structure is N-channel open-drain output.

Pin P1

6 is also used as external interrupt input pin INT3.

Pin P1

7 is also used as serial I/O data input pin SIN.

Port P2 is an 8-bit I/O port and has basically the same functions as port P0. The output
structure is CMOS output.

Pins P2

4–P26, P27 are also used as analog input pins AD3–AD1, AD5 respectively.

Ports P3

0 and P31 are 2-bit I/O ports and have basically the same functions as port P0.

The output structure is CMOS output.
Ports P4

0–P46 are a 7-bit input port.

Pin P4

0 is also used as analog input pin AD4.

1, P44 are also used as external interrupt input pins INT2, INT1.

Pins P4

Pins P4

2 and P43 are also used as external clock input pins TIM2, TIM3 respectively.

Pin P4

5 is used as serial I/O data output pin SOUT. The output structure is N-channel open-

drain output.
Pin P4

6 is used as serial I/O synchronous clock input/output pin SCLK. The output structure

is N-channel open-drain output.

Ports P5

2–P55 are 4-bit output ports. The output structure is CMOS output.

2–P55 are also used as OSD output pins R, G, B, OUT1 respectively.

Pins P5

and ON-SCREEN DISPLAY CONTROLLER

CC and AVCC, and 0 V to VSS.

µ

s or more (under

IN and

2

C-

6

MITSUBISHI MICROCOMPUTERS

M37274MA-XXXSP

PRELIMINARY

Notice: This is not a final specification.

Some paramentic limits are subject to change.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER

and ON-SCREEN DISPLAY CONTROLLER

PIN DESCRIPTION (continued)

Pin Name Functions

P63/OSC1/
X

CIN,

P6

4/OSC2/

X

COUT

Input port
Clock input for OSD
Clock output for OSD
Sub-clock output
Sub-clock input

P70/CVIN,
P71/VHOLD,
P7

2/RVCO

HLF/AD

Input port P7
Input for data slicer

Input/output for

data slicer

6

Analog input
HSYNC
VSYNC

H

SYNC input
SYNC input

V

Note : As shown in the memory map (Figure 5), port P0 is accessed as a memory at address 00C016 of zero page. Port P0 has the port P0

direction register (address 00C1
programmed as “1” in the direction register are output pins. When pins are programmed as “0,” they are input pins. When pins are
programmed as output pins, the output data are written into the port latch and then output. When data is read from the output pins, the
output pin level is not read but the data of the port latch is read. This allows a previously-output value to be read correctly even if the
output “L” voltage has risen, for example, because a light emitting diode was directly driven. The input pins float, so the values of the pins
can be read. When data is written into the input pin, it is written only into the port latch, while the pin remains in the floating state.

Input/

Output

Input

Input
Output
Output

Input

Input

Input

Ports P63 and P64 are 2-bit input port.
Pin P6

3 is also used as OSD clock input pin OSC1.
4 is also used as OSD clock output pin OSC2. The output structure is CMOS output.

Pin P6
Pin P6

4 is also used as sub-clock output pin XCOUT. The output structure is CMOS output.
3 is also used as sub-clock input pin XCIN.

Pin P6

0–P72 are 3-bit input port.

Ports P7
Pins P7

0, P71 are also used as data slicer input pins CVIN, VHOLD respectively. When

using data slicer, input composite video signal through a capacitor. Connect a capacitor

I/O

between V
Pins P7

connect a resistor between RVCO and V

HOLD and VSS.

2 pin is also used as input/output pin for data slicer RVCO. When using data slicer,

SS.

When using data slicer, connect a filter using of a capacitor and a resistor between HLF
and V

SS.

Input

Input

Input

16 of zero page) which can be used to program each bit as an input (“0”) or an output (“1”). The pins

This is an analog input pin AD6.
This is a horizontal synchronous signal input for OSD.

This is a vertical synchronous signal input for OSD.

7

MITSUBISHI MICROCOMPUTERS

M37274MA-XXXSP

PRELIMINARY

Notice: This is not a final specification.

Some paramentic limits are subject to change.

3

Ports P0

Ports P0

, P10, P15–P17, P2, P30, P3

Data bus

0

–P02, P04–P0

7

Data bus

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER

and ON-SCREEN DISPLAY CONTROLLER

1

Direction register

Port latch

Direction register

Port latch

CMOS output

Ports P0

3, P10, P15–P17,

0, P31

P2, P3

Note : Each port is also used as follows :

3/DA

P0

0 : OUT2

P1

6 : INT3

P1
P1

7 : SIN

P24–P26 : AD3–AD1

7 : AD5

P2

N-channel open-drain output

Ports P0

0–P02, P04–P07

Note : Each port is also used as follows :

0–P02 : PWM4–PWM6

P0

4–P07 : PWM0–PWM3

P0

Ports P11–P1

4

Data bus

Fig. 1. I/O Pin Block Diagram (1)

Direction register

Port latch

N-channel open-drain output

Port P1

1-P14

Note : Each port is also used as follows :

1 : SCL1

P1

2 : SCL2

P1

3 : SDA1

P1

4 : SDA2

P1

8

MITSUBISHI MICROCOMPUTERS

M37274MA-XXXSP

PRELIMINARY

Notice: This is not a final specification.

Some paramentic limits are subject to change.

S

OUT

, S

CLK

Data bus

H

SYNC

, V

SYNC

Internal circuit

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER

and ON-SCREEN DISPLAY CONTROLLER

N-channel open-drain output

Direction register

Schmidt input

SYNC, VSYNC

H

P52–P5

5

Ports P4

5, P46

Note : Each pin is also used

as follows :

5 : SOUT

P4
P46 : SCLK

CMOS output

0

–P4

Ports P4

4

Data bus

Fig. 2. I/O Pin Block Diagram (2)

Internal circuit

Input

Ports P40–P44
Note : Each port is also used as below :

0 : AD4

P4

1 : INT2

P4

2 : TIM2

P4

3 : TIM3

P4

4 : INT1

P4

P52–P55

Note : Each port is also used

as follows :

2 : R P54 : B

P5

3 : G P55 : OUT1

P5

9

MITSUBISHI MICROCOMPUTERS

M37274MA-XXXSP

PRELIMINARY

Notice: This is not a final specification.

Some paramentic limits are subject to change.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER

FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)

The M37274MA-XXXSP uses the standard 740 Family instruction
set. Refer to the table of 740 Family addressing modes and machine
instructions or the SERIES 740 <Software> User’s Manual for de­tails on the instruction set.
Machine-resident 740 Family instructions are as follows:
The FST, SLW instruction cannot be used.
The MUL, DIV, WIT and STP instructions can be used.

70

11 00

CPU mode register
(CPUM (CM) : address 00FB

Processor mode bits

b1 b0

0 0 : Single-chip mode
0 1 :
1 0 :
1 1 :

Stack page selection bit (Note)
0 : Zero page

1 : 1 page
Fix these bits to “1.”
X

0 : LOW drive
1 : HIGH drive

Main colock (X
0 : Oscillating
1 : Stopped

Internal system clock selection bit
0 : X
1 : X

and ON-SCREEN DISPLAY CONTROLLER

CPU Mode Register

The CPU mode register contains the stack page selection bit and
internal system clock selection bit. The CPU mode register is allo­cated at address 00FB

Not available

COUT

drivability selection bit

IN–XOUT

IN–XOUT

selected (high-speed mode)

CIN–XCOUT

) stop bit

selected (low-speed mode)

16.

16

)

Fig. 3. CPU Mode Register

Note: This bit is set to “1” after the reset release.

10

MITSUBISHI MICROCOMPUTERS

M37274MA-XXXSP

PRELIMINARY

Notice: This is not a final specification.

Some paramentic limits are subject to change.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER

MEMORY
Special Function Register (SFR) Area

The special function register (SFR) area in the zero page contains
control registers such as I/O ports and timers.

RAM

RAM is used for data storage and for stack area of subroutine calls
and interrupts.

ROM

ROM is used for storing user programs as well as the interrupt vector
area.

RAM for OSD

RAM for display is used for specifying the character codes and col­ors to display.

ROM for OSD

ROM for display is used for storing character data.

0000

16

Zero page

ROM correction memory
Block 1 : addresses 02C0
Block 2 : addresses 02E016 to 02FF

RAM

(768 bytes)

00C0
00FF

0200
0248

02C0
02FF

0300

16

16

16

16

16

16

SFR1 area

SFR2 area

Not used

16

and ON-SCREEN DISPLAY CONTROLLER

Interrupt Vector Area

The interrupt vector area contains reset and interrupt vectors.

Zero Page

The 256 bytes from addresses 000016 to 00FF16 are called the zero
page area. The internal RAM and the special function registers (SFR)
are allocated to this area.
The zero page addressing mode can be used to specify memory and
register addresses in the zero page area. Access to this area with
only 2 bytes is possible in the zero page addressing mode.

Special Page

The 256 bytes from addresses FF0016 to FFFF16 are called the spe­cial page area. The special page addressing mode can be used to
specify memory addresses in the special page area. Access to this
area with only 2 bytes is possible in the special page addressing
mode.

ROM Correction Memory (RAM)

This is used as the program area for ROM correction.

10000

16

to 02DF

16

16

10800

155FF

16

16

16

18000

16

Not used

Not used

RAM for OSD (Note)

(1296 bytes)

ROM

(40 K bytes)

Fig. 4. Memory map

043F

0800
0DF3

6000

FF00
FFDE

FFFF

16

16

16

16

16

16

Interrupt vector area

16

Not used

Not used

Special page

ROM for OSD
(11072 bytes)

1E41F

16

1FFFF

16

Note : Refer to Table 15. Contents of OSD RAM.

Not used

11

MITSUBISHI MICROCOMPUTERS

M37274MA-XXXSP

PRELIMINARY

Notice: This is not a final specification.

Some paramentic limits are subject to change.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER

■SFR1 area (addresses C016 to DF16)

<

Bit allocation

Name

0

1

Address

C0

16

C1

16

C2

16

C3

16

C4

16

C5

16

C6

16

C7

16

C8

16

C9

16

CA

16

CB

16

CC

16

CD

16

CE

16

CF

16

D0

16

D1

16

D2

16

D3

16

D4

16

D5

16

D6

16

D7

16

D8

16

D9

16

DA

16

DB

16

DC

16

DD

16

DE

16

DF

16

Register

Port P0 (P0)
Port P0 direction register (D0)
Port P1 (P1)
Port P1 direction register (D1)
Port P2 (P2)
Port P2 direction register (D2)
Port P3 (P3)
Port P3 direction register (D3)
Port P4 (P4)

Port P4 direction register (D4)
Port P5 (P5)
OSD port control register (PF)

Port P6 (P6)
Port P7 (P7)

OSD control register (OC)
Horizontal position register (HP)
Block control register 1 (BC
Block control register 2 (BC
Block control register 3 (BC
Block control register 4 (BC
Block control register 5 (BC
Block control register 6 (BC
Block control register 7 (BC
Block control register 8 (BC
Block control register 9 (BC
Block control register 10 (BC
Block control register 11 (BC
Block control register 12 (BC

)

1

)

2

)

3

)

4

)

5

)

6

)

7

)

8

)

9

10
11

12

b7

0

)
)

)

and ON-SCREEN DISPLAY CONTROLLER

>

:

Function bit

:
:

No function bit

: Fix to this bit to “0”

<

State immediately after reset

: “0” immediately after reset

0

: “1” immediately after reset

1

: Indeterminate immediately

?

after reset
(do not write to “1”)
: Fix to this bit to “1”

(do not write to “0”)

Bit allocation State immediately after reset

b0

b7

?

00

?

00

?

00

?

T3SC

00

?

0

00

?

OUT1OUT2

R0 0GB

00

?

00?00??0

OC6OC7 OC4OC5 OC2OC3 OC0OC1

HP6HP7 HP4HP5 HP2HP3 HP0HP1

BC11BC12BC13BC14BC15BC16BC17BC18
BC21BC22BC23BC24BC25BC26BC27BC28
BC31BC32BC33BC34BC35BC36BC37BC38
BC41BC42BC43BC44BC45BC46BC47BC48
BC51BC52BC53BC54BC55BC56BC57BC58
BC61BC62BC63BC64BC65BC66BC67BC68
BC71BC72BC73BC74BC75BC76BC77BC78
BC81BC82BC83BC84BC85BC86BC87BC88
BC91BC92BC93BC94BC95BC96BC97BC98

BC101BC102BC103BC104BC105BC106BC107BC108
BC111BC112BC113BC114BC115BC116BC117BC118
BC121BC122BC123BC124BC125BC126BC127BC128

00
00

?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?

>

b0

16

16

16

16

16

16

16
16

Fig. 5. Memory Map of Special Function Register 1 (SFR1) (1)

12

MITSUBISHI MICROCOMPUTERS

M37274MA-XXXSP

PRELIMINARY

Notice: This is not a final specification.

Some paramentic limits are subject to change.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER

and ON-SCREEN DISPLAY CONTROLLER

■SFR1 area (addresses E016 to FF16)

<

Bit allocation

:

Function bit

:

Name

:

No function bit

: Fix to this bit to “0”

0

(do not write to “1”)
: Fix to this bit to “1”

1

(do not write to “0”)

Address Register Bit allocation State immediately after reset

Caption position register (CP)

E0

16

Start bit position register (SP)

E1

16

E2

16

Window register (WN)

E3

16

Sync slice register (SSL)

E4

16

Data register 1 (CD1)

E5

16

Data register 2 (CD2)

E6

16

Clock run-in register 1 (CR1)
Clock run-in register 2 (CR2)

E7

16

Clock run-in detect register 1 (CRD1)

E8

16

Clock run-in detect register 2 (CRD2)

E9

16

Data slicer control register 1 (DSC1)

EA

16

Data slicer control register 2 (DSC2)

EB

16

EC

16

Data register 3 (CD3)
Data register 4 (CD4)

ED

16

A-D conversion register (AD)

EE

16

EF

16

A-D control register (ADCON)

F0

16

Timer 1 (TM1)
Timer 2 (TM2)

F1

16

F2

16

Timer 3 (TM3)

F3

16

Timer 4 (TM4)

F4

16

Timer mode register 1 (TM1)

F5

16

Timer mode register 2 (TM2)

I2C

F6
F7
F8

F9
FA
FB
FC
FD
FE
FF

data shift register (S0)

16
16

I2C

address register (S0D)

I2C

status register (S1)

16

I2C

control register (S1D)

16

I2C

clock control register (S2)

16
16

CPU mode

16

Interrupt request

16

Interrupt request
Interrupt control

16

16

Interrupt control

register (CPUM)

register 1 (IREQ1)
register 2 (IREQ2)

register 1 (ICON1)
register 2 (ICON2)

b7

100

00

SSL7

0000 011

0101
100111 1

000
000

0

TM26TM27

BSEL0BSEL1

ACK

ACK

BIT

CM7 CM5CM6

0

ADE

>

CR13 CR12 CR10

CRD15CRD17CRD15 CRD15CRD15

ADVREF

ADSTR

ADIN2

TM15TM16TM17
TM25

10 BIT
SAD
FAST
MODE

11 00

INT2R

IICRT56R

CK0

IICET56ET56S

CM2

1MSR

1MSE

b0
CP0CP1CP2CP3CP4
SP0SP1SP2SP3SP4SP5SP6SP7
WN0WN1WN2WN3WN4WN5

CR11
CR21

CRD20CRD21CRD22CRD25CRD27CRD25 CRD25 CRD25
DSC10DSC11DSC12DSC15DSC17

DSC20DSC21DSC22DSC25DSC27

ADIN0ADIN1

TM10TM11TM12TM13TM14
TM20TM21TM22TM23TM24

SAD0SAD1SAD2SAD3SAD4SAD5SAD6 RBW

LRBAD0AASALPINBBTRXMST
BC0BC1BC2ES0ALS
CCR0CCR1CCR2CCR3CCR4

TM1RTM2RTM3RTM4RCRTRVSCRADR

INT1R

DSRSIOR

TM1ETM2ETM3ETM4ECRTEVSCE

INT1EDSESIOEINT2E

State immediately after reset

<

: “0” immediately after reset

0

: “1” immediately after reset

1

: Indeterminate immediately

?

>

after reset

b7

00

16

00

16

00

16

00

16

00

16

00

16

00

16

00

16

00

16

00

16

? 0?00 00 0
? 0?00 0? 0

00

16

00

16

?

?0010000

16

FF
07

16

FF

16

07

16

00

16

00

16

?

00

16

000001?0

00

16

00

16

10 0 111 00

00

16

00

16

00

16

00

16

b0

Fig. 6. Memory Map of Special Function Register 1 (SFR2) (2)

13

MITSUBISHI MICROCOMPUTERS

M37274MA-XXXSP

PRELIMINARY

Notice: This is not a final specification.

Some paramentic limits are subject to change.

■

SFR2 area (addresses 200

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER

and ON-SCREEN DISPLAY CONTROLLER

16

to 21F16)

<

Bit allocation

:

Function bit

:

Name

:

No function bit

: Fix to this bit to “0”

0

>

<

State immediately after reset

: “0” immediately after reset

0

: “1” immediately after reset

1

: Indeterminate immediately

?

>

after reset

(do not write to “1”)

: Fix to this bit to “1”

1

(do not write to “0”)

Address Register Bit allocation State immediately after reset

SYC1SYC2SYC3SYC4SYC5

RE1RE2RE5
SM1SM2SM3SM5

RE1RE2RE3RE5
PC1PC2PC5PC6PC7
RC1RC2RC5RC6RC7
RE1RE2RE3RE5

WL11

b0

b7

? ???0 00

PN0PN1PN2

PW0PW1PW2PW3PW4PW5PW6

SYC0

DSC30DSC31DSC32DSC37 DSC35

SM0RE1RE2RE3SM4RE5

CS0CS4 CS1CS2CS3CS5CS6
PC0RE1RE2RE3PC4RE5
RC0RE1RE2RE3RE5

EC0EC1EC2

FC0FC1

WH10WH11
WL10
WH20WH21

WL20WL21

00

00
07
FF
00
00
00

00
00

00

00
00
00
00

?
?
?
?
?
?
?
?

16

?

16
16

16
16
16
16

?

16
16

?
?

16

01 0 000 00

16
16
16
16

?
?

?
?

200
201
202
203

204
205
206

207
208
209
20A
20B
20C

20D
20E
20F
210

211
212
213
214
215

216
217
218

219
21A
21B
21C
21D
21E
21F

PWM0 register (PWM0)

16
16

PWM1 register (PWM1)

16

PWM2 register (PWM2)

16

PWM3 register (PWM3)

16

PWM4 register (PWM4)

16

PWM5 register (PWM5)

16

PWM6 register (PWM6)

16

Clock run-in detect register 3 (CRD3)

16
16

Clock run-in register (CR3)

16

PWM mode register 1 (PN)

16

PWM mode register 2 (PW)

16

Timer 5 (TM5)
Timer 6 (TM6)

16
16

Sync pulse counter register (SYC)

16

Data slicer control register 3 (DSC3)

16
16

Interrupt input polarity register (IP)

16

Serial I/O mode register (SM)

16

Serial I/O register (SIO)

16
16
16

Clock source control register (CS)

16

I/O polarity control register (PC)

16

Raster color register (RC)
Extra font color register (EC)

16

16
16

Border color register (FC)

16

Window H register 1 (WH1)

16

Window L register 1 (WH1)
Window H register 2 (WH2)

16

Window L register 2 (WH2)

16

b7

CRD31CRD32CRD33CRD34CRD35

CR36 CR35 CR34 CR33 CR32 CR31 CR30

PN3

0

16

00

DSC36 DSC34DSC33

INT3

INT3

AD/INT3

AD/INT3
SEL

SEL

POL

POL
INT3

AD/INT3

00

SEL

POL

0

INT3

AD/INT3

0

SEL

POL
INT3

AD/INT3
SEL

POL
INT3

AD/INT3
SEL

POL
INT3

AD/INT3
SEL

POL

INT2
POL

INT1
POL

0000

00

00000

FC2

00

WH14

WH15

WH16

WH17
WL17

WL16

WL15

WL14

WL13

WH12WH13
WL12

b0

0

Fig. 7. Memory Map of Special Function Register 2 (SFR2) (1)

14

MITSUBISHI MICROCOMPUTERS

M37274MA-XXXSP

PRELIMINARY

Notice: This is not a final specification.

Some paramentic limits are subject to change.

■

SFR2 area (addresses 220

Address Register Bit allocation State immediately after reset

Vertical position register 1

220

16

Vertical position register 1

221

16

Vertical position register 1

222

16

Vertical position register 14 (VP14)

223

16

Vertical position register 15 (VP15)

224

16

Vertical position register 1

225

16

Vertical position register 1

226

16

Vertical position register 18 (VP18)

227

16

Vertical position register 1

228

16

Vertical position register 1

229

16

Vertical position register 1

22A

16

Vertical position register 1

22B

16

22C

16

22D

16

22E

16

22F

16

Vertical position register 2

230

16

Vertical position register 2

231

16

Vertical position register 2

232

16

233

16

Vertical position register 2

234

16

Vertical position register 2
Vertical position register 2

235

16

Vertical position register 2

236

16

237

16

Vertical position register 2
Vertical position register 2

238

16

Vertical position register 2

239

16

23A

16

Vertical position register 2
Vertical position register 2

23B

16

23C

16

23D

16

23E

16

23F

16

DA-H register (DA-H)

16

240

DA-L register (DA-L)

241

16

ROM correction address 1 (high-order)

242

16

ROM correction address 1 (low-order)

243

16

244

16

ROM correction address 2 (high-order)

245

16

ROM correction address 2 (low-order)
ROM correction enable register (RCR)

246

16

247

16
16

248

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER

and ON-SCREEN DISPLAY CONTROLLER

16 to 24816)

<

Bit allocation

:

Function bit

:

Name

:

No function bit

: Fix to this bit to “0”

0

(do not write to “1”)
: Fix to this bit to “1”

1

>

State immediately after reset

<

: “0” immediately after reset

0

: “1” immediately after reset

1

: Indeterminate immediately

?

after reset

>

(do not write to “0”)

(VP11)

1

(VP12)

2

(VP13)

3

(VP16)

6

(VP17)

7

(VP19)

9

(VP110)

10

(VP111)

11

(VP112)

12

b7 b0 b7 b0

VP111

VP112VP113VP114VP115VP116VP117VP118

VP121VP122VP123VP124VP125VP126VP127VP128
VP131VP132VP133VP134VP135VP136VP137VP138
VP141VP142VP143VP144VP145VP146VP147VP148
VP151VP152VP153VP154VP155VP156VP157VP158
VP161VP162VP163VP164VP165VP166VP167VP168
VP171VP172VP173VP174VP175VP176VP177VP178
VP181VP182VP183VP184VP185VP186VP187VP188
VP191VP192VP193VP194VP195VP196VP197VP198

VP1101VP1102VP1103VP1104VP1105VP1106VP1107VP1108
VP1111VP1112VP1113VP1114VP1115VP1116VP1117VP1118
VP1121VP1122VP1123VP1124VP1125VP1126VP1127VP1128

?
?
?
?
?
?
?
?
?

?
?
?
?

?
?
?

(VP21)

1

(VP22)

2

(VP23)

3

(VP24)

4

(VP25)

5

(VP26)

6

(VP27)

7

(VP28)

8

(VP29)

9
10
11

12

(VP210)
(VP211)

(VP212)

VP211VP212
VP221VP222
VP231VP232
VP241VP242
VP251VP252
VP261VP262
VP271VP272
VP281VP282
VP291VP292

VP2101VP2102
VP2111VP2112
VP2121VP2122

?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?

00??????

00

16

00

16

00

16

00

16

00

RCR0RCR1

00

16

000

00
00
00

16
16
16

Fig. 8. Memory Map of Special Function Register 2 (SFR2) (2)

15

MITSUBISHI MICROCOMPUTERS

M37274MA-XXXSP

PRELIMINARY

Notice: This is not a final specification.

Some paramentic limits are subject to change.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER

<

Bit allocation

>

:

Function bit

:

Name

:

No function bit

: Fix to this bit to “0”

0

(do not write to “1”)
: Fix to this bit to “1”

1

(do not write to “0”)

Register

b7

Processor status register (PS)
Program counter (PCH)

Program counter (PCL)

Fig. 9. Internal State of Processor Status Register and Program Counter at Reset

Bit allocation State immediately after reset

I ZCDBTVN?????

and ON-SCREEN DISPLAY CONTROLLER

<

State immediately after reset

: “0” immediately after reset

0

: “1” immediately after reset

1

: Indeterminate immediately

?

>

after reset

b0

b7

?

1
Contents of address FFFF
Contents of address FFFE

b0

?

16
16

16

MITSUBISHI MICROCOMPUTERS

M37274MA-XXXSP

PRELIMINARY

Notice: This is not a final specification.

Some paramentic limits are subject to change.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER

INTERRUPTS

Interrupts can be caused by 18 different sources consisting of 4 ex­ternal, 12 internal, 1 software, and reset. Interrupts are vectored in­terrupts with priorities as shown in Table 1. Reset is also included in
the table because its operation is similar to an interrupt.
When an interrupt is accepted,
(1) The contents of the program counter and processor status

register are automatically stored into the stack.

(2) The interrupt disable flag I is set to “1” and the corresponding

interrupt request bit is set to “0.”

(3) The jump destination address stored in the vector address enters

the program counter.
Other interrupts are disabled when the interrupt disable flag is set to
“1.”
All interrupts except the BRK instruction interrupt have an interrupt
request bit and an interrupt enable bit. The interrupt request bits are
in interrupt request registers 1 and 2 and the interrupt enable bits are
in interrupt control registers 1 and 2. Figure 11 shows the interrupt­related registers.
Interrupts other than the BRK instruction interrupt and reset are ac­cepted when the interrupt enable bit is “1,” interrupt request bit is “1,”
and the interrupt disable flag is “0.” The interrupt request bit can be
set to “0” by a program, but not set to “1.” The interrupt enable bit can
be set to “0” and “1” by a program.
Reset is treated as a non-maskable interrupt with the highest priority.
Figure 10 shows interrupt control.

and ON-SCREEN DISPLAY CONTROLLER

Interrupt Causes

(1) VSYNC and OSD interrupts

SYNC interrupt is an interrupt request synchronized with

The V
the vertical sync signal.
The OSD interrupt occurs after character block display to the
CRT is completed.

(2) INT1, INT2, INT3 interrupts

With an external interrupt input, the system detects that the level
of a pin changes from “L” to “H” or from “H” to “L,” and generates
an interrupt request. The input active edge can be selected by
bits 3, 4 and 6 of the interrupt input polarity register (address

16) : when this bit is “0,” a change from “L” to “H” is detected;

0212
when it is “1,” a change from “H” to “L” is detected. Note that all
bits are cleared to “0” at reset.

(3) Timer 1, 2, 3 and 4 interrupts

An interrupt is generated by an overflow of timer 1, 2, 3 or 4.

(4) Serial I/O interrupt

This is an interrupt request from the clock synchronous serial
I/O function.

IN)/4096 interrupt

(5) f(X

This interrupt occurs regularly with a f(X
of the PWM mode register 1 to “0.”

(6) Data slicer interrupt

An interrupt occurs when slicing data is completed.

(7) Multi-master I

This is an interrupt request related to the multi-master I
interface.

(8) A-D conversion interrupt

An interrupt occurs at the completion of A-D conversion. Since
A-D conversion interrupt and the INT3 interrupt share the same
vector, an interrupt source is selected by bit 7 of the interrupt
interval determination control register (address 0212

2

C-BUS interface interrupt

IN)/4096 period. Set bit 0

16).

2

C-BUS

Table 1. Interrupt Vector Addresses and Priority

Interrupt Source
Reset
OSD interrupt
INT1 interrupt
Data slicer interrupt
Serial I/O interrupt
Timer 4 interrupt

IN)/4096 interrupt

f(X

SYNC interrupt

V
Timer 3 interrupt
Timer 2 interrupt
Timer 1 interrupt
A-D convertion · INT3 interrupt

INT2 interrupt
Multi-master I
Timer 5 · 6 interrupt
BRK instruction interrupt

Note : Switching a source during a program causes an unnecessary interrupt occurs. Accordingly, set a source at initializing of program.

2

C-BUS interface interrupt

Priority

1
2
3
4
5
6
7
8

9
10
11
12

13
14
15
16

Vector Addresses

16, FFFE16

FFFF
FFFD16, FFFC16
FFFB16, FFFA16
FFF916, FFF816
FFF716, FFF616
FFF516, FFF416
FFF316, FFF216
FFF116, FFF016
FFEF16, FFEE16
FFED16, FFEC16
FFEB16, FFEA16
FFE916, FFE816

FFE716, FFE616
FFE516, FFE416
FFE316, FFE216
FFDF16, FFDE16

Remarks

Non-maskable

Active edge selectable

Active edge selectable

Software switch by software (See note)/
When selecting INT3 interrupt, active edge selectable.
Active edge selectable

Software switch by software (See note)
Non-maskable (software interrupt)

17

MITSUBISHI MICROCOMPUTERS

M37274MA-XXXSP

PRELIMINARY

Notice: This is not a final specification.

Some paramentic limits are subject to change.

(9)Timer 5 · 6 interrupt

An interrupt is generated by an overflow of timer 5 or 6. Their
priorities are same, and can be switched by software.

(10)BRK instruction interrupt

This software interrupt has the least significant priority. It does
not have a corresponding interrupt enable bit, and it is not af­fected by the interrupt disable flag I (non-maskable).

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER

and ON-SCREEN DISPLAY CONTROLLER

Interrupt request bit

Interrupt enable bit

Interrupt disable flag I

Fig. 10. Interrupt Control

BRK instruction

Reset

Interrupt
request

18

MITSUBISHI MICROCOMPUTERS

M37274MA-XXXSP

PRELIMINARY

Notice: This is not a final specification.

Some paramentic limits are subject to change.

7

7

0

0

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER

and ON-SCREEN DISPLAY CONTROLLER

Interrupt request register 1
(IREQ1: address 00FC

Timer 1 interrupt request bit
Timer 2 interrupt request bit
Timer 3 interrupt request bit
Timer 4 interrupt request bit
OSD interrupt request bit
V

SYNC

interrupt request bit

A-D conversion
request bit

Interrupt control register 1
( ICON1: address 00FE

16

INT3 interrupt

•

7

)

0 : No interrupt request issued
1 : Interrupt request issued

16

)

0

7

0

Interrupt request register 2
(IREQ2: address 00FD

INT1 interrupt request bit
Data slicer interrupt request bit
Serial I/O interrupt request bit
f(XIN)/4096 interrupt request bit

INT2 interrupt request bit
Multi-master I2C-BUS

interface interrupt request bit
Timer 5

• 6 interrupt request bit

Fix this bit to “0.”

0

Interrupt control register 2
( ICON2 : address 00FF

16

16

)

)

7 0

0 0

Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
Timer 3 interrupt enable bit
Timer 4 interrupt enable bit
OSD interrupt enable bit
V

SYNC

interrupt enable bit

A-D conversion• INT3 interrupt
request bit

0 : Interrupt disabled
1 : Interrupt enabled

Interrupt input polarity register

00

(IP : address 0212

Fix these bits to “0.”
INT1 polarity switch bit

0 : Positive polarity
1 : Negative polarity

INT2 polarity switch bit

0 : Positive polarity

1 : Negative polarity
Fix this bit to “0.”
INT3 polarity switch bit

0 : Positive polarity

1 : Negative polarity
A-D conversion. INT3 interrupt source selection bit

0 : INT3 interrupt

1 : A-D conversion interrupt

16

)

INT1 interrupt enable bit
Data slicer interrupt enable bit
Serial I/O interrupt enable bit
f(XIN)/4096 interrupt enable bit

INT2 interrupt enable bit
Multi-master I

interface enable bit
Timer 5

Timer 5

0 : Timer 5
1 : Timer 6

2

C-BUS

• 6 interrupt enable bit

• 6 interrupt switch bit

Fig. 11. Interrupt-related Registers

19

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PRELIMINARY

Notice: This is not a final specification.

Some paramentic limits are subject to change.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER

TIMERS

The M37271MF-XXXSP has 6 timers: timer 1, timer 2, timer 3,
timer 4, timer 5, and timer 6. All timers are 8-bit timers with the 8-bit
timer latch. The timer block diagram is shown in Figure 13.
All of the timers count down and their divide ratio is 1/(n+1), where n
is the value of timer latch. By writing a count value to the correspond­ing timer latch (addresses 00F0

16 and 020D16 : timers 5 and 6), the value is also set to a timer,

020C
simultaneously.
The count value is decremented by 1. The timer interrupt request bit
is set to “1” by a timer overflow at the next count pulse, after the
count value reaches “00

16 to 00F316 : timers 1 to 4, addresses

16”.

(1) Timer 1

Timer 1 can select one of the following count sources:

f(XIN)/16 or f(XCIN)/16

•

f(XIN)/4096 or f(XCIN)/4096

•

External clock from the P42 TIM2 pin

•

The count source of timer 1 is selected by setting bits 5 and 0 of
timer mode register 1 (address 00F4
selected by bit 7 of the CPU mode register.
Timer 1 interrupt request occurs at timer 1 overflow.

16). Either f(XIN) or f(XCIN) is

(2) Timer 2

Timer 2 can select one of the following count sources:

f(XIN)/16 or f(XCIN)/16

•

Timer 1 overflow signal

•

External clock from the TIM2 pin

•

The count source of timer 2 is selected by setting bits 4 and 1 of
timer mode register 1 (address 00F4
selected by bit 7 of the CPU mode register. When timer 1 overflow
signal is a count source for the timer 2, the timer 1 functions as an 8­bit prescaler.
Timer 2 interrupt request occurs at timer 2 overflow.

16). Either f(XIN) or f(XCIN) is

(3) Timer 3

Timer 3 can select one of the following count sources:

f(XIN)/16 or f(XCIN)/16

•

f(XCIN)

•

External clock from the TIM3 pin

•

The count source of timer 3 is selected by setting bit 0 of timer mode
register 2 (address 00F5

CIN) is selected by bit 7 of the CPU mode register.

or f(X
Timer 3 interrupt request occurs at timer 3 overflow.

16) and bit 6 at address 00C716. Either f(XIN)

and ON-SCREEN DISPLAY CONTROLLER

(5) Timer 5

Timer 5 can select one of the following count sources:

f(XIN)/16 or f(XCIN)/16

•

Timer 2 overflow signal

•

Timer 4 overflow signal

•

The count source of timer 3 is selected by setting bit 6 of timer mode
register 1 (address 00F4
dress 00F5
timer 5, either timer 2 or 4 functions as an 8-bit prescaler. Either
f(X
Timer 5 interrupt request occurs at timer 5 overflow.

16). When overflow of timer 2 or 4 is a count source for

IN) or f(XCIN) is selected by bit 7 of the CPU mode register.

16) and bit 7 of timer mode register 2 (ad-

(6) Timer 6

Timer 6 can select one of the following count sources:

f(XIN)/16 or f(XCIN)/16

•

Timer 5 overflow signal

•

The count source of timer 6 is selected by setting bit 7 of timer mode
register 1 (address 00F4
7 of the CPU mode register. When timer 5 overflow signal is a count
source for timer 6, timer 5 functions as an 8-bit prescaler.
Timer 6 interrupt request occurs at timer 6 overflow.

At reset, timers 3 and 4 are connected by hardware and “FF
automatically set in timer 3; “07
lected as the timer 3 count source. The internal reset is released by
timer 4 overflow in this state and the internal clock is connected.
At execution of the STP instruction, timers 3 and 4 are connected by
hardware and “FF
However, the f(X
So set both bit 0 of timer mode register 2 (address 00F5
at address 00C7

✽

IN)

/16 is selected as the timer 3 count source). The internal

(f(X
STP state is released by timer 4 overflow in this state and the inter­nal clock is connected.
As a result of the above procedure, the program can start under a
stable clock.
✽ : When bit 7 of the CPU mode register (CM

comes f(X

The structure of timer-related registers is shown in Figure 12.

CIN).

16). Either f(XIN) or f(XCIN) is selected by bit

16” is

16” in timer 4. The f(XIN)

16” is automatically set in timer 3; “0716” in timer 4.

✽

IN)

/16 is not selected as the timer 3 count source.

16 to “0” before execution of the STP instruction

✽

/16 is se-

16) and bit 6

7) is “1,” f(XIN) be-

(4) Timer 4

Timer 4 can select one of the following count sources:

f(XIN)/16 or f(XCIN)/16

•

f(XIN)/2 or f(XCIN)/2

•

f(XCIN)

•

The count source of timer 3 is selected by setting bits 1 and 4 of
timer mode register 2 (address 00F5
selected by bit 7 of the CPU mode register. When timer 3 overflow
signal is a count source for the timer 4, the timer 3 functions as an 8­bit prescaler.
Timer 4 interrupt request occurs at timer 4 overflow.

20

16). Either f(XIN) or f(XCIN) is

MITSUBISHI MICROCOMPUTERS

M37274MA-XXXSP

PRELIMINARY

Notice: This is not a final specification.

Some paramentic limits are subject to change.

70

Timer mode register 1
(TM1 : address 00F4

Timer 1 count source selection bit 1
0 : f(X
1 : Count source selected by bit 5
of TM1

Timer 2 count source selection bit 1
0 : Count source selected by bit 4 of
TM1
1 : External clock from TIM2 pin

Timer 1 count stop bit
0 : Count start
1 : Count stop

Timer 2 count stop bit
0 : Count start
1 : Count stop

Timer 2 count source selection bit 2
0 : f(X
1 : Timer 1 overflow

Timer 1 count source selection bit 2
0 : f(X
1 : External clock from TIM2 pin

Timer 5 count source selection bit 2
0 : Timer 2 overflow
1 : Timer 4 overflow

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER

and ON-SCREEN DISPLAY CONTROLLER

IN

)/16 or f(X

IN

)/16 or f(X

IN

)/4096 or f(X

16

)

CIN

)/16 (Note)

CIN

)/16 (Note)

CIN

)/4096 (Note)

70

Timer mode register 2
(TM2 : address 00F5

16

)

Timer 3 count source selection bit

(Bit 6 at
address

16

)

00C7

b0

0 0 : f(X
1 0 : f(X
0 1 :

1 1 :

IN

)/16 or f(X

CIN

External clock from
TIM3 pin

CIN

)

Timer 4 count source selection bits
b4 b1
0 0 : Timer 3 overflow
0 1 : f(X
1 0 : f(X
1 1 : f(X

Timer 3 count stop bit
0 : Count start

IN

)/16 or f(X

IN

)/2 or f(X

CIN

)

CIN

1 : Count stop

Timer 4 count stop bit
0 : Count start
1 : Count stop

Timer 5 count stop bit
0 : Count start
1 : Count stop

)/16 (Note)

CIN

)/16 (Note)

)/2 (Note)

IN

) or f(X

Note : Either f(X

CIN

Fig. 12. Timer-related Registers

Timer 6 count source selection bit

IN

0 : f(X
1 : Timer 5 overflow

)/16 or f(X

CIN

)/16 (Note)

) is selected by bit 7 of the CPU mode register.

Timer 6 count stop bit
0 : Count start
1 : Count stop

Timer 5 count source selection bit 1
0 : f(X

IN

1 : Count source selected by bit 6

)/16 or f(X

of TM1

CIN

)/16 (Note)

21

MITSUBISHI MICROCOMPUTERS

M37274MA-XXXSP

PRELIMINARY

Notice: This is not a final specification.

Some paramentic limits are subject to change.

CIN

X

X

TIM2

TIM3

IN

CM7

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER

and ON-SCREEN DISPLAY CONTROLLER

Data bus

8

1/4096

1/2

TM15

1/8

TM10

TM14

TM11

TM20

TM12

TM13

TM3EL

TM22

Timer 1 latch (8)

8

Timer 1 (8)

Timer 2 latch (8)

8

Timer 2 (8)

Timer 3 latch (8)

8

Timer 3 (8)

Timer 1
interrupt request

8

8

Timer 2
interrupt request

8

8

FF

16

Reset
STP instruction

Timer 3
interrupt request

8

8

07

16

8

8

8

8

TM21

Selection gate : Connected to

black side at
reset

TM1 : Timer mode register 1
TM2 : Timer mode register 2
TM3EL : Timer 3 count source
switch bit (address 00C7

TM24

TM21

TM23

Timer 4 latch (8)

8

Timer 4 (8)

TM16

Timer 5 latch (8)

8

TM27

TM25

16

)

Timer 5 (8)

CM : CPU mode register

Timer 6 latch (8)

8

TM17

TM26

Timer 6 (8)

8

Notes 1: HIGH pulse width of external clock inputs TIM2 and TIM3 needs 4 machine cycles or more.

2: When the external clock source is selected, timers 1, 2, and 3 are counted at a rising edge of input signal.
3: In the stop mode or the wait mode, external clock inputs TIM2 and TIM3 cannot be used.

Timer 4
interrupt request

Timer 5
interrupt request

Timer 6
interrupt request

Fig. 13. Timer Block Diagram

22

MITSUBISHI MICROCOMPUTERS

M37274MA-XXXSP

PRELIMINARY

Notice: This is not a final specification.

Some paramentic limits are subject to change.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER

SERIAL I/O

The M37274MA-XXXSP has a built-in serial I/O which can either trans­mit or receive 8-bit data serially in the clock synchronous mode.
The serial I/O block diagram is shown in Figure 14. The synchronous
clock I/O pin (S
P4, data input pin (S
Bit 2 of the serial I/O mode register (address 0213
the synchronous clock is supplied internally or externally (from the
P4

6/SCLK pin). When an internal clock is selected, bits 1 and 0 select

whether f(X
and P46/SCLK pins for serial I/O, set the corresponding bits of the
port P4 direction register (address 00C9
serial I/O, set the corresponding bit of the port P1 direction register
(address 00C3

CLK), and data output pin (SOUT) also function as port

IN) also functions as port P1.

16) selects whether

IN) or f(XCIN) is divided by 8, 16, 32, or 64. To use SOUT

16) to “0.” To use SIN pin for

16) to “0.”

X

CIN

1/2

X

IN

1/2

1/2

CM7

Synchronous

circuit

S

CLK

SM2

S

Serial I/O counter (8)

and ON-SCREEN DISPLAY CONTROLLER

The operation of the serial I/O is described below. The operation of
the serial I/O differs depending on the clock source; external clock or
internal clock.

Data bus

Frequency divider

1/2

1/81/4 1/16

SM1
SM0

Selection gate: Connect to

black side at
reset.

CM : CPU mode register
SM : Serial I/O mode register

Serial I/O
interrupt request

SM5

S

OUT

: LSB

MSB

(Note)

S

IN

Serial I/O shift register (8)

(Address 021416)

8

Note : When the data is set in the serial I/O register (address 021416), the register functions as the serial I/O shift register.

Fig. 14. Serial I/O Block Diagram

23

MITSUBISHI MICROCOMPUTERS

M37274MA-XXXSP

PRELIMINARY

Notice: This is not a final specification.

Some paramentic limits are subject to change.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER

Internal clock : The serial I/O counter is set to “7” during the write
cycle into the serial I/O register (address 0214

16), and the transfer

clock goes “H” forcibly. At each falling edge of the transfer clock after
the write cycle, serial data is output from the S

OUT pin. Transfer di-

rection can be selected by bit 5 of the serial I/O mode register. At
each rising edge of the transfer clock, data is input from the S

IN pin

and data in the serial I/O register is shifted 1 bit.
After the transfer clock has counted 8 times, the serial I/O counter
becomes “0” and the transfer clock stops at HIGH. At this time the
interrupt request bit is set to “1.”
External clock : The an external clock is selected as the clock source,
the interrupt request is set to “1” after the transfer clock has been
counted 8 counts. However, transfer operation does not stop, so the
clock should be controlled externally. Use the external clock of 500kHz
or less with a duty cycle of 50%.
The serial I/O timing is shown in Figure 15. When using an external
clock for transfer, the external clock must be held at HIGH for initial­izing the serial I/O counter. When switching between an internal clock
and an external clock, do not switch during transfer. Also, be sure to
initialize the serial I/O counter after switching.

Notes 1: On programming, note that the serial I/O counter is set by

writing to the serial I/O register with the bit managing in­structions, such as SEB and CLB.

2: When an external clock is used as the synchronous clock,

write transmit data to the serial I/O register when the trans­fer clock input level is HIGH.

and ON-SCREEN DISPLAY CONTROLLER

7
0

0

0

Serial I/O mode register
(SM : address 0213

16

Internal synchronous clock
selection bits
b1 b0

IN

0 0 : f(X
0 1 : f(X
1 0 : f(X
1 1 : f(X

)/8 or f(X

IN

)/16 or f(X

IN

)/32 or f(X

IN

)/64 or f(X

Synchronous clock selection bit

0 : External clock
1 : Internal clock

Port function selection bit

0 : P1

1

, P13 functions as port

1 : SCL1, SDA1

Port function selection bit

0 : P1

2

, P14 functions as port

1 : SCL2, SDA2

Transfer direction selection bit

0 : LSB first
1 : MSB first

Fix these bits to “0”

CIN

)

)/8

CIN

)/16

CIN

)/32

CIN

)/64

Synchronous clock

Transfer clock

Serial I/O register
write signal

Serial I/O output

S

OUT

Serial I/O input

S

IN

Note : When an internal clock is selected, the S

Fig. 15. Serial I/O Timing (for LSB first)

Fig. 16. Serial I/O Mode Register

D

0

D

1

D

2

D

3

D

4

D

OUT

pin is at high-impedance after transfer is completed.

(Note)

5

D

6

D

7

Interrupt request bit is set to “1”

24

MITSUBISHI MICROCOMPUTERS

M37274MA-XXXSP

PRELIMINARY

Notice: This is not a final specification.

Some paramentic limits are subject to change.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER

PWM OUTPUT FUNCTION

The M37274MA-XXXSP is equipped with a 14-bit PWM (DA) seven
8-bit PWMs (PWM0–PWM6). DA has a 14-bit resolution with the
minimum resolution bit width of 0.25
4096 ms (for f(X
structure and an 8-bit resolution with minimum resolution bit width of
4

µ

s and repeat period of 1024 µs (for f(XIN) = 8 MHz) .
Figure 17 shows the PWM block diagram. The PWM timing generat­ing circuit applies individual control signals to PWM0–PWM6 using

IN) divided by 2 as a reference signal.

f(X

IN) = 8 MHz). PWM0–PWM6 have the same circuit

µ

s and a repeat period of

(1) Data Setting

When outputting DA, first set the high-order 8 bits to the DA-H regis­ter (address 0240
(address 0241
data to the PWMi register (i means 0 to 6; addresses 0200
0206

16).

16), then the low-order 6 bits to the DA-L register

16). When outputting PWM0–PWM6, set 8-bit output
16 to

(2) Transmitting Data from Register to PWM circuit

Data transfer from the 8-bit PWM register to the 8-bit PWM circuit is
executed at writing data to the register.
The signal output from the 8-bit PWM output pin corresponds to the
contents of this register.
Also, data transfer from the DA register (addresses 0240
0241

16) to the 14-bit PWM circuit is executed at writing data to the

DA-L register (address 0241
dress 0240
possible to confirm the data being output from the D-A output pin by
reading the DA register.

16) means reading this transferred data. Accordingly, it is

16). Reading from the DA-H register (ad-

16 and

(3) Operating of 8-bit PWM

The following explains PWM operation.
First, set the bit 0 of PWM mode register 1 (address 020A
(at reset, bit 0 is already set to “0” automatically), so that the PWM
count source is supplied.
PWM0–PWM3 are also used as pins P0
also used as pins P0
of the port P0 direction register to “1” (output mode). And select each
output polarity by bit 3 of PWM mode register 1 (address 020A
Then, set bits 7 to 0 of PWM mode register 2 to “1” (PWM output).
The PWM waveform is output from the PWM output pins by setting
these registers.
Figure 18 shows the 8-bit PWM timing. One cycle (T) is composed

8

of 256 (2
each bit (bits 0 to 7), are output inside the circuit during 1 cycle.
Refer to Figure 20 (a). The 8-bit PWM outputs waveform which is
the logical sum (OR) of pulses corresponding to the contents of bits
0 to 7 of the 8-bit PWM register. Several examples are shown in
Figure 20 (b). 256 kinds of output (HIGH area: 0/256 to 255/256) are
selected by changing the contents of the PWM register. A length of
entirely HIGH cannot be output, i.e. 256/256.

) segments. The 8 kinds of pulses, relative to the weight of

0–P02, respectively. Set the corresponding bits

4–P07, PWM4–PWM6 are

16) to “0”

16).

and ON-SCREEN DISPLAY CONTROLLER

(4) Operating of 14-bit PWM

As with 8-bit PWM, set the bit 0 of the PWM mode register 1 (ad­dress 020A
cally), so that the PWM count source is supplied. Pin DA is also used
as port P0
tion register. Next, select the output polarity by bit 3 of the PWM
mode register 1. Then, the 14-bit PWM outputs from the D-A output
pin by setting bit 1 of the PWM mode register 1 to “0” (at reset, this bit
already set to “0” automatically) to select the DA output.
The output example of the 14-bit PWM is shown in Figure 19.
The 14-bit PWM divides the data of the DA latch into the low-order 6
bits and the high-order 8 bits.
The fundamental waveform is determined with the high-order 8-bit
data “D
fundamental waveform) is output every short area of “t” = 256τ =
64 ms (τ is the minimum resolution bit width of 0.25
area increase interval (t
“D
longer by τ than that of other smaller intervals in PWM repeat period
“T” = 64t. Thus, a rectangular waveform with the different “H” width is
output from the D-A pin. Accordingly, the PWM output changes by τ
unit pulse width by changing the contents of the DA-H and DA-L
registers. A length of entirely “H” output cannot be output, i. e. 256/

256.

16) to “0” (at reset, bit 0 is already set to “0” automati-

3. Select output mode by setting bit 3 of the port P0 direc-

H.” A “H” level area with a length τ ✕ DH(“H” level area of

µ

s). The “H” level

m) is determined with the low-order 6-bit data

L.” The “H” level are of smaller intervals “tm” shown in Table 6 is

(5) Output after Reset

At reset, the output of ports P00–P02 and P04–P07 is in the high­impedance state and the contents of the PWM register and the PWM
circuit are undefined. Note that after reset, the PWM output is unde­fined until setting the PWM register.

25

MITSUBISHI MICROCOMPUTERS

M37274MA-XXXSP

PRELIMINARY

Notice: This is not a final specification.

Some paramentic limits are subject to change.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER

Table 2. Relation Between Low-order 6-bit Data and High-level

Area Increase Interval

Low-order 6 bits of Data

0 0 0 0 0 0
0 0 0 0 0 1

0 0 0 0 1 0
0 0 0 1 0 0
0 0 1 0 0 0
0 1 0 0 0 0
1 0 0 0 0 0

Area Longer by τ Than That of Other tm (m = 0 to 63)

LSB

Nothing
m = 32
m = 16, 48
m = 8, 24, 40, 56
m = 4, 12, 20, 28, 36, 44, 52, 60

2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62

m =

m = 1, 3, 5, 7, ................................. 57, 59, 61, 63

Data bus

DA-H register

(Address : 0240

b7 b0

DA latch
(14 bits)

MSB

8

1/2XIN

PN0

PWM0 register
(Address 0200

b7 b0

16

16

)

6

14-bit PWM circuit

)

14

PWM timing

generating

circuit

and ON-SCREEN DISPLAY CONTROLLER

DA-L register (Note)

(Address : 0241

LSB

6

P0

PN2

3

PN1

16

)

D0

3

D-A

Selection gate

Connected to
black side at
reset.

Inside of

Fig. 17. PWM Block Diagram

8

8-bit PWM circuit

PWM1 register (Address 020116)

PWM2 register (Address 020216)

PWM3 register (Address 020316)

PWM4 register (Address 020416)

PWM5 register (Address 020516)

:

PWM6 register (Address 020616)

is as same contents with the others.

POL

PN

: PWM mode register 1(address 020A16)
: PWM mode register 2(address 020B

PW
P0

: Port P0 register

D0

: Port P0 direction register

P0

PW0

P0

PW1

P0

PW2

P0

PW3

P0

PW4

P0

PW5

P0

PW6

D0

4

4

D0

5

5

D0

6

6

D0

7

7

D0

0

0

D0

1

1

D0

2

2

(

address 00C0

(

PWM0

PWM1

PWM2

PWM3

PWM4

PWM5

PWM6

16

16

)

address 00C1

)

16

)

26

MITSUBISHI MICROCOMPUTERS

5

M37274MA-XXXSP

PRELIMINARY

Notice: This is not a final specification.

Some paramentic limits are subject to change.

25

254

252

250

250

246

244

242

240

238

236

234
230

230

220

210

200

190

180

170

160

150

140

130

120

110

100

90

80

70

60

50

40

30

20

9
7
5
3
1

228

226
222

220

218
214

212

210
206

204

202
198

196

194
190

188

186
182

180

178
174

172

170
166

164

162
158

156

154
150

148

146
142
138
134

132 140

130
126

124

122
118

116

114
110

108

106
102

100

98
94

92

90
86

84

82
78

76

74
70

68

66
62

60

58
54

52

50
46

44

42
38

36

34
30

28

26
22

20

18
14

12

10
6

4

2

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER

and ON-SCREEN DISPLAY CONTROLLER

248

240

232

224

216

208

200

192

184

176

168

160

152

144

136

128

120

112

104

96

88

80

72

64

56

48

40

32

24

16

8

(a) Pulses showing the weight of each bit

t

T = 256 t

t = 4 µs T = 1024 µs

PWM output

) = 8 MHz

IN

f(X

(b) Example of 8-bit PWM

Bit 7

Fig. 18. 8-bit PWM Timing

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(0)

16

00

(1)

16

01

(24)

16

18

(255)

16

FF

27

MITSUBISHI MICROCOMPUTERS

M37274MA-XXXSP

PRELIMINARY

Notice: This is not a final specification.

Some paramentic limits are subject to change.

Set “2C

16

” to DA-H register.

b7 b0b6 b5 b4 b3 b2 b1

[DA-H
register]

0

“H” level area of
fundamental waveform

Fundamental

waveform

14-bit
PWM output

8-bit
counter

2C 2B 2A … 03 02 01 00 2C 2B 2A … 03 02 01 00

FF 00D3FE FD…D6 D4 02 01D5

At writing of DA-L

[DA latch]

These bits decide “H” level area of
fundamental waveform.

Minimum
resolution bit

=

width 0.25

0.25

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER

H

D

0010110

b13 b6

0010110

High-order 8-bit

✕

value of DA latch

s

s

✕44

…

and ON-SCREEN DISPLAY CONTROLLER

16

” to DA-L register.

Set “28

b7

[DA-L register]

Undefined

At writing of DA-L

b0b5

101000

0

These bits decide smaller interval “tm” in which “H” leval
area is [“H” level area of fundamental waveform + τ ].

Waveform of smaller interval “tm” specified by low-order 6 bits

s

✕45

0.25

14-bit
PWM output

8-bit
counter

FF 00D3FE FD D6 D4 02 01D5

…

…

0.25

b0b6 b5 b4 b3 b2 b1

D

L

010100

s

Fundamental waveform of smaller interval
“tm” which is not specified by low-order 6
bits is not changed.

0.25s✕44 τ = 0.25

14-bit PWM output

t0t1t2t

Low-order 6-bit output
of DA latch

Fig. 19. 14-bit PWM Output Example (f(XIN) = 8MHz)

3t4t5

s

Repeat period

T = 4096

t

59t60t61t62t63

s

28

MITSUBISHI MICROCOMPUTERS

M37274MA-XXXSP

PRELIMINARY

Notice: This is not a final specification.

Some paramentic limits are subject to change.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER

and ON-SCREEN DISPLAY CONTROLLER

07

PWM mode register 1

16

(PN: address 020A

)

PWM count source selection bit
0 : Count source supply
1 : Count source stop

3

output selection bit

DA/P0
0 : P0

3

output

1 : DA output

DA output polarity selection bit
0 : Positive polarity
1 : Negative polarity

PWM output polarity selection bit
0 : Positive polarity
1 : Negative polarity

0

PWM mode register 2
(PW: address 020B

P04/PWM0 output selection bit
0 : P0

4

output

1 : PWM0 output

5

/PWM1 output selection bit

P0

5

output

0 : P0
1 : PWM1 output

P0

6

/PWM2 output selection bit

6

output

0 : P0
1 : PWM2 output

P0

7

/PWM3 output selection bit

7

output

0 : P0
1 : PWM3 output

P0

0

/PWM4 output selection bit

0

output

0 : P0
1 : PWM4 output

16

)

Fig. 20. PWM-related Registers

1

/PWM5 output selection bit

P0

1

output

0 : P0
1 : PWM5 output

P0

2

/PWM6 output selection bit

2

output

0 : P0
1 : PWM6 output

Fix this bit to “0.”

29

MITSUBISHI MICROCOMPUTERS

M37274MA-XXXSP

PRELIMINARY

Notice: This is not a final specification.

Some paramentic limits are subject to change.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER

A-D CONVERTER
(1)A-D Conversion Register (AD)

A-D conversion reigister is a read-only register that stores the result
of an A-D conversion. This register should not be read during A-D
conversion.

(2)A-D Control Register (ADCON)

The A-D control register controls A-D conversion. Bits 1 and 0 of this
register select analog input pins. When these pins are not used as
anlog input pins, they are used as ordinary I/O pins. Bit 3 is the A-D
conversion completion bit, A-D conversion is started by writing “0” to
this bit. The value of this bit remains at “0” during an A-D conversion,
then changes to “1” when the A-D conversion is completed.
Bit 4 controls connection between the resistor ladder and V

CC. When

not using the A-D converter, the resistor ladder can be cut off from
the internal V

CC by setting this bit to “0,” accordingly providing low-

power dissipation.

(3)Comparison Voltage Generator (Resistor

Ladder)

The voltage generator divides the voltage between VSS and VCC by
256, and outputs the divided voltages to the comparator as the refer­ence voltage V

ref.

(4)Channel Selector

The channel selector connects an analog input pin, selected by bits
1 and 0 of the A-D control register, to the comparator.

and ON-SCREEN DISPLAY CONTROLLER

(5)Comparator and Control Circuit

The conversion result of the analog input voltage and the reference
voltage “V
version completion bit and A-D conversion interrupt request bit are
set to “1” at the completion of A-D conversion.

Fig. 21. A-D Control Register

ref” is stored in the A-D conversion register. The A-D con-

7
0

0

A-D control register
(ADCON: address 00EF

Analog input pin selection bits

b2 b1 b0

0 : AD1

0 0
0 0 1 : AD2
0 1 0 : AD3
0 1 1 : AD4

0 : AD5

1 0
1 0 1 : AD6

1 1 0 :
1 1 1 :

A-D conversion completion bit
0 : Conversion in purogress
1 : Conversion completed

VCC connection selection bit

0 : OFF
1 : ON
Fix this bit to “0.”

Do not set.

16

)

A-D control register

(address 00EF

AD1
AD2
AD3
AD4

AD5
AD6

Channel selector

Fig. 22. A-D Comparator Block Diagram

30

Data bus

b7 b0

16

)

2

A-D control circuit

Compa­rator

A-D conversion register

8

(address 00EE16)

Switch tree

Resistor ladder

VSSV

CC

A-D conversion
interrupt request