Mitsubishi M37274EFSP Datasheet
MITSUBISHI MICROCOMPUTERS
M37274EFSP
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
DESCRIPTION
The M3727EFSP is a single-chip microcomputer designed with CMOS
silicon gate technology. It is housed in a 52-pin shrink plastic molded
DIP.
In addition to their simple instruction sets, the ROM, RAM and I/O
addresses are placed on the same memory map to enable easy programming.
The M3727EFSP has a OSD function and a data slicer function, so it
is useful for a channel selection system for TV with a closed caption
decoder.
FEATURES
Number of basic instructions..................................................... 71
•
Memory size
•
Minimum instruction execution time
•
......................................... 0.5 µs (at 8 MHz oscillation frequency)
Power source voltage...................................................5 V ± 10 %
•
Subroutine nesting .............................................128 levels (Max.)
•
Interrupts ....................................................... 18 types, 16 vectors
•
8-bit timers .................................................................................. 6
•
Programmable I/O ports (Ports P0, P1, P2, P30, P31).............. 26
•
Input ports (Ports P40–P46, P63, P64, P70–P72) ...................... 12
•
Output ports (Ports P52–P55)...................................................... 4
•
12 V withstand ports.................................................................... 7
•
LED drive ports ........................................................................... 2
•
Serial I/O ............................................................8-bit ✕ 1 channel
•
Multi-master I2C-BUS interface................................1 (2 systems)
•
A-D converter (8-bit resolution) .................................... 6 channels
•
PWM output circuit ......................................... 14-bit ✕ 1, 8-bit ✕ 7
•
Power dissipation
•
In high-speed mode .......................................................... 165mW
(at VCC = 5.5V, 8MHz oscillation frequency, CRT on, and Data
slicer on)
In low-speed mode...........................................................0.33mW
(at VCC = 5.5V, 32kHz oscillation frequency)
Data slicer
•
ROM correction function
•
ROM ....................................................... 60 K bytes
RAM ........................................................1024 bytes
ROM correction memory.............................64 bytes
ROM for OSD .......................................11072 bytes
RAM for OSD ..........................................1920 bytes
and ON-SCREEN DISPLAY CONTROLLER
OSD function
•
Display characters............................... 40 characters ✕ 16 lines
Kinds of characters ..................................................... 256 kinds
(In EXOSD mode, they can be combined with 16 kinds of extra
fonts)
Character display area ........................ CC mode : 16 ✕ 26 dots
OSD mode : 16 ✕ 20 dots
EXOSD mode : 16 ✕ 26 dots
Kinds of character sizes ............................... CC mode : 2 types
OSD mode : 14 types
EXOSD mode : 6 types
Kinds of character background colors
CC mode : 7 kinds (a character unit)
OSD mode : 7 kinds (a character unit)
EXOSD mode : 5 kinds (a character unit)
It can be specified by a screen unit (maximum 7 kinds).
Extra font coloring, raster coloring, border coloring
Kinds of character colors............... CC mode : 7 kinds (R, G, B)
OSD mode : 7 kinds (R, G, B)
EXOSD mode : 5 kinds (R, G, B)
Display position
Horizontal ................................................................ 256 levels
Vertical .................................................................. 1024 levels
Attribute ......................CC mode : smooth italic, underline, flash
OSD mode : border
EXOSD mode : border,
extra font (16 kinds)
Automatic solid space function
Window function
Dual layer OSD function
APPLICATION
TV with a closed caption decoder
MITSUBISHI MICROCOMPUTERS
M37274EFSP
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
PIN CONFIGURATION (TOP VIEW)
H
V
P40/AD4
P4
1
/INT2
P4
2
/TIM2
P4
3
/TIM3
P2
4
/AD3
P2
5
/AD2
P26/AD1
P2
7
/AD5
P0
0
/PWM4
P0
1
/PWM5
P0
2
/PWM6
P1
P44/INT1
P4
5/SOUT
6/SCLK
P4
AV
HLF/AD6
P72/RVCO
P71/V
P70/CV
CNV
X
SYNC
SYNC
7/SIN
CC
HOLD
SS
X
OUT
V
SS
and ON-SCREEN DISPLAY CONTROLLER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
IN
23
IN
24
25
26
M37274EFSP
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
P52/R
P5
3
/G
4
/B
P5
P5
5
/OUT1
P0
4
/PWM0
P0
5
/PWM1
P06/PWM2
P07/PWM3
P2
0
P2
1
P2
2
P2
3
P1
0
/OUT2
1
/SCL1
P1
2
/SCL2
P1
P1
3
/SDA1
P1
4
/SDA2
5
P1
P16/INT3
P03/DA
0
P3
P31
RESET
P6
4
/OSC2/X
P63/OSC1/X
V
CC
COUT
CIN
Outline 52P4B
2
MITSUBISHI MICROCOMPUTERS
M37274EFSP
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
3, P64
29
Clock output for OSD/
sub-clock output
OSC2
28
OSC1
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
Input ports P6
sub-clock input
P6 (2)
Clock input for OSD/
A-D converter
19
HLF
20
RVCO
21
22
23
26
Data slicer
P7 (3)
selection circuit
Timer count source
TIM2
TIM3
T1 (8)
Timer 1
ROM
T2 (8)
Timer 2
T3 (8)
Timer 3
VHOLD
Pins for data slicer
Input ports P70–P72
CVIN
CNVSS
VSS
60 K bytes
27
VCC
CC
18
AV
30
RESET
Reset input
counter
Program
counter
Progam
PCL (8)
PCH (8)
Data bus
RAM
1024 bytes
25
Clock output
XOUT
IN
X
24
Clock
circuit
generating
Address bus
Clock input
FUNCTIONAL BLOCK DIAGRAM of M37274EFSP
ROM
correction
Instruction
Control signal
T4 (8)
Timer 4
Timer 5
Stack
pointer
Index
register
Index
register
status
Processor
A (8)
Accumulator
8-bit
arithmetic
and ON-SCREEN DISPLAY CONTROLLER
SYNC
H
1
VSYNC
2
P5 (4)
P4 (7)
SOUT
SCLK
SIN
P0 (8)
P2 (8)
P1 (8)
P3 (2)
R
G
B
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
SCL1
SCL2
SDA1
SDA2
OUT1
52
51
50
49
3
4
5
6
15
16
17
11
12
13
33
48
47
46
45
44
43
42
41
7
8
9
10
40
39
38
37
36
35
34
14
31
32
function
decoder
T5 (8)
S (8)
Y (8)
X (8)
PS (8)
register
and
logical unit
CRT circuit
Instruction
register (8)
T6 (8)
Timer 6
8-bit
PWM circuit
INT2
INT1
SI/O (8)
14bit
PWM
A-D
converter
INT3
OUT2
Multi-master
C-BUS interface
2
I
Sync
signal input
Output port P5
0–P46
Input ports P4
I/O port P0
I/O port P2
I/O port P1
0, P31
I/O ports
P3
3
MITSUBISHI MICROCOMPUTERS
M37274EFSP
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
FUNCTIONS
Number of basic instructions
Instruction execution time
Clock frequency
Memory size
Input/Output ports
Serial I/O
Multi-master I2C-BUS interface
A-D converter
PWM output circuit
Timers
Subroutine nesting
Interrupt
Clock generating circuit
Data slicer
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
Parameter
ROM
RAM
ROM correction memory
OSD ROM
OSD RAM
P00–P02,
P04–P07
P03
P10, P15–P17
P11–P14
P2
P30, P31
P40–P44
P45, P46
P52–P55
P63
P64
P70–P72
I/O
I/O
I/O
I/O
I/O
I/O
Input
Input
Output
Input
Input
Input
and ON-SCREEN DISPLAY CONTROLLER
Functions
71
0.5 µs (the minimum instruction execution time, at 8 MHz oscillation frequency)
8 MHz (maximum)
60 K bytes
1024 bytes
64 bytes
11072 bytes
1920 bytes
7-bit ✕ 1 (N-channel open-drain output structure, can be used as 8-bit
PWM output pins)
1-bit ✕ 1
(CMOS input/output structure, can be used as 14-bit PWM output pin)
4-bit ✕ 1 (CMOS input/output structure, can be used as OSD output pin,
INT input pin, serial input pin)
4-bit ✕ 1 (N-channel open-drain output structure, can be used as multi-
master I2C-BUS interface)
8-bit ✕ 1 (CMOS input/output structure, can be used as A-D input pins)
2-bit ✕ 1 (CMOS input/output structure)
5-bit ✕ 1 (can be used as A-D input pins, INT input pins, external clock
input pins)
2-bit ✕ 1 (N-channel open-drain output structure when serial I/O is used,
can be used as serial I/O pins)
4-bit ✕ 1 (CMOS output structure, can be used as OSD output)
1-bit ✕ 1 (can be used as sub-clock input pin, OSD clock input pin)
1-bit ✕ 1 (CMOS output structure when LC is oscillating, can be used as
sub-clock output pin, OSD clock output pin)
3-bit ✕ 1 (can be used as data slicer input/output)
8-bit ✕ 1
1
6 channels (8-bit resolution)
14-bit ✕ 1, 8-bit ✕ 7
8-bit timer ✕ 6
128 levels (maximum)
External interrupt ✕ 3, Internal timer interrupt ✕ 6, Serial I/O interrupt ✕ 1,
OSD interrupt ✕ 1, Multi-master I2C-BUS interface interrupt ✕ 1,
Data slicer interrupt ✕ 1, f(XIN)/4092 interrupt ✕ 1, VSYNC interrupt ✕ 1, AD conversion interrupt ✕ 1, BRK instruction interrupt ✕ 1
2 built-in circuits (externally connected to a ceramic resonator or a quartzcrystal oscillator)
Built in
4
MITSUBISHI MICROCOMPUTERS
M37274EFSP
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
FUNCTIONS (continued)
Parameter
OSD function
Power source voltage
Power dissipation
Operating temperature range
Device structure
Package
In high-speed
mode
In low-speed
mode
In stop mode
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
Number of display characters
Character display area
Kinds of characters
Kinds of character sizes
Kinds of character colors
Display position (horizontal, vertical)
OSD ON
OSD OFF
OSD OFF
Data slicer ON
Data slicer OFF
Data slicer OFF
40 characters ✕ 16 lines
CC mode: 16 ✕ 26 dots (dot structure: 16 ✕ 20 dots)
OSD mode: 16 ✕ 20 dots
EXOSD mode: 16 ✕ 26 dots
256 kinds
(In EXOSDmode, they can be combined with 16 kinds of extra fonts)
CC mode: 2 kinds
OSD mode: 14 kinds
EXOSD mode: 6 kinds
CC mode: 7 kinds (R, G, B)
OSD mode: 7 kinds (R, G, B)
EXOSD mode: 5 kinds (R, G, B)
256 levels (horizontal) ✕ 1024 levels (vertical)
5 V ± 10 %
165 mW typ. (at oscillation frequency f(X
82.5 mW typ. (at oscillation frequency f(X
0.33mW typ. (at oscillation frequency f(X
0.055 mW (maximum)
–10 °C to 70 °C
CMOS silicon gate process
52-pin shrink plastic molded DIP
and ON-SCREEN DISPLAY CONTROLLER
Functions
IN) = 8 MHz, fOSC = 13 MHz)
IN) = 8 MHz)
CIN) = 32 kHz, f(XIN) = stopped)
5
MITSUBISHI MICROCOMPUTERS
M37274EFSP
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
PIN DESCRIPTION
Pin Name Functions
VCC,
AVCC,
VSS
CNVSS
_____
RESET
XIN
XOUT
P00/PWM4–
P02/PWM6,
P03/DA,
P04/PWM0–
P07/PWM3
P10/OUT2,
P11/SCL1,
P12/SCL2,
P13/SDA1,
P14/SDA2,
P15,
P16/INT3,
P17/SIN
P20–P23
P24/AD3–
P26/AD1,
P27/AD5
P30, P31
P40/AD4,
P41/INT2,
P42/TIM2,
P43/TIM3,
P44/INT1,
P45/SOUT,
P46/SCLK
P52/R,P53/G,
P54/B,
P55/OUT1
Power source
CNVSS
Reset input
Clock input
Clock output
I/O port P0
DA output
8-bit PWM output
I/O port P1
OSD output
Multi-master
I2C-BUS interface
External interrupt
input
Serial I/O data
input
I/O port P2
Analog input
I/O port P3
Input port P4
Analog input
External interrupt
input
External clock input
Serial I/O data
output
Serial I/O
synchronous clock
input/output
Output port P5
OSD output
Input/
Output
Input
Input
Output
I/O
Output
Output
I/O
Output
Output
Input
Input
I/O
Input
I/O
Input
Input
Input
Input
Output
I/O
Output
Output
Apply voltage of 5 V ± 10 % (typical) to VCC and AVCC, and 0 V to VSS.
Connected to VSS.
To enter the reset state, the reset input pin must be kept at a “L” for 2 µs or more (under
normal VCC conditions).
If more time is needed for the quartz-crystal oscillator to stabilize, this “L” condition should
be maintained for the required time.
This chip has an internal clock generating circuit. To control generating frequency, an
external ceramic resonator or a quartz-crystal oscillator is connected between pins XIN and
XOUT. If an external clock is used, the clock source should be connected to the XIN pin and
the XOUT pin should be left open.
Port P0 is an 8-bit I/O port with direction register allowing each I/O bit to be individually
programmed as input or output. At reset, this port is set to input mode. The output structure
of P03 is CMOS output, that of P00–P02 and P04–P07 are N-channel open-drain output.
See notes at end of Table for full details of port P0 functions.
Pin P03 is also used as 14-bit PWM output pin DA. The output structure is CMOS output.
Pins P00–P02 and P04–P07 are also used as PWM output pins PWM4–PWM6 and PWM0–
PWM3 respectively. The output structure is N-channel open-drain output.
Port P1 is an 8-bit I/O port and has basically the same functions as port P0. The output
structure of P10 and P15–P17 is CMOS output, that of P11–P14 is N-channel open-drain
output.
Pin P10 is also used as OSD output pin OUT2. The output structure is CMOS output.
Pin P11 is used as SCL1, SCL2, SDA1 and SDA2 respectively, when multi-master I2C-
BUS interface is used. The output structure is N-channel open-drain output.
Pin P16 is also used as external interrupt input pin INT3.
Pin P17 is also used as serial I/O data input pin SIN.
Port P2 is an 8-bit I/O port and has basically the same functions as port P0. The output
structure is CMOS output.
Pins P24–P26, P27 are also used as analog input pins AD3–AD1, AD5 respectively.
Ports P30 and P31 are 2-bit I/O ports and have basically the same functions as port P0.
The output structure is CMOS output.
Ports P40–P46 are a 7-bit input port.
Pin P40 is also used as analog input pin AD4.
Pins P41, P44 are also used as external interrupt input pins INT2, INT1.
Pins P42 and P43 are also used as external clock input pins TIM2, TIM3 respectively.
Pin P45 is used as serial I/O data output pin SOUT. The output structure is N-channel open-
drain output.
Pin P46 is used as serial I/O synchronous clock input/output pin SCLK. The output structure
is N-channel open-drain output.
Ports P52–P55 are 4-bit output ports. The output structure is CMOS output.
Pins P52–P55 are also used as OSD output pins R, G, B, OUT1 respectively.
and ON-SCREEN DISPLAY CONTROLLER
6
MITSUBISHI MICROCOMPUTERS
M37274EFSP
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
PIN DESCRIPTION (continued)
Pin Name Functions
P63/OSC1/
XCIN,
P64/OSC2/
XCOUT
P70/CVIN,
P71/VHOLD,
P72/RVCO
HLF/AD6
HSYNC
VSYNC
Note : As shown in the memory map (Figure 5), port P0 is accessed as a memory at address 00C016 of zero page. Port P0 has the port P0
Input port
Clock input for OSD
Clock output for OSD
Sub-clock output
Sub-clock input
Input port P7
Input for data slicer
Input/output for
data slicer
Analog input
HSYNC input
VSYNC input
direction register (address 00C116 of zero page) which can be used to program each bit as an input (“0”) or an output (“1”). The pins
programmed as “1” in the direction register are output pins. When pins are programmed as “0,” they are input pins. When pins are
programmed as output pins, the output data are written into the port latch and then output. When data is read from the output pins, the
output pin level is not read but the data of the port latch is read. This allows a previously-output value to be read correctly even if the
output “L” voltage has risen, for example, because a light emitting diode was directly driven. The input pins float, so the values of the pins
can be read. When data is written into the input pin, it is written only into the port latch, while the pin remains in the floating state.
Input/
Output
Input
Input
Output
Output
Input
Input
Input
I/O
Input
Input
Input
Ports P63 and P64 are 2-bit input port.
Pin P63 is also used as OSD clock input pin OSC1.
Pin P64 is also used as OSD clock output pin OSC2. The output structure is CMOS output.
Pin P64 is also used as sub-clock output pin XCOUT. The output structure is CMOS output.
Pin P63 is also used as sub-clock input pin XCIN.
Ports P70–P72 are 3-bit input port.
Pins P70, P71 are also used as data slicer input pins CVIN, VHOLD respectively. When
using data slicer, input composite video signal through a capacitor. Connect a capacitor
between VHOLD and VSS.
Pins P72 pin is also used as input/output pin for data slicer RVCO. When using data slicer,
connect a resistor between RVCO and VSS.
When using data slicer, connect a filter using of a capacitor and a resistor between HLF
and VSS.
This is an analog input pin AD6.
This is a horizontal synchronous signal input for OSD.
This is a vertical synchronous signal input for OSD.
7
MITSUBISHI MICROCOMPUTERS
M37274EFSP
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
3
Ports P0
Ports P0
, P10, P15–P17, P2, P30, P3
Data bus
0
–P02, P04–P0
7
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
1
Direction register
CMOS output
Port latch
Direction register
Ports P03, P10, P15–P17,
P2, P30, P31
Note :Each port is also used as follows :
P03/DA
P10 : OUT2
P16 : INT3
P17 : SIN
P24–P26 : AD3–AD1
P27 : AD5
N-channel open-drain output
Ports P00–P02, P04–P07
Data bus
Ports P11–P1
4
Data bus
Fig. 1. I/O Pin Block Diagram (1)
Port latch
Direction register
Port latch
Note :Each port is also used as follows :
P00–P02 : PWM4–PWM6
P04–P07 : PWM0–PWM3
N-channel open-drain output
Port P11-P14
Note :Each port is also used as follows :
P11 : SCL1
P12 : SCL2
P13 : SDA1
P14 : SDA2
8
MITSUBISHI MICROCOMPUTERS
M37274EFSP
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
S
OUT
, S
CLK
Direction register
Data bus
H
SYNC
, V
SYNC
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
N-channel open-drain output
Ports P45, P46
Note : Each pin is also used
as follows :
P45 : SOUT
P46 : SCLK
P52–P5
5
Schmidt input
CMOS output
Internal circuit
0
–P4
Ports P4
4
Data bus
Fig. 2. I/O Pin Block Diagram (2)
HSYNC, VSYNC
Internal circuit
Input
Ports P40–P44
Note : Each port is also used as below :
P40 : AD4
P41 : INT2
P42 : TIM2
P43 : TIM3
P44 : INT1
P52–P55
Note : Each port is also used
as follows :
P52 : R P54 : B
P53 : G P55 : OUT1
9
MITSUBISHI MICROCOMPUTERS
M37274EFSP
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)
The M37274EFSP uses the standard 740 Family instruction set. Refer
to the table of 740 Family addressing modes and machine instructions or the SERIES 740 <Software> User’s Manual for details on
the instruction set.
Machine-resident 740 Family instructions are as follows:
The FST, SLW instruction cannot be used.
The MUL, DIV, WIT and STP instructions can be used.
CPU Mode Register
b7b6 b5b4b3 b2b1b0
100
1
CPU mode register (CPUM) (CM) [Address FB16]
B
Processor mode bits
0, 1
Name Functions
(CM0, CM1)
and ON-SCREEN DISPLAY CONTROLLER
CPU Mode Register
The CPU mode register contains the stack page selection bit and
internal system clock selection bit. The CPU mode register is allocated at address 00FB16.
After reset
b1 b0
0 0: Single-chip mode
0 1:
1 0: Not available
1 1:
RW
RW
0
Fig. 3. CPU Mode Register
Stack page selection
2
bit (CM2) (See note)
3, 4
Fix these bits to “1.”
X
COUT
5
drivability
selection bit (CM5)
Main Clock (X
6
stop bit
(CM6)
Internal system clock
7
selection bit
(CM7)
IN–XOUT
0: 0 page
1: 1 page
0: LOW drive
1: HIGH drive
)
0: Oscillating
1: Stopped
0: X
IN–XOUT
(high-speed mode)
1: X
CIN–XCOUT
selected
selected
(high-speed mode)
Note: This bit is set to “1” after the reset release.
RW
1
RW
1
1
RW
RW
0
RW
0
10
MITSUBISHI MICROCOMPUTERS
M37274EFSP
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
MEMORY
Special Function Register (SFR) Area
The special function register (SFR) area in the zero page contains
control registers such as I/O ports and timers.
RAM
RAM is used for data storage and for stack area of subroutine calls
and interrupts.
ROM
ROM is used for storing user programs as well as the interrupt vector
area.
RAM for OSD
RAM for display is used for specifying the character codes and colors to display.
ROM for OSD
ROM for display is used for storing character data.
and ON-SCREEN DISPLAY CONTROLLER
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
Zero Page
The 256 bytes from addresses 000016 to 00FF16 are called the zero
page area. The internal RAM and the special function registers (SFR)
are allocated to this area.
The zero page addressing mode can be used to specify memory and
register addresses in the zero page area. Access to this area with
only 2 bytes is possible in the zero page addressing mode.
Special Page
The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to
specify memory addresses in the special page area. Access to this
area with only 2 bytes is possible in the special page addressing
mode.
ROM Correction Memory (RAM)
This is used as the program area for ROM correction.
RAM
(1024 bytes)
RAM for OSD (Note)
(1920 bytes)
ROM
(60 K bytes)
0000
00C0
00FF
0100
0200
0248
02C0
02FF
0300
053F
0800
0FF7
1000
FF00
FFDE
FFFF
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
SFR1 area
SFR2 area
16
Interrupt vector area
Not used
Not used
Not used
Zero page
ROM correction memory
Block 1 : addresses 02C0
Block 2 : addresses 02E016 to 02FF
Special page
16
to 02DF
ROM for OSD
(11072 bytes)
10000
16
10800
16
155FF
16
18000
1E41F
1FFFF
16
16
16
16
16
Note : Refer to Table 13. Contents of OSD RAM.
Not used
Not used
Not used
Fig. 4. Memory map
11
MITSUBISHI MICROCOMPUTERS
M37274EFSP
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
■ SFR1 area (addresses C0
<
Address
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
Port P0 (P0)
16
Port P0 direction register (D0)
16
Port P1 (P1)
16
16
Port P1 direction register (D1)
Port P2 (P2)
16
Port P2 direction register (D2)
16
Port P3 (P3)
16
Port P3 direction register (D3)
16
Port P4 (P4)
16
Port P4 direction register (D4)
16
Port P5 (P5)
16
16
OSD port control register (PF)
Port P6 (P6)
16
Port P7 (P7)
16
OSD control register (OC)
16
Horizontal position register (HP)
16
16
Block control register 1 (BC
Block control register 2 (BC
16
Block control register 3 (BC
16
Block control register 4 (BC
16
Block control register 5 (BC
16
Block control register 6 (BC
16
16
Block control register 7 (BC7)
16
Block control register 8 (BC
16
Block control register 9 (BC
Block control register 10 (BC10)
16
Block control register 11 (BC
16
16
Block control register 12 (BC
16
Block control register 13 (BC13)
16
Block control register 14 (BC
16
Block control register 15 (BC15)
Block control register 16 (BC
16
Register
)
1
)
2
)
3
)
4
)
5
)
6
)
8
)
9
)
11
)
12
)
14
)
16
and ON-SCREEN DISPLAY CONTROLLER
16
to DF16)
Bit allocation
:
Function bit
:
Name
:
No function bit
: Fix to this bit to “0”
0
>
State immediately after reset
<
: “0” immediately after reset
0
: “1” immediately after reset
1
: Indeterminate immediately
?
>
after reset
(do not write to “1”)
: Fix to this bit to “1”
1
(do not write to “0”)
Bit allocation State immediately after reset
b7 b0 b7 b0
?
16
00
?
16
00
?
16
00
?
T3SC
P6IM
00
16
?
P45DP46D
0
00
16
?
RGB
0
OUT1OUT2
0
0
00
16
?
00?00??0
OC6OC7 OC4OC5 OC2OC3 OC0OC1
HP6HP7 HP4HP5 HP2HP3 HP0HP1
BC13
BC14
BC15
BC16
BC17
BC
BC
BC
BC
BC
BC
BC
BC
BC
BC
BC
BC
BC107
BC
11
BC
12
BC
14
BC
15
6
7
2
2
6
7
BC
BC
3
3
BC
BC
6
7
4
4
BC
BC
6
7
5
5
BC
BC
6
7
6
6
6
7
BC
BC
7
7
BC
BC
6
7
8
8
BC
BC
6
7
9
9
BC105
BC106
BC
BC
6
7
11
BC
BC
6
7
12
6
7
BC
BC
14
BC
BC
6
7
15
BC165BC167
BC166
4
5
2
2
4
5
BC
BC
3
3
BC
BC
4
5
4
4
BC
BC
4
5
5
5
BC
BC
4
5
6
6
4
5
BC
BC
7
7
BC
BC
4
5
8
8
BC
BC
4
5
9
9
BC103
BC104
BC
BC
4
5
11
5
12
5
14
5
15
11
BC
12
BC
14
BC
15
BC164
11
BC
4
12
4
BC
14
BC
4
15
BC
16
BC11BC12
BC10
BC
BC
BC
BC
BC
BC
BC
BC
BC101BC102
BC
BC
BC
BC141BC142
BC
BC161BC162
1BC22
BC
0
2
2
BC
1BC32
0
3
3
BC
1BC42
0
4
4
1BC52
0
BC
5
5
1BC62
BC
0
6
6
BC
1BC72
0
7
7
BC
1BC82
0
8
8
1BC92
0
BC
9
9
BC
0
10
BC
0
1BC112
11
11
BC
0
1BC122
12
12
BC131BC132BC133BC134BC135BC136BC137
0
13
0
BC
14
BC
0
1BC152
15
15
0
BC
16
3
2
3
3
3
4
3
5
3
6
3
7
3
8
3
9
3
3
3
3
3
00
16
00
16
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
Fig. 5. Memory Map of Special Function Register 1 (SFR1) (1)
12
MITSUBISHI MICROCOMPUTERS
M37274EFSP
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
■ SFR1 area (addresses E016 to FF
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
16
)
<Bit allocation>
:
Function bit
:
Name
: No function bit
: Fix to this bit to “0”
0
State immediately after reset
<
: “0” immediately after reset
0
: “1” immediately after reset
1
: Indeterminate immediately
?
>
after reset
(do not write to “1”)
: Fix to this bit to “1”
1
(do not write to “0”)
Address Register Bit allocation State immediately after reset
b7 b0 b7 b0
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
Caption position register (CP)
16
Start bit position register (SP)
16
16
Window register (WN)
16
Sync slice register (SSL)
Caption data register 1 (CD1)
16
Caption data register 2 (CD2)
16
16
Clock run-in register 1 (CR1)
Clock run-in register 2 (CR2)
16
Clock run-in detect register 1 (CRD1)
16
Clock run-in detect register 2 (CRD2)
16
Data slicer control register 1 (DSC1)
16
Data slicer control register 2 (DSC2)
16
16
Caption data register 3 (CD3)
Caption data register 4 (CD4)
16
A-D conversion register (AD)
16
16
A-D control register (ADCON)
16
Timer 1 (TM1)
Timer 2 (TM2)
16
16
Timer 3 (TM3)
16
Timer 4 (TM4)
16
Timer mode register 1 (TM1)
16
Timer mode register 2 (TM2)
I2C data shift register (S0)
16
16
I2C address register (S0D)
I2C status register (S1)
16
I2C control register (S1D)
16
I2C
clock control register (S2)
16
16
CPU mode register (CPUM)
16
Interrupt request
16
Interrupt request
Interrupt control
16
16
Interrupt control
register 1 (IREQ1)
register 2 (IREQ2)
register 1 (ICON1)
register 2 (ICON2)
100
CP0CP1CP2CP3CP4
SP0SP1SP2SP3SP4SP5SP6SP7
00
SSL7
0101
000 011
0
CR12CR13
100111 1
CRD15CRD17CRD15 CRD15 CRD15
000
000
ADVREF
ADSTR
00
TM15TM16TM17
TM25
TM26TM27
D7 D6
ACK
CM7 CM5CM6
0
D5 D4 D3 D2 D1 D0
10 BIT
BSEL0BSEL1
SAD
ACK
FAST
BIT
MODE
INT2R
IICRT56R
CK0
ADE
IICET56ET56S
1
ADIN2
CM2
1
1MSR
1MSE
WN0WN1WN2WN3WN4WN5
CR11
CR10
CR21
CRD20CRD21CRD22CRD25CRD27CRD25 CRD25 CRD25
DSC10DSC11DSC12DSC15DSC17
DSC20DSC21DSC22DSC25DSC27
ADIN0ADIN1
TM10TM11TM12TM13TM14
TM20TM21TM22TM23TM24
SAD0SAD1SAD2SAD3SAD4SAD5SAD6 RBW
LRBAD0AASALPINBBTRXMST
BC0BC1BC2ES0ALS
CCR0CCR1CCR2CCR3CCR4
0
0
TM1RTM2RTM3RTM4RCRTRVSCRADR
INT1R
DSRSIOR
TM1ETM2ETM3ETM4ECRTEVSCE
INT1EDSESIOEINT2E
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
? 0?00 00 0
?0?00 0? 0
00
16
00
16
?
?0010000
16
FF
07
16
FF
16
07
16
00
16
00
16
?
00
16
000001?0
00
16
00
16
10 0 111 00
00
16
00
16
00
16
00
16
Fig. 6. Memory Map of Special Function Register 1 (SFR2) (2)
13
MITSUBISHI MICROCOMPUTERS
M37274EFSP
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
■ SFR2 area (addresses 200
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
16
to 21F16)
<
Bit allocation>
:
Function bit
:
Name
:
No function bit
: Fix to this bit to “0”
0
<
State immediately after reset
: “0” immediately after reset
0
: “1” immediately after reset
1
: Indeterminate immediately
?
>
after reset
(do not write to “1”)
: Fix to this bit to “1”
1
(do not write to “0”)
Address Register Bit allocation State immediately after reset
b7 b0 b7 b0
200
201
202
203
204
205
206
207
208
209
20A
20B
20C
20D
20E
20F
210
211
212
213
214
215
216
217
218
219
21A
21B
21C
21D
21E
21F
PWM0 register (PWM0)
16
16
PWM1 register (PWM1)
16
PWM2 register (PWM2)
16
PWM3 register (PWM3)
16
PWM4 register (PWM4)
16
PWM5 register (PWM5)
16
PWM6 register (PWM6)
16
Clock run-in detect register 3 (CRD3)
16
16
Clock run-in register (CR3)
16
PWM mode register 1 (PN)
16
PWM mode register 2 (PW)
16
Timer 5 (TM5)
Timer 6 (TM6)
16
16
Sync pulse counter register (SYC)
16
Data slicer control register 3 (DSC3)
16
16
Interrupt input polarity register (IP)
16
Serial I/O mode register (SM)
16
Serial I/O register (SIO)
16
16
16
Clock source control register (CS)
16
I/O polarity control register (PC)
16
Raster color register (RC)
Extra font color register (EC)
16
16
16
Border color register (FC)
16
Window H register 1 (WH1)
16
Window L register 1 (WL1)
Window H register 2 (WH2)
16
Window L register 2 (WL2)
16
CRD34CRD34CRD34
CR36 CR35
0
DSC36 DSC34 DSC33
INT3
INT3
AD/INT3
SEL
0
0
AD/INT3
SEL
AD/INT3
SEL
WH17 WH16
WL17 WL16
POL
POL
0
INT3
POL
INT3
POL
INT3
POL
0
WH15 WH14
WL15 WL14
CRD31CRD32CRD33CRD34CRD35
CR34CR34
CR33
PN3
CR32
CR31
CR30
PN0PN1PN2
PW0PW1PW2PW3PW4PW5PW6
00
16
SYC0
SYC1SYC2SYC3SYC4SYC5
DSC30DSC31DSC32DSC37 DSC35
INT2
INT1
RE3
POL
POL
SM4 SM0
0
0
0
0
0
0
0
0
0
WH13 WH12 WH11
WL13 WL12 WL21
00
0
RE1RE2RE3RE5 SM1SM2SM3SM5
RE1RE2RE3RE5
PC1PC2PC5PC6PC7
RC1RC2RC5RC6RC7
RE1RE2RE5
000
FC2
CS0CS4 CS1CS2CS3CS5CS6
PC0RE1RE2RE3PC4RE5
RC0RE1RE2RE5
EC0EC1EC2
FC0FC1
WH10
WL20
WH20WH21
WL20WL21
?
?
?
?
?
?
?
?
00
16
?
? ?? ?0 00
00
16
07
16
FF
16
00
16
00
16
00
16
?
00
16
00
16
?
?
00
16
01 0 000 00
00
16
00
16
00
16
00
16
?
?
?
?
0
Fig. 7. Memory Map of Special Function Register 2 (SFR2) (1)
14
MITSUBISHI MICROCOMPUTERS
M37274EFSP
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
■ SFR2 area (addresses 22016 to 24816)
Address Register
Vertical position register 1
22016
Vertical position register 1
22116
Vertical position register 1
22216
Vertical position register 1
22316
Vertical position register 1
22416
Vertical position register 1
22516
Vertical position register 1
22616
Vertical position register 1
22716
Vertical position register 1
22816
Vertical position register 1
22916
Vertical position register 1
22A16
Vertical position register 1
22B16
22C16
Vertical position register 1
Vertical position register 1
22D16
22E16
Vertical position register 1
Vertical position register 1
22F16
Vertical position register 2
23016
Vertical position register 2
23116
Vertical position register 2
23216
Vertical position register 2
23316
23416
Vertical position register 2
Vertical position register 2
23516
Vertical position register 2
23616
23716
Vertical position register 2
Vertical position register 2
23816
Vertical position register 2
23916
Vertical position register 2
23A16
Vertical position register 2
23B16
Vertical position register 2
23C16
23D16
Vertical position register 2
23E16
Vertical position register 2
Vertical position register 2
23F16
DA-H register (DA-H)
16
240
DA-L register (DA-L)
24116
ROM correction address 1 (high-order)
24216
ROM correction address 1 (low-order)
24316
24416
ROM correction address 2 (high-order)
ROM correction address 2 (low-order)
24516
ROM correction enable register (RCR)
24616
24716
24816
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
<Bit allocation>
:
Function bit
:
Name
: No function bit
: Fix to this bit to “0”
0
State immediately after reset
: “0” immediately after reset
0
: “1” immediately after reset
1
: Indeterminate immediately
?
after reset
>
<
(do not write to “1”)
: Fix to this bit to “1”
1
(do not write to “0”)
(VP11)
1
(VP12)
2
(VP13)
3
(VP14)
4
(VP15)
5
(VP16)
6
(VP17)
7
(VP18)
8
(VP19)
9
(VP110)
10
(VP111)
11
(VP112)
12
(VP113)
13
(VP114)
14
(VP115)
15
(VP116)
16
(VP21)
1
(VP22)
2
(VP23)
3
(VP24)
4
(VP25)
5
(VP26)
6
(VP27)
7
(VP28)
8
(VP29)
9
(VP210)
10
(VP211)
11
(VP212)
12
(VP213)
13
(VP214)
14
(VP215)
15
(VP216)
16
b7
Bit allocation State immediately after reset
VP112VP113VP114VP115VP116VP117
VP1
VP1
VP1
VP1
VP1
VP1
VP1
VP1
VP1102VP1103VP1104VP1105VP1106VP1107
VP1
11
VP1142VP1143VP1144VP1145VP1146VP1147
VP1
15
VP1
16
VP111
VP1
2VP123VP124VP125VP126VP127
2
2
2VP133VP134VP135VP136VP137
VP1
3
3
VP1
2VP143VP144VP145VP146VP147
4
4
VP1
2VP153VP154VP155VP156VP157
5
5
VP1
2VP163VP164VP165VP166VP167
6
6
2VP173VP174VP175VP176VP177
VP1
7
7
VP1
2VP183VP184VP185VP186VP187
8
8
2VP193VP194VP195VP196VP197
VP1
9
9
VP1101
VP1
2VP1113VP1114VP1115VP1116VP1117
11
VP1
12
VP1131VP1132VP1133VP1134VP1135VP1136VP1137 VP1130
VP1
14
VP1
2VP1153VP1154VP1155VP1156VP1157
15
2VP1163VP1164VP1165VP1166VP1167
VP1
16
VP110
VP1
1
1
VP1
VP1
1
VP1
1
VP1
1
1
VP1
VP1
1
1
VP1
VP1100
VP1
1
1VP1122VP1123VP1124VP1125VP1126VP1127
VP1
1
VP1
VP1
1
1
VP1
VP2100VP2101
VP2110VP2111
VP2120VP2121
VP2130VP2131
VP2
VP2
VP2
b0
b7
b0
?
0
2
0
3
0
4
0
5
0
6
0
7
0
8
0
9
?
?
?
?
?
?
?
?
?
0
11
0
12
?
?
?
0
14
0
15
0
16
VP210VP211
VP220VP221
VP230VP231
VP240VP241
VP250VP251
VP260VP261
VP270VP271
VP280VP281
VP290VP291
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
0VP2141
14
0VP2151
15
0VP2161
16
?
?
?
?
00??????
0016
0016
0016
0016
0016
RCR0RCR1
00
000
0016
0016
0016
Fig. 8. Memory Map of Special Function Register 2 (SFR2) (2)
15
MITSUBISHI MICROCOMPUTERS
M37274EFSP
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
Register
Processor status register (PS)
Program counter (PCH)
Program counter (PCL)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
<
Bit allocation
>
:
Function bit
:
Name
:
No function bit
: Fix to this bit to “0”
0
and ON-SCREEN DISPLAY CONTROLLER
<
State immediately after reset
: “0” immediately after reset
0
: “1” immediately after reset
1
: Indeterminate immediately
?
>
after reset
(do not write to “1”)
: Fix to this bit to “1”
1
(do not write to “0”)
Bit allocation State immediately after reset
b7
b0
b7
I ZCDBTVN?????
1
Contents of address FFFF
Contents of address FFFE
b0
?
?
16
16
Fig. 9. Internal State of Processor Status Register and Program Counter at Reset
16
MITSUBISHI MICROCOMPUTERS
M37274EFSP
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
INTERRUPTS
Interrupts can be caused by 18 different sources consisting of 4 external, 12 internal, 1 software, and reset. Interrupts are vectored interrupts with priorities as shown in Table 1. Reset is also included in
the table because its operation is similar to an interrupt.
When an interrupt is accepted,
(1) The contents of the program counter and processor status
register are automatically stored into the stack.
(2) The interrupt disable flag I is set to “1” and the corresponding
interrupt request bit is set to “0.”
(3) The jump destination address stored in the vector address enters
the program counter.
Other interrupts are disabled when the interrupt disable flag is set to
“1.”
All interrupts except the BRK instruction interrupt have an interrupt
request bit and an interrupt enable bit. The interrupt request bits are
in interrupt request registers 1 and 2 and the interrupt enable bits are
in interrupt control registers 1 and 2. Figures 11 to 15 show the interrupt-related registers.
Interrupts other than the BRK instruction interrupt and reset are accepted when the interrupt enable bit is “1,” interrupt request bit is “1,”
and the interrupt disable flag is “0.” The interrupt request bit can be
set to “0” by a program, but not set to “1.” The interrupt enable bit can
be set to “0” and “1” by a program.
Reset is treated as a non-maskable interrupt with the highest priority.
Figure 10 shows interrupt control.
and ON-SCREEN DISPLAY CONTROLLER
Interrupt Causes
(1) VSYNC and OSD interrupts
The VSYNC interrupt is an interrupt request synchronized with
the vertical sync signal.
The OSD interrupt occurs after character block display to the
CRT is completed.
(2) INT1, INT2, INT3 interrupts
With an external interrupt input, the system detects that the level
of a pin changes from “L” to “H” or from “H” to “L,” and generates
an interrupt request. The input active edge can be selected by
bits 3, 4 and 6 of the interrupt input polarity register (address
021216) : when this bit is “0,” a change from “L” to “H” is detected;
when it is “1,” a change from “H” to “L” is detected. Note that all
bits are cleared to “0” at reset.
(3) Timer 1, 2, 3 and 4 interrupts
An interrupt is generated by an overflow of timer 1, 2, 3 or 4.
(4) Serial I/O interrupt
This is an interrupt request from the clock synchronous serial
I/O function.
(5) f(XIN)/4096 interrupt
This interrupt occurs regularly with a f(XIN)/4096 period. Set bit 0
of the PWM mode register 1 to “0.”
(6) Data slicer interrupt
An interrupt occurs when slicing data is completed.
(7) Multi-master I2C-BUS interface interrupt
This is an interrupt request related to the multi-master I2C-BUS
interface.
(8) A-D conversion interrupt
An interrupt occurs at the completion of A-D conversion. Since
A-D conversion interrupt and the INT3 interrupt share the same
vector, an interrupt source is selected by bit 7 of the interrupt
interval determination control register (address 021216).
Table 1. Interrupt Vector Addresses and Priority
Interrupt Source
Reset
OSD interrupt
INT1 interrupt
Data slicer interrupt
Serial I/O interrupt
Timer 4 interrupt
f(XIN)/4096 interrupt
VSYNC interrupt
Timer 3 interrupt
Timer 2 interrupt
Timer 1 interrupt
A-D convertion · INT3 interrupt
INT2 interrupt
Multi-master I2C-BUS interface interrupt
Timer 5 · 6 interrupt
BRK instruction interrupt
Note : Switching a source during a program causes an unnecessary interrupt occurs. Accordingly, set a source at initializing of program.
Priority
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Vector Addresses
FFFF16, FFFE16
FFFD16, FFFC16
FFFB16, FFFA16
FFF916, FFF816
FFF716, FFF616
FFF516, FFF416
FFF316, FFF216
FFF116, FFF016
FFEF16, FFEE16
FFED16, FFEC16
FFEB16, FFEA16
FFE916, FFE816
FFE716, FFE616
FFE516, FFE416
FFE316, FFE216
FFDF16, FFDE16
Remarks
Non-maskable
Active edge selectable
Active edge selectable
Software switch by software (See note)/
When selecting INT3 interrupt, active edge selectable.
Active edge selectable
Software switch by software (See note)
Non-maskable (software interrupt)
17
MITSUBISHI MICROCOMPUTERS
M37274EFSP
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
(9)Timer 5 · 6 interrupt
An interrupt is generated by an overflow of timer 5 or 6. Their
priorities are same, and can be switched by software.
(10)BRK instruction interrupt
This software interrupt has the least significant priority. It does
not have a corresponding interrupt enable bit, and it is not affected by the interrupt disable flag I (non-maskable).
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Interrupt request bit
Interrupt enable bit
Interrupt disable flag I
Fig. 10. Interrupt Control
BRK instruction
Reset
Interrupt
request
18
MITSUBISHI MICROCOMPUTERS
M37274EFSP
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
Interrupt Request Register 1
b7b6 b5b4b3 b2b1b0
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Interrupt request register 1 (IREQ1) [Address 00FC
B Name Functions
0
Timer 1 interrupt
request bit (TM1R)
1 Timer 2 interrupt
request bit (TM2R)
2 Timer 3 interrupt
request bit (TM3R)
Timer 4 interrupt
3
request bit (TM4R)
4 OSD interrupt request
bit (CRTR)
5V
SYNC
interrupt
request bit (VSCR)
A-D conversion • INT3
6
interrupt request bit (ADR)
Nothing is assigned. This bit is a write disable bit.
7
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
16
]
After reset
RW
0 ✽
R
0 ✽
R
0 ✽
R
0 ✽
R
0 ✽
R
0 ✽
R
0 ✽
R
0
R
—
When this bit is read out, the value is “0.”
✽: “0” can be set by software, but “1” cannot be set.
Fig. 11. Interrupt Request Register 1
Interrupt Request Register 2
b7b6 b5b4b3 b2b1b0
0
Interrupt request register 2 (IREQ2) [Address 00FD
B Name Functions
INT1 interrupt
0
request bit (INT1R)
Data slicer interrupt
1
request bit (DSR)
Serial I/O interrupt
2
request bit (SIOR)
IN
)/4096 interrupt
f(X
3
request bit (1MSR)
INT2 interrupt
4
request bit (INT2R)
2
Multi-master I
5
C-BUS
interrupt request bit (IICR)
6 Timer 5 • 6 interrupt
request bit (T56R)
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
7 Fix this bit to “0.”
16
]
After reset
RW
0 ✽
R
0 ✽
R
0 ✽
R
0
R ✽
0 ✽
R
0
R ✽
0
0
RW
✽R
Fig. 12. Interrupt Request Register 2
✽: “0” can be set by software, but “1” cannot be set.
19
MITSUBISHI MICROCOMPUTERS
M37274EFSP
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
Interrupt Control Register 1
b7b6 b5b4b3 b2b1b0
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Interrupt control register 1 (ICON1) [Address 00FE
B Name Functions
Timer 1 interrupt
0
enable bit (TM1E)
Timer 2 interrupt
1
enable bit (TM2E)
Timer 3 interrupt
2
enable bit (TM3E)
Timer 4 interrupt
3
enable bit (TM4E)
OSD interrupt enable bit
4
(CRTE)
SYNC
interrupt enable
V
5
bit (VSCR)
A-D conversion • INT3
6
interrupt enable bit (ADE)
Nothing is assigned. This bit is a write disable
7
bit. When this bit is read out, the value is “0.”
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
16]
After reset
0
0
0
0
0
0RW
0RW
0
RW
RW
RW
RW
RW
RW
R—
Fig. 13. Interrupt Control Register 1
Interrupt Control Register 2
b7b6 b5b4b3 b2b1b0
Interrupt control register 2 (ICON2) [Address 00FF
B Name Functions
INT1 interrupt
0
enable bit (INT1E)
Data slicer interrupt
1
enable bit (DSR)
Serial I/O interrupt
2
enable bit (SIOE)
IN
)/4096 interrupt
f(X
3
enable bit (1MSE)
INT2 interrupt enable
4
bit (INT2E)
Multi-master I2C-BUS interface
5
interrupt enable bit (IICE)
Timer 5 • 6 interrupt
6
enable bit (T56E)
Timer 5 • 6 interrupt
7
switch bit (TM56S)
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Timer 5
1 : Timer 6
16]
After reset
0
0
0
0
0
0RW
0RW
0RW
RW
RW
RW
RW
RW
RW
Fig. 14. Interrupt Control Register 2
20
MITSUBISHI MICROCOMPUTERS
M37274EFSP
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
Interrupt Input Polarity Register
b7 b6 b5 b4 b3 b2 b1 b0
0000
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Interrupt input polarity register (IP) [Address 0212
B Name Functions After reset R W
0 to 2,
Fix these bits to “0.”
5
3
INT1 polarity switch bit
(INT1POL)
4
INT2 polarity switch bit
(INT2POL)
6
INT3 polarity switch bit
(INT3POL)
7 A-D conversion • INT3
interrupt source selection
bit (RE7)
0 : Positive polarity
1 : Negative polarity
0 : Positive polarity
1 : Negative polarity
0 : Positive polarity
1 : Negative polarity
0 : Positive polarity
1 : Negative polarity
16
]
0
RW
0RW
RW
0
RW
0
0
RW
Fig. 15. Interrupt Input Polarity Register
21
MITSUBISHI MICROCOMPUTERS
M37274EFSP
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
TIMERS
The M37271MF-XXXSP has 6 timers: timer 1, timer 2, timer 3,
timer 4, timer 5, and timer 6. All timers are 8-bit timers with the 8-bit
timer latch. The timer block diagram is shown in Figure 18.
All of the timers count down and their divide ratio is 1/(n+1), where n
is the value of timer latch. By writing a count value to the corresponding timer latch (addresses 00F016 to 00F316 : timers 1 to 4, addresses
020C16 and 020D16 : timers 5 and 6), the value is also set to a timer,
simultaneously.
The count value is decremented by 1. The timer interrupt request bit
is set to “1” by a timer overflow at the next count pulse, after the
count value reaches “0016”.
(1) Timer 1
Timer 1 can select one of the following count sources:
f(XIN)/16 or f(XCIN)/16
•
f(XIN)/4096 or f(XCIN)/4096
•
External clock from the P42 TIM2 pin
•
The count source of timer 1 is selected by setting bits 5 and 0 of
timer mode register 1 (address 00F416). Either f(XIN) or f(XCIN) is
selected by bit 7 of the CPU mode register.
Timer 1 interrupt request occurs at timer 1 overflow.
(2) Timer 2
Timer 2 can select one of the following count sources:
f(XIN)/16 or f(XCIN)/16
•
Timer 1 overflow signal
•
External clock from the TIM2 pin
•
The count source of timer 2 is selected by setting bits 4 and 1 of
timer mode register 1 (address 00F416). Either f(XIN) or f(XCIN) is
selected by bit 7 of the CPU mode register. When timer 1 overflow
signal is a count source for the timer 2, the timer 1 functions as an 8bit prescaler.
Timer 2 interrupt request occurs at timer 2 overflow.
(3) Timer 3
Timer 3 can select one of the following count sources:
f(XIN)/16 or f(XCIN)/16
•
f(XCIN)
•
External clock from the TIM3 pin
•
The count source of timer 3 is selected by setting bit 0 of timer mode
register 2 (address 00F516) and bit 6 at address 00C716. Either f(XIN)
or f(XCIN) is selected by bit 7 of the CPU mode register.
Timer 3 interrupt request occurs at timer 3 overflow.
and ON-SCREEN DISPLAY CONTROLLER
(5) Timer 5
Timer 5 can select one of the following count sources:
f(XIN)/16 or f(XCIN)/16
•
Timer 2 overflow signal
•
Timer 4 overflow signal
•
The count source of timer 3 is selected by setting bit 6 of timer mode
register 1 (address 00F416) and bit 7 of timer mode register 2 (address 00F516). When overflow of timer 2 or 4 is a count source for
timer 5, either timer 2 or 4 functions as an 8-bit prescaler. Either
f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register.
Timer 5 interrupt request occurs at timer 5 overflow.
(6) Timer 6
Timer 6 can select one of the following count sources:
f(XIN)/16 or f(XCIN)/16
•
Timer 5 overflow signal
•
The count source of timer 6 is selected by setting bit 7 of timer mode
register 1 (address 00F416). Either f(XIN) or f(XCIN) is selected by bit
7 of the CPU mode register. When timer 5 overflow signal is a count
source for timer 6, timer 5 functions as an 8-bit prescaler.
Timer 6 interrupt request occurs at timer 6 overflow.
At reset, timers 3 and 4 are connected by hardware and “FF16” is
automatically set in timer 3; “0716” in timer 4. The f(XIN) ✽ /16 is selected as the timer 3 count source. The internal reset is released by
timer 4 overflow in this state and the internal clock is connected.
At execution of the STP instruction, timers 3 and 4 are connected by
hardware and “FF16” is automatically set in timer 3; “0716” in timer 4.
However, the f(XIN) ✽ /16 is not selected as the timer 3 count source.
So set both bit 0 of timer mode register 2 (address 00F516) and bit 6
at address 00C716 to “0” before execution of the STP instruction
(f(XIN) ✽ /16 is selected as the timer 3 count source). The internal
STP state is released by timer 4 overflow in this state and the internal clock is connected.
As a result of the above procedure, the program can start under a
stable clock.
✽ : When bit 7 of the CPU mode register (CM7) is “1,” f(XIN) be-
comes f(XCIN).
The structure of timer-related registers is shown in Figure 16 and 17.
(4) Timer 4
Timer 4 can select one of the following count sources:
f(XIN)/16 or f(XCIN)/16
•
f(XIN)/2 or f(XCIN)/2
•
f(XCIN)
•
The count source of timer 3 is selected by setting bits 1 and 4 of
timer mode register 2 (address 00F516). Either f(XIN) or f(XCIN) is
selected by bit 7 of the CPU mode register. When timer 3 overflow
signal is a count source for the timer 4, the timer 3 functions as an 8bit prescaler.
Timer 4 interrupt request occurs at timer 4 overflow.
22
MITSUBISHI MICROCOMPUTERS
M37274EFSP
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
Timer Mode Register 1
b7b6b5b4b3 b2b1 b0
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Timer mode register 1 (TM1) [Address 00F4
B
0
1
2
3
4
Name Functions
Timer 1 count source
selection bit 1 (TM10)
Timer 2 count source
selection bit 1 (TM11)
Timer 1 count
stop bit (TM12)
Timer 2 count stop
bit (TM13)
Timer 2 count source
selection bit 2
0: f(XIN)/16 or f(X
1: Count source selected by bit 5 of TM1
Count source selected by bit 4 of TM1
0:
1:
External clock from TIM2 pin
0: Count start
1: Count stop
0: Count start
1: Count stop
0: f(XIN)/16 or f(X
1: Timer 1 overflow
(TM14)
5
Timer 1 count source
selection bit 2 (TM15)
6
Timer 5 count source
selection bit 2 (TM16)
7 Timer 6 internal count
source selection bit
0: f(XIN)/4096 or f(X
1: External clock from TIM2 pin
0: Timer 2 overflow
1: Timer 4 overflow
0: f(XIN)/16 or f(X
1: Timer 5 overflow
(TM17)
Note: Either f(XIN) or f(X
CIN
) is selected by bit 7 of the CPU mode register.
16
]
CIN
)/16 (Note)
CIN
)/16 (See note)
CIN
)/4096 (See note)
CIN
)/16 (See note)
After reset
R
0
0
0
0
0
0WR
0WR
0WR
W
WR
WR
WR
WR
WR
Fig. 16. Timer Mode Register 1
Timer Mode Register 2
b7b6b5b4b3 b2b1b0
Timer mode register 2 (TM2) [Address 00F5
B
0
1, 4
2
3
5
6
7
Note: Either f(XIN) or f(X
Name Functions
Timer 3 count source
selection bit (TM20)
Timer 4 count source
selection bits
(TM21, TM24)
Timer 3 count
stop bit (TM22)
Timer 4 count stop bit
(TM23)
Timer 5 count stop bit
(TM25)
Timer 6 count stop bit
(TM26)
Timer 5 count source
selection bit 1
(TM27)
(b6 at address 00C7
b0
0 0 : f(X
0 1 : f(X
1 0 :
1 1 :
b4 b1
0 0 : Timer 3 overflow signal
0 1 : f(X
1 0 : f(X
1 1 : f(X
0: Count start
1: Count stop
0: Count start
1: Count stop
0: Count start
1: Count stop
0: Count start
1: Count stop
0: f(XIN)/16 or f(X
1: Count source selected by bit 6
CIN
) is selected by bit 7 of the CPU mode register.
External clock from TIM3 pin
of TM1
IN
)/16 or f(X
CIN
)
IN
)/16 or f(X
IN
)/2 or f(X
CIN
)
CIN
16
]
16
)
CIN
)/16 (See note)
CIN
)/16 (See note)
CIN
)/2 (See note)
)/16 (See note)
After reset
RW
0 RW
0RW
0
RW
0
RW
RW
0
RW
0
RW
0
Fig. 17. Timer Mode Register 2
23
MITSUBISHI MICROCOMPUTERS
M37274EFSP
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
CIN
X
XIN
TIM2
TIM3
CM7
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Data bus
8
1/4096
1/2
TM15
1/8
TM10
TM14
TM11
TM20
TM12
TM13
TM3EL
TM22
Timer 1 latch (8)
8
Timer 1 (8)
Timer 2 latch (8)
8
Timer 2 (8)
Timer 3 latch (8)
8
Timer 3 (8)
8
8
8
8
8
FF16
Timer 1
interrupt request
Timer 2
interrupt request
Reset
STP instruction
Timer 3
interrupt request
8
TM21
16)
TM24
TM27
TM17
TM23
TM25
TM26
TM21
Selection gate : Connected to
black side at
reset
TM1 : Timer mode register 1
TM2 : Timer mode register 2
TM3EL : Timer 3 count source
switch bit (address 00C7
CM : CPU mode register
Notes 1: HIGH pulse width of external clock inputs TIM2 and TIM3 needs 4 machine cycles or more.
2: When the external clock source is selected, timers 1, 2, and 3 are counted at a rising edge of input signal.
3: In the stop mode or the wait mode, external clock inputs TIM2 and TIM3 cannot be used.
Timer 4 latch (8)
8
Timer 4 (8)
TM16
Timer 5 latch (8)
8
Timer 5 (8)
Timer 6 latch (8)
8
Timer 6 (8)
0716
8
8
8
8
8
Timer 4
interrupt request
Timer 5
interrupt request
Timer 6
interrupt request
Fig. 18. Timer Block Diagram
24
MITSUBISHI MICROCOMPUTERS
M37274EFSP
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
SERIAL I/O
The M37274EFSP has a built-in serial I/O which can either transmit
or receive 8-bit data serially in the clock synchronous mode.
The serial I/O block diagram is shown in Figure 19. The synchronous
clock I/O pin (SCLK), and data output pin (SOUT) also function as port
P4, data input pin (SIN) also functions as port P1.
Bit 2 of the serial I/O mode register (address 021316) selects whether
the synchronous clock is supplied internally or externally (from the
P46/SCLK pin). When an internal clock is selected, bits 1 and 0 select
whether f(XIN) or f(XCIN) is divided by 8, 16, 32, or 64. To use SOUT
and P46/SCLK pins for serial I/O, set the corresponding bits of the
port P4 direction register (address 00C916) to “0.” To use SIN pin for
serial I/O, set the corresponding bit of the port P1 direction register
(address 00C316) to “0.”
X
CIN
1/2
X
IN
S
CLK
1/2
CM7
1/2
Synchronous
circuit
SM2
S
Serial I/O counter (8)
and ON-SCREEN DISPLAY CONTROLLER
The operation of the serial I/O is described below. The operation of
the serial I/O differs depending on the clock source; external clock or
internal clock.
Data bus
Frequency divider
1/2
1/81/4 1/16
SM1
SM0
Selection gate: Connect to
black side at
reset.
CM : CPU mode register
SM : Serial I/O mode register
Serial I/O
interrupt request
SM5
S
OUT
: LSB
MSB
(Note)
S
IN
Serial I/O shift register (8)
(Address 021416)
8
Note : When the data is set in the serial I/O register (address 021416), the register functions as the serial I/O shift register.
Fig. 19. Serial I/O Block Diagram
25
MITSUBISHI MICROCOMPUTERS
M37274EFSP
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
Internal clock : The serial I/O counter is set to “7” during the write
cycle into the serial I/O register (address 021416), and the transfer
clock goes “H” forcibly. At each falling edge of the transfer clock after
the write cycle, serial data is output from the SOUT pin. Transfer direction can be selected by bit 5 of the serial I/O mode register. At
each rising edge of the transfer clock, data is input from the SIN pin
and data in the serial I/O register is shifted 1 bit.
After the transfer clock has counted 8 times, the serial I/O counter
becomes “0” and the transfer clock stops at HIGH. At this time the
interrupt request bit is set to “1.”
and ON-SCREEN DISPLAY CONTROLLER
External clock : The an external clock is selected as the clock source,
the interrupt request is set to “1” after the transfer clock has been
counted 8 counts. However, transfer operation does not stop, so the
clock should be controlled externally. Use the external clock of 500kHz
or less with a duty cycle of 50%.
The serial I/O timing is shown in Figure 20. When using an external
clock for transfer, the external clock must be held at HIGH for initializing the serial I/O counter. When switching between an internal clock
and an external clock, do not switch during transfer. Also, be sure to
initialize the serial I/O counter after switching.
Notes 1: On programming, note that the serial I/O counter is set by
writing to the serial I/O register with the bit managing instructions, such as SEB and CLB.
2: When an external clock is used as the synchronous clock,
write transmit data to the serial I/O register when the transfer clock input level is HIGH.
Synchronous clock
Transfer clock
Serial I/O register
write signal
Serial I/O output
S
OUT
Serial I/O input
S
IN
Note : When an internal clock is selected, the S
Fig. 20. Serial I/O Timing (for LSB first)
D
0
D
1
D
2
D
3
D
4
D
OUT
pin is at high-impedance after transfer is completed.
(Note)
5
D
6
D
7
Interrupt request bit is set to “1”
26
MITSUBISHI MICROCOMPUTERS
M37274EFSP
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
Serial I/O Mode Register
b7b6b5b4b3 b2b1b0
0
0
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
CIN
16]
CIN
CIN
CIN
)/4
)/16
)/32
)/64
After reset
0
0
0
0
0
RW
RW
RW
RW
RW
RW
Serial I/O mode register (SM) [Address 0213
B Name Functions
Internal synchronous
0, 1
clock selection bits
(SM0, SM1)
Synchronous clock
2
selection bit (SM2)
Port function
3
selection bit (SM3)
Port function
4
selection bit (SM4)
Transfer direction
5
selection bit (SM5)
b1 b0
0 0: f(X
0 1: f(X
1 0: f(X
1 1: f(X
IN
)/4 or f(X
IN
)/16 or f(X
IN
)/32 or f(X
IN
)/64 or f(X
0: External clock
1: Internal clock
1
, P1
0: P1
3
1: SCL1, SDA1
0: P1
2
, P1
4
1: SCL2, SDA2
0: LSB first
1: MSB first
Fig. 21. Serial I/O Mode Register
Fix these bits to “0.” 0
6, 7
RW
27
MITSUBISHI MICROCOMPUTERS
M37274EFSP
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
PWM OUTPUT FUNCTION
The M37274EFSP is equipped with a 14-bit PWM (DA) seven 8-bit
PWMs (PWM0–PWM6). DA has a 14-bit resolution with the minimum resolution bit width of 0.25 µs and a repeat period of
4096 ms (for f(XIN) = 8 MHz). PWM0–PWM6 have the same circuit
structure and an 8-bit resolution with minimum resolution bit width of
4 µs and repeat period of 1024 µs (for f(XIN) = 8 MHz) .
Figure 22 shows the PWM block diagram. The PWM timing generating circuit applies individual control signals to PWM0–PWM6 using
f(XIN) divided by 2 as a reference signal.
(1) Data Setting
When outputting DA, first set the high-order 8 bits to the DA-H register (address 024016), then the low-order 6 bits to the DA-L register
(address 024116). When outputting PWM0–PWM6, set 8-bit output
data to the PWMi register (i means 0 to 6; addresses 020016 to
020616).
(2) Transmitting Data from Register to PWM circuit
Data transfer from the 8-bit PWM register to the 8-bit PWM circuit is
executed at writing data to the register.
The signal output from the 8-bit PWM output pin corresponds to the
contents of this register.
Also, data transfer from the DA register (addresses 024016 and
024116) to the 14-bit PWM circuit is executed at writing data to the
DA-L register (address 024116). Reading from the DA-H register (address 024016) means reading this transferred data. Accordingly, it is
possible to confirm the data being output from the D-A output pin by
reading the DA register.
(3) Operating of 8-bit PWM
The following explains PWM operation.
First, set the bit 0 of PWM mode register 1 (address 020A16) to “0”
(at reset, bit 0 is already set to “0” automatically), so that the PWM
count source is supplied.
PWM0–PWM3 are also used as pins P04–P07, PWM4–PWM6 are
also used as pins P00–P02, respectively. Set the corresponding bits
of the port P0 direction register to “1” (output mode). And select each
output polarity by bit 3 of PWM mode register 1 (address 020A16).
Then, set bits 7 to 0 of PWM mode register 2 to “1” (PWM output).
The PWM waveform is output from the PWM output pins by setting
these registers.
Figure 23 shows the 8-bit PWM timing. One cycle (T) is composed
of 256 (28) segments. The 8 kinds of pulses, relative to the weight of
each bit (bits 0 to 7), are output inside the circuit during 1 cycle.
Refer to Figure 20 (a). The 8-bit PWM outputs waveform which is
the logical sum (OR) of pulses corresponding to the contents of bits
0 to 7 of the 8-bit PWM register. Several examples are shown in
Figure 23 (b). 256 kinds of output (HIGH area: 0/256 to 255/256) are
selected by changing the contents of the PWM register. A length of
entirely HIGH cannot be output, i.e. 256/256.
and ON-SCREEN DISPLAY CONTROLLER
(4) Operating of 14-bit PWM
As with 8-bit PWM, set the bit 0 of the PWM mode register 1 (address 020A16) to “0” (at reset, bit 0 is already set to “0” automatically), so that the PWM count source is supplied. Pin DA is also used
as port P03. Select output mode by setting bit 3 of the port P0 direction register. Next, select the output polarity by bit 3 of the PWM
mode register 1. Then, the 14-bit PWM outputs from the D-A output
pin by setting bit 1 of the PWM mode register 1 to “0” (at reset, this bit
already set to “0” automatically) to select the DA output.
The output example of the 14-bit PWM is shown in Figure 23.
The 14-bit PWM divides the data of the DA latch into the low-order 6
bits and the high-order 8 bits.
The fundamental waveform is determined with the high-order 8-bit
data “DH.” A “H” level area with a length τ ✕ DH(“H” level area of
fundamental waveform) is output every short area of “t” = 256τ =
64 ms (τ is the minimum resolution bit width of 0.25 µs). The “H” level
area increase interval (tm) is determined with the low-order 6-bit data
“DL.” The “H” level are of smaller intervals “tm” shown in Table 6 is
longer by τ than that of other smaller intervals in PWM repeat period
“T” = 64t. Thus, a rectangular waveform with the different “H” width is
output from the D-A pin. Accordingly, the PWM output changes by τ
unit pulse width by changing the contents of the DA-H and DA-L
registers. A length of entirely “H” output cannot be output, i. e. 256/
256.
(5) Output after Reset
At reset, the output of ports P00–P02 and P04–P07 is in the highimpedance state and the contents of the PWM register and the PWM
circuit are undefined. Note that after reset, the PWM output is undefined until setting the PWM register.
28
MITSUBISHI MICROCOMPUTERS
M37274EFSP
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
Table 2. Relation Between Low-order 6-bit Data and High-level
Area Increase Interval
Low-order 6 bits of Data
0 0 0 0 0 0
0 0 0 0 0 1
0 0 0 0 1 0
0 0 0 1 0 0
0 0 1 0 0 0
0 1 0 0 0 0
1 0 0 0 0 0
Area Longer by τ Than That of Other tm (m = 0 to 63)
LSB
Nothing
m = 32
m = 16, 48
m = 8, 24, 40, 56
m = 4, 12, 20, 28, 36, 44, 52, 60
m =
2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62
m = 1, 3, 5, 7,................................. 57, 59, 61, 63
Data bus
DA-H register
(Address : 0240
b7 b0
DA latch
(14 bits)
MSB
8
1/2XIN
PWM0 register
(Address 0200
b7 b0
16
)
6
14-bit PWM circuit
PN0
16
)
14
PWM timing
generating
circuit
and ON-SCREEN DISPLAY CONTROLLER
DA-L register (Note)
(Address : 0241
LSB
6
P0
PN2
3
PN1
16
)
D0
3
D-A
Selection gate :
Connected to
black side at
reset.
Inside of
Fig. 22. PWM Block Diagram
8
8-bit PWM circuit
PWM1 register (Address 020116)
PWM2 register (Address 020216)
PWM3 register (Address 020316)
PWM4 register (Address 020416)
PWM5 register (Address 020516)
PWM6 register (Address 020616)
is as same contents with the others.
POL
PN
PW
P0
D0
4
P0
PW0
P0
5
PW1
P0
6
PW2
P0
7
PW3
P0
0
PW4
P0
1
PW5
P0
2
PW6
: PWM mode register 1
: PWM mode register 2
: Port P0 register
: Port P0 direction register
D0
4
D0
5
D0
6
D0
7
D0
0
D0
1
D0
2
(address 00C0
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
(address 020A16)
(address 020B
16
)
(address 00C1
16
)
16
)
29
MITSUBISHI MICROCOMPUTERS
M37274EFSP
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
5
255
254
250
240
230
220
210
200
190
180
170
150
140
130
120
110
100
90
80
70
60
50
40
30
20
9
7
5
3
1
160
252
250
246
244
242
238
236
234
230
228
226
222
220
218
214
212
210
206
204
202
198
196
194
190
188
186
182
180
178
174
172
170
166
164
162
158
156
154
150
148
146
142
138
134
132 140
130
126
124
122
118
116
114
110
108
106
102
100
98
94
92
90
86
84
82
78
76
74
70
68
66
62
60
58
54
52
50
46
44
42
38
36
34
30
28
26
22
20
18
14
12
10
6
4
2
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
248
240
232
224
216
208
200
192
184
176
168
160
152
144
136
120
104
88
72
56
40
24
8
128
112
96
(a) Pulses showing the weight of each bit
80
64
48
32
16
t
T = 256 t
t = 4 µs T = 1024 µs
PWM output
) = 8 MHz
IN
f(X
(b) Example of 8-bit PWM
Bit 7
Fig. 23. 8-bit PWM Timing
30
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(0)
16
00
(1)
16
01
(24)
16
18
(255)
16
FF
Loading...