Mitsubishi M37272MA-XXXSP, M37272M8-XXXSP, M37272M8-XXXFP, M37272M6-XXXSP, M37272M6-XXXFP Datasheet
...
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
1. DESCRIPTION
The M37272M6/M8-XXXSP/FP and M37272MA-XXXSP are singlechip microcomputers designed with CMOS silicon gate technology.
They have a OSD, data slicer, and I
for a channel selection system for TV with a closed caption decoder .
The features of the M37272E8SP/FP and M37272EFSP are similar
to those of the M37272M6-XXXSP except that the chip has a built-in
PROM which can be written electrically. The difference between
M37272M6-XXXSP/FP, M37272M8-XXXSP/FP and M37272MAXXXSP are the ROM size and RAM size. Accordingly, the following
descriptions will be for the M37272M6-XXXSP/FP.
2
C-BUS interface, so it is useful
2. FEATURES
●Number of basic instructions .................................................... 71
●Memory size
ROM .............. 24K bytes
(
M37272M6-XXXSP/FP
32K bytes
(
M37272M8-XXXSP/FP, M37272E8SP/FP
40K bytes
(
M37272MA-XXXSP
60K bytes
(
M37272EFSP
RAM ...............
(*ROM correction memory included)
●Minimum instruction execution time
......................................... 0.5 µs
●Power source voltage ................................................. 5 V ± 10 %
●Subroutine nesting .............................................128 levels (Max.)
●Interrupts....................................................... 17 types, 16 vectors
●8-bit timers .................................................................................. 6
●Programmable I/O ports (Ports P0, P1, P2, P3
●Input ports (Ports P5
●Output ports (Ports P5
●12 V withstand ports ................................................................... 6
●LED drive ports ........................................................................... 4
●Serial I/O ............................................................8-bit ✕ 1 channel
●Multi-master I
●A-D comparator (6-bit resolution) ................................6 channels
●PWM output circuit......................................................... 8-bit ✕ 6
●Power dissipation
In high-speed mode .........................................................165 mW
(at V
CC = 5.5V, 8 MHz oscillation frequency, OSD on, and Data
slicer on)
In low-speed mode .........................................................0.33 mW
(at V
CC = 5.5V, 32 kHz oscillation frequency)
●ROM correction function ................................................ 2 vectors
●Closed caption data slicer
2
C-BUS interface .............................. 1 (2 systems)
1024
bytes
(
M37272M6-XXXSP/FP
1152
bytes
M37272M8-XXXSP/FP, M37272E8SP/FP
(
1472
bytes
(
M37272MA-XXXSP, M37272EFSP
(at 8 MHz oscillation frequency)
0, P51) ........................................................ 2
2–P55) ..................................................... 4
)
)
)
)
)
0, P31) ............. 26
●OSD function
Display characters ................................... 32 characters ✕ 2 lines
Kinds of characters ........................................................254 kinds
Character display area............................ CC mode: 16 ✕ 26 dots
Kinds of character sizes..................................... CC mode: 1 kind
Kinds of character colors .................................. 8 colors (R, G, B)
Coloring unit................... character, character background, raster
Display position
Horizontal: 128 levels Vertical: 512 levels
Attribute ........................................................................................
CC mode: smooth italic, underline, flash, automatic solid space
OSD mode: border
Smoth roll-up
Window function
3. APPLICA TION
)
TV with a closed caption decoder
)
(It is possible to display 3 lines or more by software)
OSD mode: 16 ✕ 20 dots
OSD mode: 8 kinds
Rev. 1.5
TABLE OF CONTENTS
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
1. DESCRIPTION ..........................................................................1
2. FEAUTURES .............................................................................1
3. APPLICATION............................................................................1
4. PIN CONFIGURATION ..............................................................3
5. FUNCTIONAL BLOCK DIAGRAM .............................................4
6. PERFORMANCE OVERVIEW...................................................5
7. PIN DESCRIPTION ...................................................................7
8. FUNCTIONAL DESCRIPTION................................................. 11
8.1 CENTRAL PROCESSING UNIT (CPU) ....................11
8.2 MEMORY ..................................................................12
8.3 INTERRUPTS ...........................................................18
8.4 TIMERS.....................................................................23
8.5 SERIAL I/O................................................................26
8.6 MULTI-MASTER I
8.7 PWM OUTPUT CIRCUIT ..........................................42
8.8 A-D COMPARA TOR ..................................................46
8.9 ROM CORRECTION FUNCTION .............................48
8.10 DATA SLICER .........................................................49
8.11 OSD FUNCTIONS...................................................60
8.11.1 Display Position .......................................65
8.11.2 Dot size....................................................69
8.11.3 Clock for OSD..........................................70
8.11.4 Field Determination Display.....................71
8.11.5 Memory For OSD..................................... 73
8.11.6 Character Color .......................................77
8.11.7 Character Background Color ...................77
8.11.8 OUT1, OUT2 Signals...............................78
8.11.9 Attribute....................................................79
8.11.10 Multiple Display......................................84
8.11.11 Automatic Solid Space Function ............85
8.11.12 Window Function ...................................86
8.11.13 OSD Output Pin Control ........................88
8.11.14 Raster Coloring Function.......................89
8.12. SOFTWARE RUNAWAY DETECT FUNCTION .....91
8.13. RESET CIRCUIT....................................................92
8.14. CLOCK GENERATING CIRCUIT...........................93
8.15. DISPLAY OSCILLATION CIRCUIT ........................96
8.16. AUTO-CLEAR CIRCUIT .........................................96
8.17. ADDRESSING MODE ............................................96
8.18. MACHINE INSTRUCTIONS...................................96
2
C-BUS INTERFACE....................29
9. PROGRAMMING NOTES........................................................96
10. ABSOLUTE MAXIMUM RATINGS .........................................97
11. RECOMMENDED OPERATING CONDITIONS.....................97
12. ELECTRIC CHARACTERISTICS ..........................................98
13. A-D COMPARISON CHARACTERISTICS...........................100
14.
MULTI-MASTER I2C-BUS BUS LINE CHARACTERISTICS .........
15. PROM PROGRAMMING METHOD..................................... 101
16. DATA REQUIRED FOR MASK ORDERS............................102
17. MASK CONFIRMATION FORM...........................................103
18. MARK SPECIFICATION FORM........................................... 112
19. ONE TIME PROM VERSIONS M37272E8SP/FP,
M37272EFSP MARKING..................................................... 114
20. APPENDIX ........................................................................... 1 15
21. PACKAGE OUTLINE ...........................................................140
100
Rev. 1.3
2
F
4. PIN CONFIGURATION
C
C
F
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Fig. 4.1 Pin Configuration (1) (Top View)
P 50/ H
S Y N C
P 51/ V
S Y N C
P 00/ P W M 0
P 0
1
/ P W M 1
P 02/ P W M 2
P 03/ P W M 3
P 0
4
/ P W M 4
P 05/ P W M 5
P 06/ I N T 2 / A D 4
P 0
7
/ I N T 1
P 2
3
/ T I M 3
P 24/ T I M 2
P 2
A V
H L
V
H O L D
C V
C N V
X
X
O U T
V
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
5
1 3
1 4
C C
1 5
1 6
1 7
I N
1 8
S S
1 9
I N
2 0
2 1
S S
Outline 42P4B
4 2
P 52/ R
4 1
4 0
3 9
3 8
M
3 7 2 7 2 M 6 / M 8 / M A - X X X S PM
3 7 2 7 2 E 8 / E F S
3 7
3 6
3 5
3 4
3 3
3 2
P
3 1
3 0
2 9
2 8
2 7
2 6
2 5
2 4
2 3
2 2
3
/ G
P 5
P 5
4
/ B
P 55/ O U T 1
P 2
0
/ S
C L K
P 21/ S
O U T
P 22/ S
I N
P 10/ O U T 2
P 1
1
/ S C L 1
2
/ S C L 2
P 1
P 1
3
/ S D A 1
P 14/ S D A 2
P 1
5
/ A D 1 / I N T 3
P 16/ A D 2
P 17/ A D 3
P 3
0
/ A D 5
1
/ A D 6
P 3
R E S E T
P 2
6
/ O S C 1 / X
P 27/ O S C 2 / X
V
C C
C I N
C O U T
Fig. 4.2 Pin Configuration (2) (Top View)
Rev. 1.4
P 50/ H
S Y N
P 51/ V
S Y N
P 00/ P W M 0
1
/ P W M 1
P 0
2
/ P W M 2
P 0
3
/ P W M 3
P 0
4
/ P W M 4
P 0
5
/ P W M 5
P 0
P 06/ I N T 2 / A D 4
7
/ I N T 1
P 0
3
/ T I M 3
P 2
4
/ T I M 2
P 2
P 2
A V
H L
V
H O L D
C V
C N V
X
O U T
X
V
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
5
1 4
C C
1 5
1 6
1 7
I N
1 8
S S
1 9
I N
2 0
2 1
S S
M
P
Outline 42P2R-A/E
4 2
P 52/ R
4 1
4 0
3 9
3 8
3 7
3 7 2 7 2 M 6 / M 8 - X X X F PM
3 7 2 7 2 E 8 F
3 6
3 5
3 4
3 3
3 2
3 1
3 0
2 9
2 8
2 7
2 6
2 5
2 4
2 3
2 2
3
/ G
P 5
4
/ B
P 5
5
/ O U T 1
P 5
0
/ S
C L K
P 2
P 21/ S
O U T
P 22/ S
I N
P 10/ O U T 2
1
/ S C L 1
P 1
2
/ S C L 2
P 1
3
/ S D A 1
P 1
4
/ S D A 2
P 1
5
/ A D 1 / I N T 3
P 1
6
/ A D 2
P 1
P 17/ A D 3
0
/ A D 5
P 3
1
/ A D 6
P 3
R E S E T
6
/ O S C 1 / X
P 2
P 27/ O S C 2 / X
V
C C
C I N
C O U T
3
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
XI
N
XO
U
T
O
S C 1 /
XC
I
N
O
S C 2 /
X
C
O U
T
P
0 ( 8
)
I N T 1
I N T 2
I N T 3
P
1 ( 8
)
P W M 5
P W M 4
P W M 3
P W M 2
P W M 1
P W M 0
P
W
M
T
I M 2T
I M
3
1
92
02
51
42
22
11
8
C
VI
N
1
71
61
5
VH
O L
D
H
L
F
2
42
31
09
8765432
82
93
03
13
23
33
43
5
P
2 ( 8
)
1
31
21
1
3
6
3
7
I
/
O
p
o
r
t
P
1
I
/
O
p
o
r
t
P
2
P
3 ( 2
)
2
7
2
6
3
8
S D A 2
S D A 1
S C L 2
S C L 1
S
I
/
O
SI
N
SC
L
K
SO
U
T
P
5 ( 6
)
3
94
04
14
22
O
u
t
p
u
t
p
o
r
t
s
P
5
2–
P
55
O
u
t
p
u
t
f
o
r
d
i
s
p
l
a
y
1
H
S Y N C
V
S Y N C
R
G
B
O U T 1
O
U
T
2
P
10
I
/
O
p
o
r
t
s
P
3
0,
P
31
A D 1 – 6
D
a t a s l i c e rC
o n t r o l s i g n a
l
C
l
o
c
k
i
n
p
u
t
C
l o c k o u t p u tXI
N
XO
U
T
R
e s e t i n p u
t
A
VC
C
VC
C
VS
S
C
N
VS
S
P
i n s f o r d a t a s l i c e rC
l o c k o u t p u t f o r O S D /s
u b - c l o c k o u t p u tI
/ O p o r t s P
2
6,
P
27
C
l
o
c
k
i
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p
u
t
f
o
r
O
S
D
/
s
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b
-
c
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k
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p
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A
-
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c
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p
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a
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8
- b i
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a
r i t h m e t i
c
a
n d
l
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t
A
c
c
u
m
u
l
a
t
o
r
A
(
8
)
T
i
m
e
r
6
T
6 ( 8
)
T
i
m
e
r
5
T
5 ( 8
)
T
i
m
e
r
4
T
4
(
8
)
T
i
m
e
r
3
T
3
(
8
)
T
i
m
e
r
2
T
2 ( 8
)
T
i
m
e
r
1
T
1 ( 8
)
T
i m e r c o u n t s o u r c
e
s
e l e c t i o n c i r c u i
t
I
n s t r u c t i o
n
r
e g i s t e r ( 8
)
I
n
s
t
r
u
c
t
i
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n
d
e
c
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e
r
O
S
D
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c
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t
P
r o c e s s o
r
s
t a t u
s
r
e g i s t e
r
P
S ( 8
)
S
t a c
k
p
o i n t e
r
S
( 8
)
I
n
d
e
x
r
e
g
i
s
t
e
r
Y
(
8
)
I
n
d
e
x
r
e
g
i
s
t
e
r
X
(
8
)
R
O
M
P
r o g r a
m
c
o u n t e
r
P
CL
(
8
)
P
r
o
g
a
m
c
o
u
n
t
e
r
P
CH
(
8
)
R
A
M
D
a t a b u
s
C
l
o
c
k
g
e
n
e
r
a
t
i
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g
c
i
r
c
u
i
t
R
E S E TC
VI
N
A
d
d
r
e
s
s
b
u
s
I
/
O
p
o
r
t
P
0
R
O M c o r r e c t i o
n
c
i r c u i
t
M
u l t i - m a s t e r
I
2
C
- B U
S
i
n t e r f a c
e
I
n
p
u
t
p
o
r
t
s
P
5
0,
P
51
S
y
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h
r
o
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s
s
i
g
n
a
l
i
n
p
u
t
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
5. FUNCTIONAL BLOCK DIAGRAM
MITSUBISHI MICROCOMPUTERS
M37272E8SP/FP, M37272EFSP
and ON-SCREEN DISPLAY CONTROLLER
Fig. 5.1 Functional Block Diagram of M37272
4
Rev. 1.3
6. PERFORMANCE OVERVIEW
Table 6.1 Performance Overview
Parameter
Number of basic instructions
Instruction execution time
Clock frequency
Memory size
Input/Output
ports
Serial I/O
Multi-master I
A-D comparator
PWM output circuit
Timers
ROM correction function
Subroutine nesting
Interrupt
Clock generating circuit
Data slicer
ROM
M37272M6-XXXSP/FP
M37272M8-XXXSP/FP,M37272E8SP/FP
M37272MA-XXXSP
M37272EFSP
RAM
M37272M6-XXXSP/FP
M37272M8-XXXSP/FP,M37272E8SP/FP
M37272MA-XXXSP, M37272EFSP
OSD ROM
OSD RAM
P0
P1
0–P17
P20–P27
P30, P31
P50, P51
P52–P55
2
C-BUS interface
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Functions
71
0.5 µs (the minimum instruction execution time, at 8 MHz oscillation frequency)
8 MHz (maximum)
24K bytes
32K bytes
40K bytes
60K bytes
1024 bytes (ROM correction memory included)
1152 bytes (ROM correction memory included)
1472 bytes (ROM correction memory included)
10K bytes
128 bytes
I/O
I/O
I/O
I/O
Input
Output
8-bit ✕ 1 (N-channel open-drain output structure, can be used as PWM
output pins, INT input pins, A-D input pin)
8-bit ✕ 1 (CMOS input/output structure, however, N-channel open-drain
output structure, when P1
face, can be used as OSD output pin, A-D input pins, INT input pin, multi-
2
master I
8-bit ✕ 1 (P2 is CMOS input/output structure, however, N-channel open-
drain output structure when P2
used as serial input/output pins, timer external clock input pins, OSD clock
input/output pin, sub-clock input/output pins)
2-bit ✕ 1 (CMOS input/output or N-channel open-drain output structure,
can be used as A-D input pins)
2-bit ✕ 1 (can be used as OSD input pins)
4-bit ✕ 1 (CMOS output structure, can be used as OSD output pins)
8-bit ✕ 1
1 (2 systems)
6 channels (6-bit resolution)
8-bit ✕ 6
8-bit timer ✕ 6
2 vectors
128 levels (maximum)
<17 types>
INT external interrupt ✕ 3, Internal timer interrupt ✕ 6, Serial I/O interrupt ✕
1, OSD interrupt ✕ 1, Multi-master I
slicer interrupt ✕ 1, f(X
instruction interrupt ✕ 1, reset ✕ 1
2 built-in circuits (externally connected to a ceramic resonator or a quartzcrystal oscillator)
Built-in
C-BUS interface)
1–P14 are used as multi-master I
0 and 21 are used as serial output, can be
2
IN)/4096 interrupt ✕ 1, VSYNC interrupt ✕ 1, BRK
C-BUS interface interrupt ✕ 1, Data
2
C-BUS inter-
Rev. 1.3
5
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
Table 6.2 Performance Overview (Continued)
Parameter
OSD function
Power source voltage
Power
dissipation
Operating temperature range
Device structure
Package
In high-speed
mode
In low-speed
mode
In stop mode
Number of display characters
Dot structure
Kinds of characters
Kinds of character sizes
1 screen : 8
Character font coloring
Display position
OSD ON
OSD OFF
OSD OFF
Data slicer ON
Data slicer OFF
Data slicer OFF
MITSUBISHI MICROCOMPUTERS
M37272E8SP/FP, M37272EFSP
and ON-SCREEN DISPLAY CONTROLLER
Functions
32 characters ✕ 2 lines
CC mode: 16 ✕ 26 dots (character display area : 16 ✕ 20 dots)
OSD mode: 16 ✕ 20 dots
254 kinds
CC mode: 1 kinds
OSD mode: 8 kinds
1 screen: 8 kinds (per character unit)
Horizontal: 128 levels, Vertical: 512 levels
5V ± 10%
165 mW typ. ( at oscillation frequency f(X
82.5 mW typ. ( at oscillation frequency f(X
0.33 mW typ. ( at oscillation frequency f(X
0.055 mW ( maximum )
–10 °C to 70 °C
CMOS silicon gate process
42-pin plastic molded DIP
42-pin plastic molded SSOP
IN) = 8 MHz, fOSC = 27 MHz)
IN) = 8 MHz)
CIN) = 32 kHz, f(XIN) = stopped)
Rev. 1.3
6
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
7. PIN DESCRIPTION
Table 7.1 Pin Description
Pin Name
V
CC, AVCC, Power source Apply voltage of 5 V ± 10 % to (typical) VCC and AVCC, and 0 V to VSS.
VSS
CNVSS CNVSS This is connected to VSS.
RESET Reset input Input To enter the reset state, the reset input pin must be kept at a LOW for 2 µs or more (under
X
IN Clock input Input This chip has an internal clock generating circuit. To control generating frequency, an
OUT Clock output Output XOUT. If an external clock is used, the clock source should be connected to the XIN pin and
X
P00/PWM0–
I/O port P0 I/O Port P0 is an 8-bit I/O port with direction register allowing each I/O bit to be individually
P05/PWM5,
P06/INT2/AD4,
7/INT1
P0
PWM output Output Pins P0
External interrupt Input
input
Analog input Input P06 pin is also used as analog input pin AD4.
P1
0/OUT2, I/O port P1 I/O Port P1 is an 8-bit I/O port and has basically the same functions as port P0. The output
P11/SCL1,
P12/SCL2, OSD output Output Pins P10 is also used as OSD output pin OUT2. The output structure is CMOS output.
3/SDA1, Multi-master I/O Pins P11–P14 are used as SCL1, SCL2, SDA1 and SDA2 respectively, when multi-master
P1
P14/SDA2,
P15/AD1/INT3,
P1
6/AD2, External interrupt Input P15 pin is also used as INT external interrupt input pin INT3.
P17/AD3
P2
0/SCLK, I/O port P2 I/O Port P2 is an 8-bit I/O port and has basically the same functions as port P0. The output
2
C-BUS interface I2C-BUS interface is used. The output structure is N-channel open-drain output.
I
Analog input Input Pins P10, P15–P17 are also used as analog input pin AD8, AD1–AD3 respectively.
input
P21/SOUT,
P2
2/SIN,
P23/TIM3,
P2
4/TIM2, Serial I/O data I/O P21 pin is also used as serial I/O data output pin SOUT. The output structure is open-drain
P25,
P26/OSC1/
X
CIN,
P27/OSC2/
XCOUT
Serial I/O synchronous
clock input/output port
output output.
Serial I/O data input
External clock Input Pins P2
input for timer respectively.
Clock input for OSD
Clock output for OSD
Sub-clock input Input P26 pin is also used as sub-clock input pin XCIN.
Sub-clock output Output P27 pin is also used as sub-clock output pin XCOUT.
Input/
Output
normal V
CC conditions).
Functions
If more time is needed for the quartz-crystal oscillator to stabilize, this LOW condition should
be maintained for the required time.
external ceramic resonator or a quartz-crystal oscillator is connected between pins X
IN and
the XOUT pin should be left open.
programmed as input or output. At reset, this port is set to input mode. The output structure
is N-channel open-drain output. (See note 1)
0–P05 are also used as PWM output pins PWM0–PWM5 respectively. The output
structure is N-channel open-drain output.
Pins P06 and P07 are also used as INT external interrupt input pins INT2 and INT1 respectively .
structure is CMOS output. (See note 1)
structure is CMOS output. (See note 1)
I/O P20 pin is also used as serial I/O synchronous clock input/output pin SCLK. The output
structure is N-channel open-drain output.
Input P22 pin is also used as serial I/O data input pin SIN.
3 and P24 are also used as timer external clock input pins TIM3 and TIM2
Input P26 pin is also used as OSD clock input pin OSC1. (See note 2)
Output P27 pin is also used as OSD clock input pin OSC2. The output structure is CMOS output.
(See note 2)
Rev. 1.4
7
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Table 7.2 Pin Description (continued)
Pin Name
P3
0/AD5, I/O port P3 I/O Ports P30 and P31 are a 2-bit I/O port and has basically the same functions as port 0.
P3
1/AD6 The output structure can be selected either CMOS output or N-channel open-drain output
Analog input Input Pins P30 and P31 are also used as analog input pins AD5 and AD6 respectively.
P50/H
SYNC
,
Input port P5 Input Pin P50 and P51 are 2-bit input ports.
P51/V
SYNC
HSYNC input Input Pin P50 is also used as HSYNC input. This is a horizontal synchronous signal input for OSD.
VSYNC input Input Pin P51 is also used as VSYNC input. This is a vertical synchronous signal input for OSD.
P5
2/R, Output port P5 Output Ports P52–P55 are a 4-bit output port. The output structure is CMOS output.
P53/G,
P5
4/B,
OSD output Output Pins P5
P55/OUT1 structure is CMOS output.
CVIN I/O for data slicer Input Input composite video signal through a capacitor.
VHOLD Input Connect a capacitor between VHOLD and Vss.
HLF I/O Connect a filter using of a capacitor and a resistor between HLF and Vss.
Notes 1: Port Pi (i = 0 to 3) has the port Pi direction register which can be used to program each bit as an input (“0”) or an output (“1”). The pins programmed as “1”
in the direction register are output pins. When pins are programmed as “0,” they are input pins. When pins are programmed as output pins, the output data
are written into the port latch and then output. When data is read from the output pins, the output pin level is not read but the data of the port latch is read.
This allows a previously-output value to be read correctly even if the output LOW voltage has risen, for example, because a light emitting diode was directly
driven. The input pins are in the floating state, so the values of the pins can be read. When data is written into the input pin, it is written only into the port
latch, while the pin remains in the floating state.
2: To switch output functions, set the raster color register and OSD control register. When pins P2
the corresponding bits of the port P2 direction register to “0” (input mode).
3: To switch output structures, set bits 2 and 3 of the port P3 direction register, When “0,” CMOS output ; when “1,” N-channel open-drain output.
Input/
Output
Functions
structure. (See notes 1, 3)
2–P55 are also used as OSD output pins R, G, B, OUT1 respectively. The output
6 and P27 are used as the OSD clock input/output pins, set
Rev. 1.4
8
r
r
P o r t s P 00
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
–P
05
D i r e c t i o n r e g i s t e
N-channel open-drain output
0–P05
Ports P0
D a t a b u s
P o r t s P 1 , P 2 , P 30, P 31
D a t a b u s
P o r t l a t c h
D i r e c t i o n r e g i s t e
P o r t l a t c h
Notes 1: Each port is also used as follows :
0 : OUT2
P1
1 : SCL1
P1
2 : SCL2
P1
3 : SDA15
P1
4 : SDA2
P1
5 : AD1/INT3
P1
6 : AD2
P1
7 : AD3
P1
P2
0 : SCLK
P21 : SOUT
P22 : SIN
P23 : TIM3
4 : TIM2
P2
0 : AD5
P3
1 : AD6
P3
2: The output structure of ports P3
drain output structure (when selecting N-channel open-drain, it is the same with P0
3: The output structure of ports P1
2
C-BUS interface (it is the same with P06 and P07).
I
4: The output structure of ports P2
output (it is the same as P0
Note :Each port is also used as follows :
CMOS output
Ports P1
0 and P31 can be selected either CMOS output or N-channel open-
6 and P07).
1–P14 is N-channel open-drain output when using as multi-master
0 and P21 is N-channel open-drain output when using as serial
6 and P07).
0–P05 : PWM0–PWM5
P0
, P2, P30, P31
Fig. 7.1 I/O Pin Block Diagram (1)
Rev. 1.3
9
r
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
P o r t s P 06, P 0
D a t a b u s
P 50, P 5
1
I n t e r n a l c i r c u i t
7
D i r e c t i o n r e g i s t e
P o r t l a t c h
N-channel open-drain output
6, P07
Ports P0
Note :Each port is also used
as follows :
6 : INT2/AD4
P0
7 : INT1
P0
P 52– P 5
5
CMOS input
0, P51
Ports P5
Note : Each pin is also used
as follows :
0 : HSYNC
P5
P51 : VSYNC
I n t e r n a l c i r c u i t
CMOS output
2–P55
Ports P5
Note : Each pin is also used
as follows :
2 : R
P5
3 : G
P5
4 : B
P5
5 : OUT1
P5
Fig. 7.2 I/O Pin Block Diagram (2)
10
Rev. 1.4
MITSUBISHI MICROCOMPUTERS
A f t e r r e s e t
4
00516
W
W
W
7
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
8. FUNCTIONAL DESCRIPTION
8.1 CENTRAL PROCESSING UNIT (CPU)
This microcomputer uses the standard 740 Family instruction set.
Refer to the table of 740 Family addressing modes and machine
instructions or the SERIES 740 <Software> User’s Manual for details on the instruction set.
Machine-resident 740 Family instructions are as follows:
The FST, SLW instruction cannot be used.
The MUL, DIV, WIT and STP instructions can be used.
C P U M o d e R e g i s t e r
b 7b 6 b 5b 4b 3 b 2b 1b 0
1
1
C P U m o d e r e g i s t e r ( C M ) [ A d d r e s s 0 0 F B
B
P r o c e s s o r m o d e b i t s
0 , 1
N a m eF
( C M 0 , C M 1 )
8.1.1 CPU Mode Register
The CPU mode register contains the stack page selection bit and
internal system clock selection bit. The CPU mode register is allocated at address 00FB
u n c t i o n
b 1 b 0
0 0 : S i n g l e - c h i p m o d e
0 1 :
1 0 : N o t a v a i l a b l e
1 1 :
1 6
16.
]
s
RW
R
0
Fig. 8.1.1 CPU Mode Register
S t a c k p a g e s e l e c t i o n
2
b i t ( C M 2 ) ( S e e n o t e )
3 ,
F i x t h e s e b i t s t o “ 1 . ”
C O U T
d r i v a b i l i t y
X
s e l e c t i o n b i t ( C M 5 )
M a i n C l o c k ( X
s t o p b i t
( C M 6 )
I n t e r n a l s y s t e m c l o c k
s e l e c t i o n b i t
( C M 7 )
I N
– X
0 : 0 p a g e
1 : 1 p a g e
0 : L O W d r i v e
1 : H I G H d r i v e
O U T
)
0 : O s c i l l a t i n g
1 : S t o p p e d
0 : X
1 : X
I N
– X
O U T
s e l e c t e d
( h i g h - s p e e d m o d e )
C I N
– X
C O U T
s e l e c t e d
( h i g h - s p e e d m o d e )
N o t e : T h i s b i t i s s e t t o “ 1 ” a f t e r t h e r e s e t r e l e a s e .
1
RW
1
R
R
0
RW
0
RW
Rev. 1.3
11
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
8.2 MEMORY
8.2.1 Special Function Register (SFR) Area
The special function register (SFR) area in the zero page contains
control registers such as I/O ports and timers.
8.2.2 RAM
RAM is used for data storage and for stack area of subroutine calls
and interrupts.
8.2.3 ROM
ROM is used for storing user programs as well as the interrupt vector
area.
8.2.4 OSD RAM
RAM for display is used for specifying the character codes and colors to display.
8.2.5 OSD ROM
ROM for display is used for storing character data.
■ M 3 7 2 7 2 M 6 / M 8 - X X X S P / F P , M 3 7 2 7 2 E 8 S P / F P
8.2.6 Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
8.2.7 Zero Page
The 256 bytes from addresses 000016 to 00FF16 are called the zero
page area. The internal RAM and the special function registers (SFR)
are allocated to this area.
The zero page addressing mode can be used to specify memory and
register addresses in the zero page area. Access to this area with
only 2 bytes is possible in the zero page addressing mode.
8.2.8 Special Page
The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to
specify memory addresses in the special page area. Access to this
area with only 2 bytes is possible in the special page addressing
mode.
8.2.9 ROM Correction Memory (RAM)
This is used as the program area for ROM correction.
M 3 7 2 7 2 M 6 -
X X X S P / F P
R A M
( 1 0 2 4 b y t e s )
M 3 7 2 7 2 M 8 -
X X X S P / F P ,
M 3 7 2 7 2 E 8 S P / F P
R O M
( 3 2 K b y t e s )
M 3 7 2 7 2 M 8 X X X S P / F P ,
M 3 7 2 7 2 E 8 S P / F P
R A M
( 1 1 5 2 b y t e s )
O S D R A M
( 1 2 8 b y t e s )
( S e e n o t e )
O S D R O M
( 1 0 K b y t e s )
M 3 7 2 7 2 M 6 -
X X X S P / F P
R O M
( 2 4 K b y t e s )
0 0 0 0
0 0 B F
0 0 C 0
0 0 F F
0 1 0 0
0 1 F F
0 2 0 0
0 2 0 F
0 3 0 0
0 3 2 0
0 5 3 F
0 5 B F
0 8 0 0
0 8 7 F
1 4 0 0
3 B F F
8 0 0 0
A 0 0 0
F F 0 0
F F D E
F F F F
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
S F R 1 a r e a
S F R 2 a r e a
N o t u s e d
N o t u s e d
N o t u s e d
N o t u s e d
I n t e r r u p t v e c t o r a r e a
Z e r o p a g e
R O M c o r r e c t i o n f u n c t i o n
V e c t o r 1 : a d d r e s s 0 3 0 0
V e c t o r 2 : a d d r e s s 0 3 2 0
S p e c i a l p a g e
1 0 0 0 0
1 6
1 6
1 6
N o t u s e d
1 F F F F
1 6
N o t e : R e f e r t o T a b l e 8 . 1 1 . 3 O S D R A M .
Fig. 8.2.1 Memory Map (M37272M6/M8-XXXSP/FP, M37272E8SP/FP)
12
Rev. 1.4
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
■ M 3 7 2 7 2 M A - X X X S P , M 3 7 2 7 2 E F S P
0 0 0 0
MITSUBISHI MICROCOMPUTERS
M37272E8SP/FP, M37272EFSP
and ON-SCREEN DISPLAY CONTROLLER
1 0 0 0 0
1 6
1 6
( 1 4 7 2 b y t e s )
O S D R A M
( 1 2 8 b y t e s )
( S e e n o t e )
M 3 7 2 7 2 E F S P
R O M
( 6 0 K b y t e s )
M 3 7 2 7 2 M A - X X X S P
R O M
( 4 0 K b y t e s )
R A M
0 0 B F
0 0 C 0
0 0 F F
0 1 0 0
0 1 F F
0 2 0 0
0 2 0 F
0 3 0 0
0 3 2 0
0 6 F F
0 8 0 0
0 8 7 F
1 0 0 0
6 0 0 0
F F 0 0
F F D E
F F F F
1 6
1 6
S F R 1 a r e a
1 6
1 6
1 6
1 6
S F R 2 a r e a
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
I n t e r r u p t v e c t o r a r e a
1 6
N o t u s e d
N o t u s e d
N o t u s e d
Z e r o p a g e
R O M c o r r e c t i o n f u n c t r i o n
V e c t o r 1 : a d d r e s s 0 3 0 0
V e c t o r 2 : a d d r e s s 0 3 2 0
O S D R O M
( 1 0 K b y t e s )
S p e c i a l p a g e
N o t u s e d
1 6
1 6
1 1 4 0 0
1 6
1 3 B F F
1 6
N o t u s e d
1 F F F F
1 6
N o t e : R e f e r t o T a b l e 8 . 1 1 . 3 O S D R A M .
Fig. 8.2.2 Memory Map (M37272MA-XXXSP, M37272EFSP)
Rev. 1.3
13
t o D
4
5
3
0
4
5
3
0
■ S F R 1 A r e a ( a d d r e s s e s C 01
A d d r e s s
C 01
C 11
C 21
C 31
C 41
C 51
C 61
C 71
C 81
C 91
C A1
C B1
C C1
C D1
C E1
C F1
D 01
D 11
D 21
D 31
D 41
D 51
D 61
D 71
D 81
D 91
D A1
D B1
D C1
D D1
D E1
D F1
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
R e g i s t e r
P o r t P 0 ( P 0 )
P o r t P 0 d i r e c t i o n r e g i s t e r ( D 0 )
P o r t P 1 ( P 1 )
P o r t P 1 d i r e c t i o n r e g i s t e r ( D 1 )
P o r t P 2 ( P 2 )
P o r t P 2 d i r e c t i o n r e g i s t e r ( D 2 )
P o r t P 3 ( P 3 )
P o r t P 3 d i r e c t i o n r e g i s t e r ( D 3 )
P o r t P 5 ( P 5 )
O S D p o r t c o n t r o l r e g i s t e r ( P F )
C a p t i o n d a t a r e g i s t e r 3 ( C D 3 )
C a p t i o n d a t a r e g i s t e r 4 ( C D 4 )
O S D c o n t r o l r e g i s t e r ( O C )
H o r i z o n t a l p o s i t i o n r e g i s t e r ( H P )
B l o c k c o n t r o l r e g i s t e r 1 ( B C 1 )
B l o c k c o n t r o l r e g i s t e r 2 ( B C 2 )
V e r t i c a l p o s i t i o n r e g i s t e r 1 ( V P 1 )
V e r t i c a l p o s i t i o n r e g i s t e r 2 ( V P 2 )
W i n d o w r e g i s t e r 1 ( W N 1 )
W i n d o w r e g i s t e r 2 ( W N 2 )
I / O p o l a r i t y c o n t r o l r e g i s t e r ( P C )
R a s t e r c o l o r r e g i s t e r ( R C )
I n t e r r u p t i n p u t p o l a r i t y c o n t r o l r e g i s t e r ( R E )
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
6
F1
6)
< B i t a l l o c a t i o n >
:
F u n c t i o n b i t
N a m e
:
: N o f u n c t i o n b i t
: F i x t h i s b i t t o “ 0 ”
0
< S t a t e i m m e d i a t e l y a f t e r r e s e t >
: “ 0 ” i m m e d i a t e l y a f t e r r e s e t
0
1
: “ 1 ” i m m e d i a t e l y a f t e r r e s e t
: I n d e t e r m i n a t e i m m e d i a t e l y
?
a f t e r r e s e t
( d o n o t w r i t e “ 1 ” )
: F i x t h i s b i t t o “ 1 ”
1
( d o n o t w r i t e “ 0 ” )
b 7b
B i t a l l o c a t i o nS
t a t e i m m e d i a t e l y a f t e r r e s e
0
b 7b
?
1 6
0 0
?
1 6
0 0
?
1 6
0 0
3 1
C
P 3 0P 3 1
P 3 0 DP 3 1 DP 3 0 CT 3 S CP
0 01
6
?
?
?
0 01
0 0
6
1 6
0 01
P F 2P F 3P F 4P F 5P F 7
6
00
?
0
0
O C 6
H P 6
H P
B C 1 6B C 1 7
P C 6
P C
00
C D L 2 0C D L 2 1C D L 2 2C D L 2 3C D L 2 4C D L 2 5C D L 2 6C D L 2 7
H P 1
P C 1
C D H 2 0C D H 2 1C D H 2 2C D H 2 3C D H 2 4C D H 2 5C D H 2 6C D H 2 7
C 0O C
1
H P
B C 1 0B C 1 1
B C 2 0B C 2 1B C 2 2B C 2 3B C 2 4B C 2 5B C 2 6B C 2 7
V P 1 0V P 1 1V P 1 2V P 1 3V P 1 4V P 1 5V P 1 6V P 1 7
V P 2 0V P 2 1V P 2 2V P 2 3V P 2 4V P 2 5V P 2 6V P 2 7
W N 1 0W N 1 1W N 1 2W N 1 3W N 1 4W N 1 5W N 1 6W N 1 7
W N 2 0W N 2 1W N 2 2W N 2 3W N 2 4W N 2 5W N 2 6W N 2 7
P C
R C 0R C 1R C 2R C 7
O C 4O C 5O
H P
P C
C 2O C
3O
H P 2H P
B C 1 2B C 1 3B C 1 4B C 1 5
P C 2P C
R C 3R C 4
?
?
0 01
0 01
?
?
?
?
?
?
4 01
0 01
6
6
6
6
?
?
0 01
0 01
0 01
S e e n o t
0 01
6
6
6
6 (
0 01
0 01
S e e n o t
0 0
I N T 1I N T 2I N T 3
6
6
1
6 (
e 1)
e 2 )
t
0
??000000
N o t e s 1: T h i s i s o n l y M 3 7 2 7 2 M A - X X X S P a n d M 3 7 2 7 2 E F S P .
2: A s f o r M 3 7 2 7 2 M 6 / M 8 - X X X S P / F P a n d M 3 7 2 7 2 E 8 S P / F P , t h e r e s e t v a l u e i s ? ( i n d e t e r m i n a t e ) .
Fig. 8.2.3 Memory Map of Special Function Register 1 (SFR1) (1)
Rev. 1.4
14
MITSUBISHI MICROCOMPUTERS
6
6
6
6
6
6
6
6
6
6
6
6
6
R
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
■ S F R 1 A r e a ( a d d r e s s e s E 0
A d d r e s s
E 01
6
E 11
6
E 21
6
E 31
6
E 41
6
E 51
6
E 61
6
E 71
6
E 81
6
E 91
6
E A1
6
E B1
6
E C1
E D1
E E1
6
E F1
F 01
F 11
F 21
F 31
F 41
F 51
F 61
F 71
F 81
F 91
F A1
6
F B1
6
F C1
6
F D1
6
F E1
6
F F1
6
R e g i s t e r
D a t a s l i c e r c o n t r o l r e g i s t e r 1 ( D S C 1 )
D a t a s l i c e r c o n t r o l r e g i s t e r 2 ( D S C 2 )
C a p t i o n d a t a r e g i s t e r 1 ( C D 1 )
C a p t i o n d a t a r e g i s t e r 2 ( C D 2 )
C l o c k r u n - i n d e t e c t r e g i s t e r ( C R D )
D a t a c l o c k p o s i t i o n r e g i s t e r ( D P S )
C a p t i o n p o s i t i o n r e g i s t e r ( C P S )
D a t a s l i c e r t e s t r e g i s t e r 2
D a t a s l i c e r t e s t r e g i s t e r 1
S y n c h r o n o u s s i g n a l c o u n t e r r e g i s t e r ( H C )
S e r i a l I / O r e g i s t e r ( S I O )
S e r i a l I / O m o d e r e g i s t e r ( S M )
A - D c o n t r o l r e g i s t e r 1 ( A D 1 )
A - D c o n t r o l r e g i s t e r 2 ( A D 2 )
T i m e r 5 ( T 5 )
T i m e r 6 ( T 6 )
T i m e r 1 ( T 1 )
T i m e r 2 ( T 2 )
T i m e r 3 ( T 3 )
T i m e r 4 ( T 4 )
T i m e r m o d e r e g i s t e r 1 ( T M 1 )
T i m e r m o d e r e g i s t e r 2 ( T M 2 )
2
I
C d a t a s h i f t r e g i s t e r ( S 0 )
2
I
C a d d r e s s r e g i s t e r ( S 0 D )
2
I
C s t a t u s r e g i s t e r ( S 1 )
2
I
C c o n t r o l r e g i s t e r ( S 1 D )
2
I
C c l o c k c o n t r o l r e g i s t e r ( S 2 )
C P U m o d e r e g i s t e r ( C P U M )
I n t e r r u p t r e q u e s t r e g i s t e r 1 ( I R E Q 1 )
I n t e r r u p t r e q u e s t r e g i s t e r 2 ( I R E Q 2 )
I n t e r r u p t c o n t r o l r e g i s t e r 1 ( I C O N 1 )
I n t e r r u p t c o n t r o l r e g i s t e r 2 ( I C O N 2 )
1 6
t o F F
< B i t a l l o c a t i o n >
N a m e
0
1 6
)
:
F u n c t i o n b i t
:
: N o f u n c t i o n b i t
: F i x t h i s b i t t o “ 0 ”
< S t a t e i m m e d i a t e l y a f t e r r e s e t >
: “ 0 ” i m m e d i a t e l y a f t e r r e s e t
0
: “ 1 ” i m m e d i a t e l y a f t e r r e s e t
1
: I n d e t e r m i n a t e i m m e d i a t e l y
?
a f t e r r e s e t
( d o n o t w r i t e “ 1 ” )
: F i x t h i s b i t t o “ 1 ”
1
( d o n o t w r i t e “ 0 ” )
b 7b
B i t a l l o c a t i o nS
01100
01
T M 2 6T M 2 7
B S E L 0B S E L 1
A C K
B I T
I N 3 R
T M 5 6 R
I N 3 E
T M 5 6 ET M 5 6 C
S M 5S M 6
T M 1 5T M 1 6T M 1 7
T M 2 5
1 0 B I T
S A D
F A S T
M O D E
00
C M 7C M 5C M 6
D S C 2 3D S C 2 4D S C 2 5
C R D 3C R D 4C R D 5C R D 6C R D 7
D P S 3D P S 4D P S 5D P S 6D P S 7
A D C 2 4A D C 2 3
101
C K 0 I N 1 R
C K
I N 2 RI I C R
C K EI I C E
D L 1 1C D L 1
2C D L 1 6C D L 1 7
D H 1 1C D H 1
2C D H 1 6C D H 1 7
1
P S 1C P S
2C P S 6C P S 7
C 1H C
2
D 1D 2D 3D 4D 5D 6D 7D
S A D 0S A D 1S A D 2S A D 3S A D 4S A D 5S A D 6R
C M 2
D S R
S 1 R
t a t e i m m e d i a t e l y a f t e r r e s e
b 7b
0
D S C 1 0D S C 1 1D S C 1 2
D S C 2 0
C D L 1 0C D L 1 3C D L 1 4C D L 1 5C
C D H 1 0C D H 1 3C D H 1 4C D H 1 5C
00
C P S 0C P S 3C P S 4C P S 5C
H C 0H C 3H C 4H C 5H
S M 0S M 1S M 2S M 3
A D C 1 0A D C 1 1A D C 1 2A D C 1 4
A D C 2 0A D C 2 1A D C 2 2A D C 2 5
T M 1 0T M 1 1T M 1 2T M 1 3T M 1 4
T M 2 0T M 2 1T M 2 2T M 2 3T M 2 4
0
B
W
L R BA D 0A A SA LP I NB BT R XM S T
B C 0B C 1B C 2E S OA L S
C C R 0C C R 1C C R 2C C R 3C C R 4A C K
00
T M 1 RT M 2 RT M 3 RT M 4 RO S D RV S C R
T M 1 ET M 2 ET M 3 ET M 4 EO S D EV S C E
I N 1 ED S ES 1 EI N 2 E
0?0? 0???
0 01
6
0 01
6
0 01
6
0 01
6
0 91
6
0 01
6
0 01
6
0 01
6
?
0 01
6
0000
?
0 01
6
0 71
6
F F1
6
F F1
6
0 71
6
F F1
6
0 71
6
0 01
6
0 01
6
?
0 01
6
0 01
0 01
3 C1
0 01
0 01
0 01
0 01
00 0 010 0?
6
6
6
6
6
6
6
t
0
0000?00 0
000
Fig. 8.2.4 Memory Map of Special Function Register 1 (SFR1) (2)
Rev. 1.3
15
MITSUBISHI MICROCOMPUTERS
6
6
6
6
6
6
6
6
6
6
6
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
■ S F R 2 A r e a ( a d d r e s s e s 2 0 0
A d d r e s s
2 0 0
1
2 0 1
1
2 0 2
1
2 0 3
1
2 0 4
1
2 0 5
1
2 0 6
1
2 0 7
1
2 0 8
1
2 0 9
1
2 0 A
1 6
2 0 B
1 6
2 0 C
1 6
2 0 D
1 6
2 0 E
1 6
2 0 F
1
P W M 0 r e g i s t e r ( P W M 0 )
P W M 1 r e g i s t e r ( P W M 1 )
P W M 2 r e g i s t e r ( P W M 2 )
P W M 3 r e g i s t e r ( P W M 3 )
P W M 4 r e g i s t e r ( P W M 4 )
P W M 5 r e g i s t e r ( P W M 5 )
P W M m o d e r e g i s t e r 1 ( P M 1 )
P W M m o d e r e g i s t e r 2 ( P M 2 )
R O M c o r r e c t i o n a d d r e s s 1 ( h i g h - o r d e r )
R O M c o r r e c t i o n a d d r e s s 1 ( l o w - o r d e r )
R O M c o r r e c t i o n a d d r e s s 2 ( h i g h - o r d e r )
O M c o r r e c t i o n a d d r e s s 2 ( l o w - o r d e r
R
O M c o r r e c t i o n e n a b l e r e g i s t e r ( R C R
R
R e g i s t e r
)
1 6
t o 2 0 F
< B i t a l l o c a t i o n >
:
N a m e
:
: N o f u n c t i o n b i t
: F i x t h i s b i t t o “ 0 ”
0
( d o n o t w r i t e “ 1 ” )
: F i x t h i s b i t t o “ 1 ”
1
( d o n o t w r i t e “ 0 ” )
b 7b
1 6
)
< S t a t e i m m e d i a t e l y a f t e r r e s e t >
: “ 0 ” i m m e d i a t e l y a f t e r r e s e t
F u n c t i o n b i t
B i t a l l o c a t i o nS
0
1
: “ 1 ” i m m e d i a t e l y a f t e r r e s e t
: I n d e t e r m i n a t e i m m e d i a t e l y
?
a f t e r r e s e t
t a t e i m m e d i a t e l y a f t e r r e s e
0
b 7b
?
?
?
?
?
?
0 0
00
)
1 6
1 6
0 0
P M 1 3
P M 2 5P M 2 4P M 2 3P M 2 2P M 2 1P M 2 0
P M 1 0
R C 0R C 1
? ???0 ?? 0
0 0
0 0
0 0
0 0
0 0
0 0
?
?
1 6
1 6
1 6
1 6
1 6
1 6
?
t
0
Fig. 8.2.5 Memory Map of Special Function Register 2 (SFR2)
16
Rev. 1.3
R e g i s t e r
P r o c e s s o r s t a t u s r e g i s t e r ( P S )
P r o g r a m c o u n t e r ( P CH)
P r o g r a m c o u n t e r ( P CL)
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
<
<
B i t a l l o c a t i o n
:
:
N a m e
:
N o f u n c t i o n b i t
: F i x t o t h i s b i t t o “ 0 ”
0
>
F u n c t i o n b i t
( d o n o t w r i t e t o “ 1 ” )
: F i x t o t h i s b i t t o “ 1 ”
1
( d o n o t w r i t e t o “ 0 ” )
B i t a l l o c a t i o nS
b 7
0
1
?
b 0
b 7
I Z CDBTVN???????
S t a t e i m m e d i a t e l y a f t e r r e s e t
: “ 0 ” i m m e d i a t e l y a f t e r r e s e t
: “ 1 ” i m m e d i a t e l y a f t e r r e s e t
: I n d e t e r m i n a t e i m m e d i a t e l y
a f t e r r e s e t
t a t e i m m e d i a t e l y a f t e r r e s e
1
C o n t e n t s o f a d d r e s s F F F F
C o n t e n t s o f a d d r e s s F F F E
>
t
b 0
1 6
1 6
Fig. 8.2.6 Internal State of Processor Status Register and Program Counter at Reset
Rev. 1.3
17
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
8.3 INTERRUPTS
Interrupts can be caused by 17 different sources consisting of 4 external, 11 internal, 1 software, and reset. Interrupts are vectored interrupts with priorities as shown in T able 8.3.1. Reset is also included
in the table because its operation is similar to an interrupt.
When an interrupt is accepted,
① The contents of the program counter and processor status regis-
ter are automatically stored into the stack.
➁ The interrupt disable flag I is set to “1” and the corresponding
interrupt request bit is set to “0.”
➂ The jump destination address stored in the vector address enters
the program counter.
Other interrupts are disabled when the interrupt disable flag is set to
“1.”
All interrupts except the BRK instruction interrupt have an interrupt
request bit and an interrupt enable bit. The interrupt request bits are
in interrupt request registers 1 and 2 and the interrupt enable bits are
in interrupt control registers 1 and 2. Figures 8.3.2 to 8.3.6 show the
interrupt-related registers.
Interrupts other than the BRK instruction interrupt and reset are accepted when the interrupt enable bit is “1,” interrupt request bit is “1,”
and the interrupt disable flag is “0.” The interrupt request bit can be
set to “0” by a program, but not set to “1.” The interrupt enable bit can
be set to “0” and “1” by a program.
Reset is treated as a non-maskable interrupt with the highest priority.
Figure 8.3.1 shows interrupt control.
8.3.1 Interrupt Causes
(1) V
SYNC, OSD interrupts
The VSYNC interrupt is an interrupt request synchronized with
the vertical sync signal.
The OSD interrupt occurs after character block display to the
CRT is completed.
(2) INT1 to INT3 external interrupts
The INT1 to INT3 interrupts are external interrupt inputs, the system detects that the level of a pin changes from LOW to HIGH or
from HIGH to LOW, and generates an interrupt request. The input active edge can be selected by bits 3 to 5 of the interrupt
input polarity register (address 00DC
change from LOW to HIGH is detected; when it is “1,” a change
from HIGH to LOW is detected. Note that both bits are cleared to
“0” at reset.
16) : when this bit is “0,” a
(3) Timers 1 to 4 interrupts
An interrupt is generated by an overflow of timers 1 to 4.
Table 8.3.1 Interrupt Vector Addresses and Priority
Priority
1
Reset
2
OSD interrupt
3
INT1 external interrupt
4
Data slicer interrupt
5
Serial I/O interrupt
6
Timer 4 interrupt
7
f(X
IN)/4096 interrupt
8
V
SYNC interrupt
9
Timer 3 interrupt
10
Timer 2 interrupt
11
Timer 1 interrupt
12
INT3 external interrupt
13
INT2 external interrupt
14
Multi-master I
15
Timer 5 • 6 interrupt
16
BRK instruction interrupt
Note: Switching a source during a program causes an unnecessary interrupt. Therefore, set a source at initializing of program.
Interrupt Source
2
C-BUS interface interrupt
Vector Addresses
FFFF
16, FFFE16
FFFD16, FFFC16
FFFB16, FFFA16
FFF916, FFF816
FFF716, FFF616
FFF516, FFF416
FFF316, FFF216
FFF116, FFF016
FFEF16, FFEE16
FFED16, FFEC16
FFEB16, FFEA16
FFE916, FFE816
FFE716, FFE616
FFE516, FFE416
FFE316, FFE216
FFDF16, FFDE16
Non-maskable
Active edge selectable
Active edge selectable
Active edge selectable
Source switch by software (see note)
Non-maskable
Remarks
18
Rev. 1.3
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
t
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
(4) Serial I/O interrupt
This is an interrupt request from the clock synchronous serial I/O
function.
(5) f(XIN)/4096 interrupt
The f (XIN)/4096 interrupt occurs regularly with a f(XIN)/4096 period. Set bit 0 of the PWM mode register 1 to “0.”
(6) Data slicer interrupt
An interrupt occurs when slicing data is completed.
(7) Multi-master I2C-BUS interface interrupt
This is an interrupt request related to the multi-master I2C-BUS
interface.
MITSUBISHI MICROCOMPUTERS
M37272E8SP/FP, M37272EFSP
and ON-SCREEN DISPLAY CONTROLLER
I n t e r r u p t r e q u e s t b i
I n t e r r u p t e n a b l e b i t
I n t e r r u p t d i s a b l e f l a g I
B R K i n s t r u c t i o n
R e s e t
I n t e r r u p t
r e q u e s t
(8) Timer 5 • 6 interrupt
An interrupt is generated by an overflow of timer 5 or 6. Their
priorities are same, and can be switched by software.
(9) BRK instruction interrupt
This software interrupt has the least significant priority. It does
not have a corresponding interrupt enable bit, and it is not affected by the interrupt disable flag I (non-maskable).
Fig. 8.3.1 Interrupt Control
Rev. 1.3
19
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
6
5
W
6
I n t e r r u p t R e q u e s t R e g i s t e r 1
b 7b 6 b 5b 4b 3 b 2b 1b 0
I n t e r r u p t r e q u e s t r e g i s t e r 1 ( I R E Q 1 ) [ A d d r e s s 0 0 F C
BN
0
1T i m e r 2 i n t e r r u p t
2T i m e r 3 i n t e r r u p t
3
4O S D i n t e r r u p t r e q u e s t
5V
6
7
MITSUBISHI MICROCOMPUTERS
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
1 6
]
a m
eF
T i m e r 1 i n t e r r u p t
r e q u e s t b i t ( T M 1 R )
r e q u e s t b i t ( T M 2 R )
r e q u e s t b i t ( T M 3 R )
T i m e r 4 i n t e r r u p t
r e q u e s t b i t ( T M 4 R )
b i t ( O S D R )
S Y N C
i n t e r r u p t
r e q u e s t b i t ( V S C R )
I N T 3 e x t e r n a l i n t e r r u p t
r e q u e s t b i t ( V S C R )
N o t h i n g i s a s s i g n e d . T h i s b i t i s a w r i t e d i s a b l e b i t .
W h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s “ 0 . ”
u n c t i o n
s
0 : N o i n t e r r u p t r e q u e s t i s s u e d
1 : I n t e r r u p t r e q u e s t i s s u e d
0 : N o i n t e r r u p t r e q u e s t i s s u e d
1 : I n t e r r u p t r e q u e s t i s s u e d
0 : N o i n t e r r u p t r e q u e s t i s s u e d
1 : I n t e r r u p t r e q u e s t i s s u e d
0 : N o i n t e r r u p t r e q u e s t i s s u e d
1 : I n t e r r u p t r e q u e s t i s s u e d
0 : N o i n t e r r u p t r e q u e s t i s s u e d
1 : I n t e r r u p t r e q u e s t i s s u e d
0 : N o i n t e r r u p t r e q u e s t i s s u e d
1 : I n t e r r u p t r e q u e s t i s s u e d
0 : N o i n t e r r u p t r e q u e s t i s s u e d
1 : I n t e r r u p t r e q u e s t i s s u e d
A f t e r r e s e t
0
0
0
0
0
0
0
0
RW
R
✽
R
✽
R
✽
R
✽
R
✽
R
✽
R
✽
—
R
Fig. 8.3.2 Interrupt Request Register 1
I n t e r r u p t R e q u e s t R e g i s t e r 2
b 7b
b 5b 4b 3 b 2b 1b 0
0
✽: “ 0 ” c a n b e s e t b y s o f t w a r e , b u t “ 1 ” c a n n o t b e s e t .
I n t e r r u p t r e q u e s t r e g i s t e r 2 ( I R E Q 2 ) [ A d d r e s s 0 0 F D
BN
0
a m
eF
I N T 1 e x t e r n a l i n t e r r u p t
r e q u e s t b i t ( I N I R )
D a t a s l i c e r i n t e r r u p t
1
r e q u e s t b i t ( D S R )
2
S e r i a l I / O i n t e r r u p t
r e q u e s t b i t ( S 1 R )
/ 4 0 9 6 i n t e r r u p t
f ( XI
N)
3
r e q u e s t b i t ( C K R )
4
I N T 2 e x t e r n a l i n t e r r u p t
r e q u e s t b i t ( I N 2 R )
2
M u l t i - m a s t e r I
C - B U S
i n t e r r u p t r e q u e s t b i t ( I I C R )
T i m e r 5 • 6 i n t e r r u p t
r e q u e s t b i t ( T M 5 6 R )
u n c t i o n
0 : N o i n t e r r u p t r e q u e s t i s s u e d
1 : I n t e r r u p t r e q u e s t i s s u e d
0 : N o i n t e r r u p t r e q u e s t i s s u e d
1 : I n t e r r u p t r e q u e s t i s s u e d
0 : N o i n t e r r u p t r e q u e s t i s s u e d
1 : I n t e r r u p t r e q u e s t i s s u e d
0 : N o i n t e r r u p t r e q u e s t i s s u e d
1 : I n t e r r u p t r e q u e s t i s s u e d
0 : N o i n t e r r u p t r e q u e s t i s s u e d
1 : I n t e r r u p t r e q u e s t i s s u e d
0 : N o i n t e r r u p t r e q u e s t i s s u e d
1 : I n t e r r u p t r e q u e s t i s s u e d
0 : N o i n t e r r u p t r e q u e s t i s s u e d
1 : I n t e r r u p t r e q u e s t i s s u e d
7F i x t h i s b i t t o “ 0 . ”
1 6]
s
A f t e r r e s e t
0
0
0
0
0
0
0
0
RW
R
✽
R
✽
R
✽
R
✽
R
✽
R
✽
R
✽
R
✽: “ 0 ” c a n b e s e t b y s o f t w a r e , b u t “ 1 ” c a n n o t b e s e t .
Fig. 8.3.3 Interrupt Request Register 2
Rev. 1.3
20
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
7
5
6
5
6
7
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
I n t e r r u p t C o n t r o l R e g i s t e r 1
b 7b 6 b 5b 4b 3 b 2b 1b 0
I n t e r r u p t c o n t r o l r e g i s t e r 1 ( I C O N 1 ) [ A d d r e s s 0 0 F E
BN
0
1
2
3
4
MITSUBISHI MICROCOMPUTERS
M37272E8SP/FP, M37272EFSP
and ON-SCREEN DISPLAY CONTROLLER
a m
eF
T i m e r 1 i n t e r r u p t
e n a b l e b i t ( T M 1 E )
T i m e r 2 i n t e r r u p t
e n a b l e b i t ( T M 2 E )
T i m e r 3 i n t e r r u p t
e n a b l e b i t ( T M 3 E )
T i m e r 4 i n t e r r u p t
e n a b l e b i t ( T M 4 E )
O S D i n t e r r u p t e n a b l e b i t
( O S D E )
V
S Y N C
i n t e r r u p t e n a b l e
b i t ( V S C E )
I N T 3 e x t e r n a l i n t e r r u p t
e n a b l e b i t ( I N 3 E )
N o t h i n g i s a s s i g n e d . T h i s b i t i s a w r i t e d i s a b l e
b i t . W h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s “ 0 . ”
u n c t i o n
0 : I n t e r r u p t d i s a b l e d
1 : I n t e r r u p t e n a b l e d
0 : I n t e r r u p t d i s a b l e d
1 : I n t e r r u p t e n a b l e d
0 : I n t e r r u p t d i s a b l e d
1 : I n t e r r u p t e n a b l e d
0 : I n t e r r u p t d i s a b l e d
1 : I n t e r r u p t e n a b l e d
0 : I n t e r r u p t d i s a b l e d
1 : I n t e r r u p t e n a b l e d
0 : I n t e r r u p t d i s a b l e d
1 : I n t e r r u p t e n a b l e d
0 : I n t e r r u p t d i s a b l e d
1 : I n t e r r u p t e n a b l e d
s
1 6
]
A f t e r r e s e t
0
0
0
0
0
0RW
0RW
0
RW
RW
RW
RW
RW
RW
R—
Fig. 8.3.4 Interrupt Control Register 1
I n t e r r u p t C o n t r o l R e g i s t e r 2
b 7b 6 b 5b 4b 3 b 2b 1b 0
I n t e r r u p t c o n t r o l r e g i s t e r 2 ( I C O N 2 ) [ A d d r e s s 0 0 F F
BN
I N T 1 e x t e r n a l i n t e r r u p t
0
e n a b l e b i t ( I N 1 E )
D a t a s l i c e r i n t e r r u p t
1
e n a b l e b i t ( D S E )
S e r i a l I / O i n t e r r u p t
2
e n a b l e b i t ( S 1 E )
f ( X
3
e n a b l e b i t ( C K E )
I N T 2 e x t e r n a l i n t e r r u p t
4
e n a b l e b i t ( I N 2 E )
M u l t i - m a s t e r I2C - B U S
i n t e r f a c e i n t e r r u p t e n a b l e
b i t ( I I C E )
T i m e r 5 • 6 i n t e r r u p t
e n a b l e b i t ( T M 5 6 E )
T i m e r 5 • 6 i n t e r r u p t
s w i t c h b i t ( T M 5 6 C )
a m
eF
I N
) / 4 0 9 6 i n t e r r u p t
u n c t i o n
0 : I n t e r r u p t d i s a b l e d
1 : I n t e r r u p t e n a b l e d
0 : I n t e r r u p t d i s a b l e d
1 : I n t e r r u p t e n a b l e d
0 : I n t e r r u p t d i s a b l e d
1 : I n t e r r u p t e n a b l e d
0 : I n t e r r u p t d i s a b l e d
1 : I n t e r r u p t e n a b l e d
0 : I n t e r r u p t d i s a b l e d
1 : I n t e r r u p t e n a b l e d
0 : I n t e r r u p t d i s a b l e d
1 : I n t e r r u p t e n a b l e d
0 : I n t e r r u p t d i s a b l e d
1 : I n t e r r u p t e n a b l e d
0 : T i m e r 5
1 : T i m e r 6
s
1 6
]
A f t e r r e s e t
0
0
0
0
0
0RW
0RW
0RW
RW
RW
RW
RW
RW
RW
Fig. 8.3.5 Interrupt Control Register 2
Rev. 1.3
21
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
Interrupt Input Polarity Register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt input polarity register (RE) [Address 00DC
B Name Functions After reset R W
INT1 polarity switch bit
0
(INT1)
INT2 polarity switch bit
4
(INT2)
INT3 polarity switch bit
5
(INT3)
4
Nothing is assigned. These bits are write disable bits.
to
When these bits are read out, the values are “0.”
7
MITSUBISHI MICROCOMPUTERS
M37272E8SP/FP, M37272EFSP
and ON-SCREEN DISPLAY CONTROLLER
16
]
0
0 : Positive polarity
1 : Negative polarity
0 : Positive polarity
1 : Negative polarity
0 : Positive polarity
1 : Negative polarity
RW
0
RW
0
RW
0
R—
Fig. 8.3.6 Interrupt Input Polarity Register
22
Rev. 1.3
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
8.4 TIMERS
This microcomputer has 6 timers: timer 1, timer 2, timer 3, timer 4,
timer 5, and timer 6. All timers are 8-bit timers with the 8-bit timer
latch. The timer block diagram is shown in Figure 8.4.3.
All of the timers count down and their divide ratio is 1/(n+1), where n
is the value of timer latch. By writing a count value to the corresponding timer latch (addresses 00F016 to 00F316 : timers 1 to 4, addresses
00EE16 and 00EF16 : timers 5 and 6), the value is also set to a timer,
simultaneously.
The count value is decremented by 1. The timer interrupt request bit
is set to “1” by a timer overflow at the next count pulse, after the
count value reaches “0016”.
8.4.1 Timer 1
Timer 1 can select one of the following count sources:
• f(XIN)/16 or f(XCIN)/16
• f(XIN)/4096 or f(XCIN)/4096
• External clock from the TIM2 pin
The count source of timer 1 is selected by setting bits 5 and 0 of
timer mode register 1 (address 00F416). Either f(XIN) or f(XCIN) is
selected by bit 7 of the CPU mode register.
Timer 1 interrupt request occurs at timer 1 overflow.
8.4.2 Timer 2
Timer 2 can select one of the following count sources:
• f(XIN)/16 or f(XCIN)/16
• Timer 1 overflow signal
• External clock from the TIM2 pin
The count source of timer 2 is selected by setting bits 4 and 1 of
timer mode register 1 (address 00F416). Either f(XIN) or f(XCIN) is
selected by bit 7 of the CPU mode register. When timer 1 overflow
signal is a count source for the timer 2, the timer 1 functions as an 8bit prescaler.
Timer 2 interrupt request occurs at timer 2 overflow.
8.4.3 Timer 3
Timer 3 can select one of the following count sources:
• f(XIN)/16 or f(XCIN)/16
• f(XCIN)
• External clock from the TIM3 pin
The count source of timer 3 is selected by setting bit 0 of timer mode
register 2 (address 00F516) and bit 6 at address 00C716. Either f(XIN)
or f(XCIN) is selected by bit 7 of the CPU mode register.
Timer 3 interrupt request occurs at timer 3 overflow.
8.4.5 Timer 5
Timer 5 can select one of the following count sources:
• f(XIN)/16 or f(XCIN)/16
• Timer 2 overflow signal
• Timer 4 overflow signal
The count source of timer 3 is selected by setting bit 6 of timer mode
register 1 (address 00F416) and bit 7 of the timer mode register 2
(address 00F516). When overflow of timer 2 or 4 is a count source
for timer 5, either timer 2 or 4 functions as an 8-bit prescaler. Either
f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register.
Timer 5 interrupt request occurs at timer 5 overflow.
8.4.6 Timer 6
Timer 6 can select one of the following count sources:
• f(XIN)/16 or f(XCIN)/16
• Timer 5 overflow signal
The count source of timer 6 is selected by setting bit 7 of the timer
mode register 1 (address 00F416). Either f(XIN) or f(XCIN) is selected
by bit 7 of the CPU mode register. When timer 5 overflow signal is a
count source for timer 6, the timer 5 functions as an 8-bit prescaler.
Timer 6 interrupt request occurs at timer 6 overflow.
At reset, timers 3 and 4 are connected by hardware and “FF16” is
automatically set in timer 3; “0716” in timer 4. The f(XIN) ✽ /16 is selected as the timer 3 count source. The internal reset is released by
timer 4 overflow in this state and the internal clock is connected.
At execution of the STP instruction, timers 3 and 4 are connected by
hardware and “FF16” is automatically set in timer 3; “0716” in timer 4.
However, the f(XIN) ✽ /16 is not selected as the timer 3 count source.
So set both bit 0 of timer mode register 2 (address 00F516) and bit 6
at address 00C716 to “0” before the execution of the STP instruction
(f(XIN) ✽ /16 is selected as timer 3 count source). The internal STP
state is released by timer 4 overflow in this state and the internal
clock is connected.
As a result of the above procedure, the program can start under a
stable clock.
✽: When bit 7 of the CPU mode register (CM7) is “1,” f(XIN) becomes
f(XCIN).
The timer-related registers is shown in Figures 8.4.1 and 8.4.2.
8.4.4 Timer 4
Timer 4 can select one of the following count sources:
• f(XIN)/16 or f(XCIN)/16
• f(XIN)/2 or f(XCIN)/2
• f(XCIN)
The count source of timer 3 is selected by setting bits 1 and 4 of the
timer mode register 2 (address 00F516). Either f(XIN) or f(XCIN) is
selected by bit 7 of the CPU mode register. When timer 3 overflow
signal is a count source for the timer 4, the timer 3 functions as an 8bit prescaler.
Timer 4 interrupt request occurs at timer 4 overflow.
Rev. 1.3
23
Timer Mode Register 1
b7b6 b5b4b3 b2b1b0
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Timer mode register 1 (TM1) [Address 00F4
16]
Fig. 8.4.1 Timer Mode Register 1
Timer Mode Register 2
b7b6 b5b4b3 b2b1b0
B
0
1
2
3
4
Name Functions
Timer 1 count source
selection bit 1 (TM10)
Timer 2 count source
selection bit 1 (TM11)
Timer 1 count
stop bit (TM12)
Timer 2 count stop
bit (TM13)
Timer 2 count source
selection bit 2
(TM14)
5
Timer 1 count source
selection bit 2 (TM15)
6
Timer 5 count source
selection bit 2 (TM16)
7 Timer 6 internal count
source selection bit
0: f(X
IN)/16 or f(XCIN)/16 (See note)
1: Count source selected by bit 5 of TM1
0: Count source selected by bit 4 of TM1
1: External clock from TIM2 pin
0: Count start
1: Count stop
0: Count start
1: Count stop
IN)/16 or f(XCIN)/16 (See note)
0: f(X
1: Timer 1 overflow
0: f(X
IN)/4096 or f(XCIN)/4096 (See note)
1: External clock from TIM2 pin
0: Timer 2 overflow
1: Timer 4 overflow
IN)/16 or f(XCIN)/16 (See note)
1: Timer 5 overflow
After reset
(TM17)
Note: Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register.
Timer mode register 2 (TM2) [Address 00F5
16
]
0
0
0
0
0
0WR
0WR
0WR0: f(X
R
W
WR
WR
WR
WR
WR
Fig. 8.4.2 Timer Mode Register 2
B
0
1, 4
Name Functions
Timer 3 count source
selection bit (TM20)
Timer 4 count source
selection bits
(TM21, TM24)
Timer 3 count
2
stop bit (TM22)
Timer 4 count stop bit
3
(TM23)
Timer 5 count stop bit
5
(TM25)
Timer 6 count stop bit
6
(TM26)
Timer 5 count source
7
selection bit 1
(TM27)
Note: Either f(XIN) or f(X
16
(b6 at address 00C7
b0
IN
0 0 : f(X
0 1 : f(X
1 0 :
11 :
)/16 or f(X
CIN
)
External clock from TIM3 pin
)
CIN
)/16 (See note)
b4 b1
0 0 : Timer 3 overflow signal
0 1 : f(X
1 0 : f(X
1 1 : f(X
IN
)/16 or f(X
IN
)/2 or f(X
CIN
)
CIN
)/16 (See note)
CIN
)/2 (See note)
0: Count start
1: Count stop
0: Count start
1: Count stop
0: Count start
1: Count stop
0: Count start
1: Count stop
0: f(X
IN
)/16 or f(X
1: Count source selected by bit 6
of TM1
CIN
) is selected by bit 7 of the CPU mode register.
CIN
)/16 (See note)
After reset
0 RW
0RW
0
0
0
0
0
RW
RW
RW
RW
RW
RW
24
Rev. 1.3
X
CIN
XIN
TIM2
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Data bus
8
CM7
1/4096
1/2
TM15
1/8
TM10
TM12
TM14
TM11
TM13
Timer 1 latch (8)
8
Timer 1 (8)
Timer 2 latch (8)
8
Timer 2 (8)
Timer 1
interrupt request
8
8
Timer 2
interrupt request
8
TIM3
Selection gate: Connected to
black side at
reset
TM1 : Timer mode register 1
TM2 : Timer mode register 2
T3SC : Timer 3 count source
switch bit (address 00C7
CM : CPU mode register
TM21
16)
TM20
TM24
TM27
T3SC
TM22
TM21
TM23
TM25
TM16
Timer 3 latch (8)
8
Timer 3 (8)
Timer 4 latch (8)
8
Timer 4 (8)
Timer 5 latch (8)
8
Timer 5 (8)
8
FF16
8
8
0716
8
8
8
8
Reset
STP instruction
Timer 3
interrupt request
Timer 4
interrupt request
Timer 5
interrupt request
Notes 1: HIGH pulse width of external clock inputs TIM2 and TIM3 needs 4 machine cycles or more.
2: When the external clock source is selected, timers 1, 2, and 3 are counted at a rising edge of input signal.
3: In the stop mode or the wait mode, external clock inputs TIM2 and TIM3 cannot be used.
Fig. 8.4.3 Timer Block Diagram
Rev. 1.3
TM17
TM26
Timer 6 latch (8)
8
Timer 6 (8)
Timer 6
interrupt request
8
25
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
8.5 SERIAL I/O
This microcomputer has a built-in serial I/O which can either transmit
or receive 8-bit data serially in the clock synchronous mode.
The serial I/O block diagram is shown in Figure 8.5.1. The synchronous clock I/O pin (SCLK), and data output pin (SOUT) also function
as port P4, data input pin (SIN) also functions as port P20–P22.
Bit 3 of the serial I/O mode register (address 00EB16) selects whether
the synchronous clock is supplied internally or externally (from the
SCLK pin). When an internal clock is selected, bits 1 and 0 select
whether f(XIN) or f(XCIN) is divided by 8, 16, 32, or 64. T o use the S IN
pin for serial I/O, set the corresponding bit of the port P2 direction
register (address 00C516) to “0.”
X
CIN
1/2
X
IN
1/2
P20 Latch
S
CLK
SM3
P21 Latch
S
OUT
S
IN
SM3
SM6
CM7
1/2
Synchronous
SM5
circuit
Serial I/O counter (8)
: LSB
Serial I/O shift register (8)
SM2
S
MSB
The operation of the serial I/O is described below. The operation of
the serial I/O differs depending on the clock source; external clock or
internal clock.
Data bus
Frequency divider
1/2
1/81/4 1/16
SM1
SM0
Selection gate: Connect to
black side at
reset.
CM : CPU mode register
SM : Serial I/O mode register
Serial I/O
interrupt request
(See note)
8
Note : When the data is set in the serial I/O register (address 00EA
Fig. 8.5.1 Serial I/O Block Diagram
26
16
), the register functions as the serial I/O shift register.
Rev. 1.3
MITSUBISHI MICROCOMPUTERS
k
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Internal clock : The serial I/O counter is set to “7” during the write
cycle into the serial I/O register (address 00EA16), and the transfer
clock goes HIGH forcibly. At each falling edge of the transfer clock
after the write cycle, serial data is output from the SOUT pin. Transfer
direction can be selected by bit 5 of the serial I/O mode register. At
each rising edge of the transfer clock, data is input from the SIN pin
and data in the serial I/O register is shifted 1 bit.
After the transfer clock has counted 8 times, the serial I/O counter
becomes “0” and the transfer clock stops at HIGH. At this time the
interrupt request bit is set to “1.”
S y n c h r o n o u s c l o c
External clock : The an external clock is selected as the clock source,
the interrupt request is set to “1” after the transfer clock has been
counted 8 counts. However, transfer operation does not stop, so the
clock should be controlled externally. Use the external clock of 1 MHz
or less with a duty cycle of 50%.
The serial I/O timing is shown in Figure 8.5.2. When using an external clock for transfer, the external clock must be held at HIGH for
initializing the serial I/O counter. When switching between an internal clock and an external clock, do not switch during transfer. Also,
be sure to initialize the serial I/O counter after switching.
Notes 1: On programming, note that the serial I/O counter is set by writing to
the serial I/O register with the bit managing instructions, such as SEB
and CLB.
2:When an external clock is used as the synchronous clock, write trans-
mit data to the serial I/O register when the transfer clock input level is
HIGH.
T r a n s f e r c l o c k
S e r i a l I / O r e g i s t e r
w r i t e s i g n a l
S e r i a l I / O o u t p u t
S
O U T
S e r i a l I / O i n p u t
S
I N
N o t e : W h e n a n i n t e r n a l c l o c k i s s e l e c t e d , t h e S
Fig. 8.5.2 Serial I/O Timing (for LSB first)
D
0
D
1
D
2
D
3
D
4
D
O U T
p i n i s a t h i g h - i m p e d a n c e a f t e r t r a n s f e r i s c o m p l e t e d .
( N o t e )
5
D
6
D
7
I n t e r r u p t r e q u e s t b i t i s s e t t o “ 1 ”
Rev. 1.3
27
r
0
W
W
S e r i a l I / O M o d e R e g i s t e
b 7b 6 b 5b 4b 3 b 2b 1b 0
0
MITSUBISHI MICROCOMPUTERS
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
1 6
S e r i a l I / O m o d e r e g i s t e r ( S M ) [ A d d r e s s 0 0 E B
]
BN
0 , 1
a m
eF
I n t e r n a l s y n c h r o n o u s
c l o c k s e l e c t i o n b i t s
( S M 0 , S M 1 )
2
S y n c h r o n o u s c l o c k
s e l e c t i o n b i t ( S M 2 )
3
P o r t f u n c t i o n
s e l e c t i o n b i t ( S M 3 )
F i x t h i s b i t t o “ 0 . ”
4
T r a n s f e r d i r e c t i o n
5
s e l e c t i o n b i t ( S M 5 )
6
T r a n s f e r c l o c k i n p u t
p i n s e l e c t i o n b i t ( S M 6 )
F i x t h i s b i t t o “ 0 . ”
7
u n c t i o n
s
b 1 b 0
0 0 : f ( X
0 1 : f ( X
1 0 : f ( X
1 1 : f ( X
I N
) / 4 o r f ( X
I N
) / 1 6 o r f ( X
I N
) / 3 2 o r f ( X
I N
) / 6 4 o r f ( X
C I N
0 : E x t e r n a l c l o c k
1 : I n t e r n a l c l o c k
0 : P 20, P 2
1 : S
C L K
, S
1
O U T
0 : L S B f i r s t
1 : M S B f i r s t
0 : I n p u t s i g n a l f r o m S
1 :
I n p u t s i g n a l f r o m S
C I N
C I N
C I N
O U T
) / 4
) / 1 6
) / 3 2
) / 6 4
I N
p i n
p i n
A f t e r r e s e t
0
0
0
0
0
0
0R
RW
RW
RW
RW
R
RW
RW
Fig. 8.5.3 Serial I/O Mode Register
Rev. 1.3
28
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BSEL0
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
8.6 MULTI-MASTER I2C-BUS INTERFACE
The multi-master I2C-BUS interface is a serial communications circuit, conforming to the Philips I2C-BUS data transfer format. This
interface, offering both arbitration lost detection and a synchronous
functions, is useful for the multi-master serial communications.
Figure 8.6.1 shows a block diagram of the multi-master I2C-BUS interface and Table 8.6.1 shows multi-master I2C-BUS interface functions.
This multi-master I2C-BUS interface consists of the I2C address register, the I2C data shift register, the I2C clock control register, the I2C
control register, the I2C status register and other control circuits.
I2C address register (S0D)
b7 b0
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1SAD0 RBW
Table 8.6.1 Multi-master I2C-BUS Interface Functions
Item
Function
In conformity with Philips I2C-BUS
standard:
10-bit addressing format
Format
7-bit addressing format
High-speed clock mode
Standard clock mode
In conformity with Philips I2C-BUS
standard:
Master transmission
Communication mode
Master reception
Slave transmission
Slave reception
SCL clock frequency
16.1 kHz to 400 kHz (at φ = 4 MHz)
φ : System clock = f(XIN)/2
Note :W e are not responsible for any third party’s infringement of patent rights
or other rights attributable to the use of the control function (bits 6 and 7
2
of the I
C control register at address 00F916) for connections between
2
the I
C-BUS interface and ports (SCL1, SCL2, SDA1, SDA2).
Interrupt
generating
circuit
Interrupt
request signal
(IICIRQ)
Serial
data
(SDA)
Serial
clock
(SCL)
Noise
elimination
circuit
Noise
elimination
circuit
Data
control
circuit
AL
circuit
BB
circuit
Clock
control
circuit
Address comparator
b7
2
I C data shift register
S0
b7 b0
FAST
ACK
ACK
BIT
I2C clock control register (S2)
CCR4 CCR3 CCR2 CCR1 CCR0
MODE
Clock division
b0
Internal data bus
System clock
b7
MST TRX BB PIN
AL AAS AD0 LRB
2
I C status
register
(S1)
b7 b0
10BIT
ALS
SAD
I2C control register (S1D)
(φ)
BC2 BC1 BC0
ESO
Bit counter
b0
Fig. 8.6.1 Block Diagram of Multi-master I2C-BUS Interface
Rev. 1.3
29
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
C
B
s
f
C
f
C
e
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
8.6.1 I2C Data Shift Register
The I2C data shift register (S0 : address 00F616) is an 8-bit shift
register to store receive data and write transmit data.
When transmit data is written into this register, it is transferred to the
outside from bit 7 in synchronization with the SCL clock, and each
time one-bit data is output, the data of this register are shifted one bit
to the left. When data is received, it is input to this register from bit 0
in synchronization with the SCL clock, and each time one-bit data is
input, the data of this register are shifted one bit to the left.
The I2C data shift register is in a write enable status only when the
ESO bit of the I2C control register (address 00F916) is “1.” The bit
counter is reset by a write instruction to the I2C data shift register.
When both the ESO bit and the MST bit of the I2C status register
(address 00F816) are “1,” the SCL is output by a write instruction to
the I2C data shift register. Reading data from the I2C data shift register is always enabled regardless of the ESO bit value.
MITSUBISHI MICROCOMPUTERS
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and ON-SCREEN DISPLAY CONTROLLER
Note: To write data into the I2C data shift register after setting the MST bit to
“0” (slave mode), keep an interval of 8 machine cycles or more.
D a t a S h i f t R e g i s t e
2
I
b 7b 6b 5b 4b 3b 2b 1b 0
r
d a t a s h i f t r e g i s t e r 1 ( S 0 ) [ A d d r e s s 0 0 F
2
I
N a m
0
D 0 t o D 7RW
t o
7
d a t a s h i f t r e g i s t e r a f t e r s e t t i n g t h e M S T b i t t
N o t e :
T o w r i t e d a t a i n t o t h e I
“ 0 ” ( s l a v e m o d e ) , k e e p a n i n t e r v a l o f 8 m a c h i n e c y c l e s o r m o r e .
t r e g i s t e r t o s t o r e
T h i s i s a n 8 - b i t s h i
r e c e i v e d a t a a n d w r i t e t r a n s m i t d a t a .
Fig. 8.6.2 Data Shift Register
2
F u n c t i o n
1 6
]
6
t e r r e s e
I n d e t e r m i n a t e
A
tRW
o
Rev. 1.3
30
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