SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
and ON-SCREEN DISPLAY CONTROLLER
DESCRIPTION
The M37207MF-XXXSP/FP and M37207M8-XXXSP are single-chip
microcomputers designed with CMOS silicon gate technology. It is
housed in a 64-pin shrink plastic molded DIP or a 80-pin plastic molded
QFP.
In addition to their simple instruction sets, the ROM, RAM and I/O
addresses are placed on the same memory map to enable easy programming.
The M37207MF-XXXSP/FP has a PWM function and an OSD function, so it is useful for a channel selection system for TV. The features of the M37207EFSP/FP are similar to those of the M37207MFXXXSP/FP except that these chips have a built-in PROM which can
be written electrically. The difference between M37207MF-XXXSP/
FP and M37207M8-XXXSP are the ROM size, RAM size, ROM size
for display and kinds of character. Accordingly, the following descriptions will be for the M37207MF-XXXSP/FP unless otherwise noted.
FEATURES
Number of basic instructions .................................................... 71
4 kinds
Maximum 15 kinds (R, G, B, I); can be specified by the character
64 levels (horizontal) ✕ 128 levels (vertical)
6
M37207MF-XXXSP/FP, M37207M8-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
PIN DESCRIPTION
PinFunctions
VCC, VSS
Name
Power source
Input/
Output
Apply voltage of 5 V ± 10 % (typical) to VCC and AVCC, and 0 V to VSS.
MITSUBISHI MICROCOMPUTERS
M37207EFSP/FP
and ON-SCREEN DISPLAY CONTROLLER
CNVSS
______
RESET
XIN
XOUT
P00–P07
P10–P17
P20–P27
P30, P31
P32/TIM2/
AD6,
P33/TIM3,
P34/INT1,
P35/AD1,
P36/INT2/
AD2
P40/SOUT2/
SDA3/XCIN,
P41/SCLK2/
SCL3/
XCOUT, P42/
SIN2/SDA2/
AD8,
_____
P43/SRDY2/
SCL2/AD7,
P44/SOUT1/
SDA1,
P45/SCLK1/
SCL1,
P46/SIN1/
PWM9,
_____
P47/SRDY1/
PWM8
CNVSS
Reset input
Clock input
Clock output
I/O port P0
I/O port P1
I/O port P2
I/O port P3
I/O port P3
Analog input
External clock
input
External interrupt
input
I/O port P4
Serial I/O data
input/output
Serial I/O synchronous clock input/
output
Serial I/O receive
enable signal output
Multi-master I2CBUS interface
Sub-clock input
Sub-clock output
Analog input
PWM output
Input
Input
Output
I/O
I/O
I/O
I/O
I/O
Input
Input
Input
I/O
I/O
I/O
Output
I/O
Input
Output
Input
Output
Connected to VSS.
To enter the reset state, the reset input pin must be kept at a “L” for 2 ms or more (under
normal VCC conditions).
If more time is needed for the quartz-crystal oscillator to stabilize, this “L” condition should
be maintained for the required time.
This chip has an internal clock generating circuit. To control generating frequency, an
external ceramic resonator or a quartz-crystal oscillator is connected between pins XIN and
XOUT. If an external clock is used, the clock source should be connected to the XIN pin and
the XOUT pin should be left open.
Port P0 is an 8-bit I/O port with direction register allowing each I/O bit to be individually
programmed as input or output. At reset, this port is set to input mode. The output structure
is CMOS output. See notes at end of table for full details of port P0 functions.
Port P1 is an 8-bit I/O port and has basically the same functions as port P0. The output
structure is CMOS output.
Port P2 is an 8-bit I/O port and has basically the same functions as port P0. The output
structure is CMOS output.
Ports P30, P31 are 2-bit I/O ports and have basically the same functions as port P0. The
output structure is CMOS output.
Ports P32–P36 are 5-bit I/O ports and have basically the same functions as port P0. The
output structure is N-channel open-drain output.
Pins P32, P35, P36 are also used as analog input pins AD6, AD1 and AD2 respectively.
Pins P32, P33 are also used as external clock input pins TIM2, TIM3 respectively.
Pins P34, P36 are also used as external interrupt input pins INT1, INT2.
Port P4 is an 8-bit I/O port and has basically the same functions as port P0. The output
structure is N-channel open-drain output.
Pins P40, P42, P44, P46 are also used as serial I/O data input/output pins SOUT2, SIN2,
SOUT1, SIN1 respectively. The output structure is N-channel open-drain output.
Pins P41, P45 are also used as serial I/O synchronous clock input/output pins SCLK2, SCLK1
respectively.
Pins P43, P47 are also used as serial I/O receive enable signal output pins SRDY2, SRDY1
respectively. The output structure is N-channel open-drain output.
Pins P40–P45 are also used as SDA3, SCL3, SDA2, SCL2, SDA1, SCL1 respectively
when multi-master I2C-BUS interface is used. The output structure is N-channel opendrain output.
Pin P40 is also used as sub-clock input pin XCIN.
Pin P41 is also used as sub-clock output pin XCOUT. The output structure is N-channel
open-drain output.
Pins P42, P43 are also used as analog input pins AD8, AD7 respectively.
Pins P46, P47 are also used as PWM output pins PWM9, PWM8 respectively. The output
structure is N-channel open-drain output.
_____ _____
7
PIN DESCRIPTION (continued)
MITSUBISHI MICROCOMPUTERS
M37207MF-XXXSP/FP, M37207M8-XXXSP
M37207EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
and ON-SCREEN DISPLAY CONTROLLER
PinName
R/P52,
G/P53,
B/P54,
I/P55/TIM1
OVERFLOW,
OUT/P56
P60/PWM–
P67/PWM7
OSC1/P70/
AD4,
OSC2/P71/
AD5
HSYNC
VSYNC
f
D-A/AD3
Note : As shown in the memory map (Figure 5), port P0 is accessed as a memory at address 00C016 of zero page. Port P0 has the port P0
direction register (address 00C116 of zero page) which can be used to program each bit as an input (“0”) or an output (“1”). The pins
programmed as “1” in the direction register are output pins. When pins are programmed as “0,” they are input pins. When pins are
programmed as output pins, the output data are written into the port latch and then output. When data is read from the output pins, the
output pin level is not read but the data of the port latch is read. This allows a previously-output value to be read correctly even if the
output “L” voltage has risen, for example, because a light emitting diode was directly driven. The input pins float, so the values of the pins
can be read. When data is written into the input pin, it is written only into the port latch, while the pin remains in the floating state.
Output port
P5
CRT output
Timer 1 overflow
signal output
I/O port P6
PWM output
Input port P7
Clock input
for CRT
display
Clock output
for CRT
display
Analog input
HSYNC input
VSYNC input
Timing
output
DA output
Analog input
Input/
Output
Output
Output
Output
I/O
Output
Input
Input
Output
Input
Input
Input
Output
Output
Input
Ports P52–P56 are 5-bit output ports. The output structure is CMOS output.
Pins P52–P56 are also used as CRT output pins R, G, B, I, OUT respectively. The output structure
is CMOS output.
Pin P55 is also used as timer 1 overflow signal output pin TIM1 OVERFLOW. The output structure is
CMOS output.
Port P6 is an 8-bit I/O port and has basically the same functions as port P0. The output structure is
N-channel open-drain output.
Pins P60–P67 are also used as PWM output pins PWM0–PWM7. The output structure is CMOS
output.
Ports P70, P71 are 2-bit input port.
Pin P70 is also used as CRT display clock input pin OSC1.
Pin P71 is also used as CRT display clock output pin OSC2. The output structure is CMOS output.
Pins P70, P71 are also used as analog input pins AD4, AD5 respectively.
This is a horizontal synchronous signal input for CRT display.
This is a vertical synchronous signal input for CRT display.
This is a timing output pin. This pin has reset-out output function. The output structure is CMOS
output.
This is an output pin for 14-bit PWM.
The D-A pin is also used as analog input pin AD3.
Functions
8
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
and ON-SCREEN DISPLAY CONTROLLER
Schmidt input
Internal circuit
R, G, B, I, OUT,
P52–P55, φ
Internal circuit
HSYNC, VSYNC
CMOS output
P52–P55, φ
Note : Each port is also used as follows:
P52 : R
P53 : G
P54 : B
P55 : I/TIM1
P56 : OUT
Fig. 2. I/O Pin Block Diagram (2)
10
MITSUBISHI MICROCOMPUTERS
M37207MF-XXXSP/FP, M37207M8-XXXSP
M37207EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
and ON-SCREEN DISPLAY CONTROLLER
FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)
This microcomputer uses the standard 740 Family instruction set.
Refer to the table of 740 Family addressing modes and machine
instructions or the SERIES 740 <Software> User’s Manual for details on the instruction set.
Machine-resident 740 Family instructions are as follows:
The FST, SLW instruction cannot be used.
The MUL, DIV, WIT and STP instructions can be used.
CPU Mode Register
b7b6 b5b4b3 b2b1b0
1
00
CPU mode register (CPUM) (CM) [Address 00FB16]
B
0, 1
NameFunctions
Processor mode bits
(CM0, CM1)
Stack page selection
2
bit (CM2) (See note 1)
CPU Mode Register
The CPU mode register contains the stack page selection bit and
internal system clock selection bit. The CPU mode register is allocated at address 00FB16.
After reset
b1 b0
0 0: Single-chip mode
0 1:
1 0: Not available
1 1:
0: 0 page
1: 1 page
RW
RW
0
RW
1
Fig. 3. CPU Mode Register
3
Fix these bits to “1.”
Internal system clock
41
output selection bit
(CM4) (See note 2)
X
COUT
51
drivability
selection bit (CM5)
Main Clock (X
60
IN–XOUT
stop bit
(CM6)
Internal system clock
70
selection bit
(CM7)
0: Output is stopped
1: Internal system
clock
φ
output
0: LOW drive
1: HIGH drive
)
0: Oscillating
1: Stopped
0: X
IN–XOUT
selected
(high-speed mode)
1: X
CIN–XCOUT
selected
RW
1
RW
RW
RW
RW
(high-speed mode)
Notes 1: This bit is set to “1” after the reset release.
φ
2: The internal system clock
stops at HIGH.
11
MITSUBISHI MICROCOMPUTERS
M37207MF-XXXSP/FP, M37207M8-XXXSP
M37207EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
and ON-SCREEN DISPLAY CONTROLLER
MEMORY
Special Function Register (SFR) Area
The special function register (SFR) area in the zero page contains
control registers such as I/O ports and timers.
RAM
RAM is used for data storage and for stack area of subroutine calls
and interrupts.
ROM
ROM is used for storing user programs as well as the interrupt vector
area.
RAM for Display
RAM for display is used for specifying the character codes and colors to display.
ROM for Display
ROM for display is used for storing character data.
000016
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
Zero Page
The 256 bytes from addresses 000016 to 00FF16 are called the zero
page area. The internal RAM and the special function registers (SFR)
are allocated to this area.
The zero page addressing mode can be used to specify memory and
register addresses in the zero page area. Access to this area with
only 2 bytes is possible in the zero page addressing mode.
Special Page
The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to
specify memory addresses in the special page area. Access to this
area with only 2 bytes is possible in the special page addressing
mode.
ROM Correction Memory (RAM)
This is used as the program area for ROM correction.
10000
16
RAM
(960 bytes)
for M37207MF
ROM
(62 K bytes)
for M37207MF
RAM
(512 bytes)
for M37207M8
RAM
for display
(144 bytes)
(See note)
ROM
(32 K bytes)
for M37207M8
00C016
00FF16
01FF16
020416
021B16
02C016
02FF16
030016
033F16
04FF16
060016
06D716
080016
800016
FF0016
FFDE16
FFFF
SFR area
Not used
2 page register
Not used
Not used
Not used
Interrupt vector area
16
Zero page
ROM
for display
(12 K bytes)
for M37207MF
ROM correction memory (64 bytes)
Block 1: addresses 02C0
Block 2: addresses 02E016 to 02FF16
Special page
for display
(8 K bytes)
for M37207M8
Note: Refer to Table 9. Contents of CRT display RAM.
ROM
11FFF16
12FFF16
16 to 02DF16
Not used
1FFFF16
Fig. 4. Memory Map
12
M37207MF-XXXSP/FP, M37207M8-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
■SFR Area (addresses C016 to DF16)
<Bit allocation>
:
Name
:
: No function bit
: Fix this bit to “0”
0
(do not write “1”)
: Fix this bit to “1”
1
(do not write “0”)
Function bit
MITSUBISHI MICROCOMPUTERS
M37207EFSP/FP
and ON-SCREEN DISPLAY CONTROLLER
<State immediately after reset>
: “0” immediately after reset
0
1
: “1” immediately after reset
: Undefined immediately
?
after reset
Address
Port P0 (P0)
C0
16
Port P0 direction register (D0)
C1
16
Port P1 (P1)
C2
16
Port P1 direction register (D1)
C3
16
Port P2 (P2)
C4
16
Port P2 direction register (D2)
C5
16
Port P3 (P3)
C6
16
Port P3 direction register (D3)
C7
16
C8
16
Port P4 (P4)
Port P4 direction register (D4)
C9
16
Port P5 (P5)
CA
16
Port P5 control register (D5)
CB
16
CC
16
Port P6 (P6)
Port P6 direction register (D6)
CD
16
DA-H register (DA-H)
CE
16
DA-L register (DA-L)
CF
16
PWM0 register (PWM0)
D0
16
PWM1 register (PWM1)
D1
16
PWM2 register (PWM2)
D2
16
PWM3 register (PWM3)
D3
16
PWM4 register (PWM4)
D4
16
PWM output control register 1 (PW)
D5
16
PWM output control register 2 (PN)
D6
16
Interrupt interval determination register (??)
D7
16
Interrupt interval determination control register (RE)
D8
16
D9
DA
DB
DC
DD
DE
DF
2
16
C data shift register (S0)
I
16
I2C address register (S0D)
16
I2C status register (S1)
16
I2C control register (S1D)
16
I2C clock control register (S2)
16
Serial I/O mode register (SM)
16
Serial I/O regsiter (SIO)
Register
b7b0
ACK
Bit allocationState immediately after reset
PW0PW1PW2PW3PW4PW5PW6PW7
PN2PN3PN4
PN1 PN0
RE1RE2RE3RE4RE5RE0
D1D2D3D4D5D6D7D0
SAD0SAD1SAD2SAD3SAD4SAD5SAD6
RBW
LRBAD0AASALPINBBTRXMST
BC0BC1BC2ESOALS
CCR0CCR1CCR2CCR3CCR4
SM0SM1SM2SM3SM5SM6
BSEL0BSEL1
ACK
BIT
10BIT
SAD
FAST
MODE
0
b7b0
?
16
00
?
16
00
?
16
00
??0
00
16
?????
?
?
0
?
00
????
16
?
?
?
00
16
?
00
??????
?
?
?
?
?
16
00
16
00
?
00
16
?
00
16
0000100?
00
16
00
16
00
16
?
Fig. 5. Memory Map of Special Function Register (SFR)
13
■
SFR Area (addresses E0
MITSUBISHI MICROCOMPUTERS
M37207MF-XXXSP/FP, M37207M8-XXXSP
M37207EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
Fig. 6. Memory Map of Special Function Register (SFR)
14
M37207MF-XXXSP/FP, M37207M8-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
■SFR Area (addresses 20416 to 21B16)
MITSUBISHI MICROCOMPUTERS
M37207EFSP/FP
and ON-SCREEN DISPLAY CONTROLLER
Address
16
204
205
16
206
16
207
16
208
16
209
16
20A
16
20B
16
20C
16
20D
16
20E
16
20F
16
210
16
211
16
212
16
213
16
214
16
215
16
216
16
217
16
218
16
219
16
21A
16
21B
16
<Bit allocation>
Name
0
1
Register
b7
Timer 5 (T5)
Timer 6 (T6)
Port control register (P7D)
Serial I/O control register (SIC)
CRT control register 2 (CBR)
CRT clock selection register (OP)
A-D control register (ADC)
Timer mode register (TMR3)
ROM correction address 1 (high-order)
ROM correction address 1 (low-order)
ROM correction address 2 (high-order)
ROM correction address 2 (low-order)
ROM correction enable register (RCR)
0
<State immediately after reset>
: “0” immediately after reset
b0
P7D0
SIC0SIC1SIC2SIC3SIC4SIC5SIC8SIC7
CBR0CBR1
ADC0ADC1ADC2ADC3ADC4ADC5
TMR30
0
: “1” immediately after reset
1
: Undefined immediately
?
after reset
b7
00
16
00
16
0000
00
16
00
16
00
16
00??
00
16
:
Function bit
:
: No function bit
: Fix this bit to “0”
(do not write “1”)
: Fix this bit to “1”
(do not write “0”)
Bit allocationState immediately after reset
P7D1P7D2P7D4
OP1OP0
?
?
?
?
?
?
?
?
?
?
?
00
16
00
16
00
16
00
16
0000
RC1RC0
????
00
??
b0
??
??
00
Fig. 7. Memory Map of 2 Page Register
15
MITSUBISHI MICROCOMPUTERS
M37207MF-XXXSP/FP, M37207M8-XXXSP
M37207EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
and ON-SCREEN DISPLAY CONTROLLER
<Bit allocation>
:
Function bit
Name
:
: No function bit
: Fix this bit to “0”
0
(do not write “1”)
: Fix this bit to “1”
1
(do not write “0”)
Register
b7
Processor status register (PS)
Program counter (PCH)
Program counter (PCL)
Fig. 8. Internal State of Processor Status Register and Program Counter at Reset
Bit allocationState immediately after reset
IZCDBTVN???????
<State immediately after reset>
: “0” immediately after reset
0
1
: “1” immediately after reset
: Undefined immediately
?
after reset
b0
b7
Contents of address FFFF
Contents of address FFFE16
b0
1
16
16
MITSUBISHI MICROCOMPUTERS
M37207MF-XXXSP/FP, M37207M8-XXXSP
M37207EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
and ON-SCREEN DISPLAY CONTROLLER
INTERRUPTS
Interrupts can be caused by 15 different sources consisting of 3 external, 10 internal, 1 software, and reset. Interrupts are vectored interrupts with priorities as shown in Table 1. Reset is also included in
the table because its operation is similar to an interrupt.
When an interrupt is accepted,
(1) The contents of the program counter and processor status
register are automatically stored into the stack.
(2) The interrupt disable flag I is set to “1” and the corresponding
interrupt request bit is set to “0.”
(3) The jump destination address stored in the vector address enters
the program counter.
Other interrupts are disabled when the interrupt disable flag is set to
“1.”
All interrupts except the BRK instruction interrupt have an interrupt
request bit and an interrupt enable bit. The interrupt request bits are
in interrupt request registers 1 and 2 and the interrupt enable bits are
in interrupt control registers 1 and 2. Figures 10 to 13 show the interrupt-related registers.
Interrupts other than the BRK instruction interrupt and reset are accepted when the interrupt enable bit is “1,” interrupt request bit is “1,”
and the interrupt disable flag is “0.” The interrupt request bit can be
set to “0” by a program, but not set to “1.” The interrupt enable bit can
be set to “0” and “1” by a program.
Reset is treated as a non-maskable interrupt with the highest priority.
Figure 9 shows interrupt control.
Interrupt Causes
(1) VSYNC and CRT interrupts
The VSYNC interrupt is an interrupt request synchronized with
the vertical sync signal.
The CRT interrupt occurs after character block display to the CRT
is completed.
(2) INT1, INT2 interrupts
With an external interrupt input, the system detects that the level
of a pin changes from “L” to “H” or from “H” to “L,” and generates
an interrupt request. The input active edge can be selected by
bits 3 and 4 of the interrupt interval determination control register
(address 00D816) : when this bit is “0,” a change from “L” to “H” is
detected; when it is “1,” a change from “H” to “L” is detected.
Note that all bits are cleared to “0” at reset.
(3) Timer 1, 2, 3 and 4 interrupts
An interrupt is generated by an overflow of timer 1, 2, 3 or 4.
(4) Serial I/O interrupt
This is an interrupt request from the clock synchronous serial
I/O function.
Source switch by software (See note)
Non-maskable (software interrupt)
17
M37207MF-XXXSP/FP, M37207M8-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
(5) f(XIN)/4096 interrupt
This interrupt occurs regularly with a f(XIN)/4096 period. Set bit 0
of the PWM output control register 1 to “0.”
(6) Multi-master I2C-BUS interface interrupt
This is an interrupt request related to the multi-master I2C-BUS
interface.
(7) Timer 5 · 6 interrupt
An interrupt is generated by an overflow of timer 5 or 6. Their
priorities are same, and can be switched by software.
(8) BRK instruction interrupt
This software interrupt has the least significant priority. It does
not have a corresponding interrupt enable bit, and it is not affected by the interrupt disable flag I (non-maskable).
Interrupt control register 1 (ICON1) [Address 00FE
MITSUBISHI MICROCOMPUTERS
M37207MF-XXXSP/FP, M37207M8-XXXSP
M37207EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
and ON-SCREEN DISPLAY CONTROLLER
16
]
Fig. 12. Interrupt Control Register 1
BNameFunctions
Timer 1 interrupt
0
enable bit (TM1E)
Timer 2 interrupt
1
enable bit (TM2E)
Timer 3 interrupt
2
enable bit (TM3E)
Timer 4 interrupt
3
enable bit (TM4E)
CRT interrupt enable
4
bit (CRTE)
SYNC
interrupt enable
V
5
bit (VSCE)
6
Multi-master I
interface interrupt
enable bit (IICE)
7
Nothing is assigned. This bit is a write disable
bit. When this bit is read out, the value is “0.”
2
C-BUS
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
After reset
0
0
0
0
0
0RW
0
0
RW
RW
RW
RW
RW
RW
R
W
—
R
Interrupt Control Register 2
b7b6 b5b4b3 b2b1b0
0
Fig. 13. Interrupt Control Register 2
0
Interrupt control register 2 (ICON2) [Address 00FF
BNameFunctions
INT1 interrupt
0
enable bit (IT1E)
INT2 interrupt enable
1
bit (IT2E)
Serial I/O interrupt
2
enable bit (SIE)
Fix these bits to “0.”
3, 6
4
f(X
IN
)/4096 interrupt
enable bit (MSE)
5
Timer 5 • 6 interrupt
enable bit (TM56E)
7
Timer 5 • 6 interrupt
switch bit (TM56C)
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Timer 5
1 : Timer 6
16
]
After reset
0
0
0
0
0RW
0RW
0RW
RW
RW
RW
RW
RW
20
MITSUBISHI MICROCOMPUTERS
M37207MF-XXXSP/FP, M37207M8-XXXSP
M37207EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
and ON-SCREEN DISPLAY CONTROLLER
TIMERS
The M37267M6-XXXSP has 6 timers: timer 1, timer 2, timer 3, timer
4, timer 5 and timer 6. All timers are 8-bit timers with the 8-bit timer
latch. The timer block diagram is shown in Figure 17 .
0 .
All of the timers count down and their divide ratio is 1/(n+1), where n
is the value of timer latch. By writing a count value to the corresponding timer latch (addresses 00F016 to 00F316 : timers 1 to 4, addresses
020C16 and 020D16 : timers 5 and 6), the value is also set to a timer,
simultaneously.
The count value is decremented by 1. The timer interrupt request bit
is set to “1” by a timer overflow at the next count pulse after the count
value reaches “0016.”
(1) Timer 1
Timer 1 can select one of the following count sources:
f(XIN)/16 or f(XCIN)/16
•
f(XIN)/4096 or f(XCIN)/4096
•
f(XCIN)
•
External clock from the TIM2 pin
•
The count source of timer 1 is selected by setting bits 5 and 0 of
timer mode register 1 (address 00F416). Either f(XIN) or f(XCIN) is
selected by bit 7 of the CPU mode register.
Timer 1 interrupt request occurs at timer 1 overflow.
(2) Timer 2
Timer 2 can select one of the following count sources:
f(XIN)/16 or f(XCIN)/16
•
Timer 1 overflow signal
•
External clock from the TIM2 pin
•
The count source of timer 2 is selected by setting bits 4 and 1 of
timer mode register 1 (address 00F416). Either f(XIN) or f(XCIN) is
selected by bit 7 of the CPU mode register. When timer 1 overflow
signal is a count source for timer 2, timer 1 functions as an 8-bit
prescaler.
Timer 2 interrupt request occurs at timer 2 overflow.
(3) Timer 3
Timer 3 can select one of the following count sources:
f(XIN)/16 or f(XCIN)/16
•
External clock from the TIM3 pin
•
The count source of timer 3 is selected by setting bit 0 of timer mode
register 2 (address 00F516). Either f(XIN) or f(XCIN) is selected by bit
7 of the CPU mode register.
Timer 3 interrupt request occurs at timer 3 overflow.
(5) Timer 5
Timer 5 can select one of the following count sources:
f(XIN)/16 or f(XCIN)/16
•
f(XCIN)
•
Timer 4 overflow signal
•
The count source of timer 3 is selected by setting bit 6 of timer mode
register 1 (address 00F416) and bit 7 of timer mode register 2 (address 00F516). Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU
mode register.
Timer 5 interrupt request occurs at timer 5 overflow.
(6) Timer 6
Timer 6 can select one of the following count sources:
f(XIN)/16 or f(XCIN)/16
•
Timer 5 overflow signal
•
The count source of timer 6 is selected by setting bit 7 of timer mode
register 1 (address 00F416). Either f(XIN) or f(XCIN) is selected by bit
7 of the CPU mode register. When timer 5 overflow signal is a count
source for timer 6, timer 5 functions as an 8-bit prescaler.
Timer 6 interrupt request occurs at timer 6 overflow.
At reset, timers 3 and 4 are connected by hardware and “FF16” is
automatically set in timer 3; “0716” in timer 4. The f(XIN) ✽ /16 is selected as the timer 3 count source. The internal reset is released by
timer 4 overflow in this state and the internal clock is connected.
At execution of the STP instruction, timers 3 and 4 are connected by
hardware and “FF16” is automatically set in timer 3; “0716” in timer 4.
However, the f(XIN) ✽ /16 is not selected as the timer 3 count source.
So set bit 0 of timer mode register 2 (address 00F516) to “0” before
execution of the STP instruction (f(XIN) ✽ /16 is selected as
timer 3 count source). The internal STP state is released by timer 4
overflow in this state and the internal clock is connected.
As a result of the above procedure, the program can start under a
stable clock.
✽ : When bit 7 of the CPU mode register (CM7 ) is “1,” f(XIN) be-
comes f(XCIN).
The timer-related registers is shown in Figures 14 to 16.
(4) Timer 4
Timer 4 can select one of the following count sources:
f(XIN)/16 or f(XCIN)/16
•
f(XIN)/2 or f(XCIN)/2
•
Timer 3 overflow signal
•
The count source of timer 3 is selected by setting bits 1 and 4 of
timer mode register 2 (address 00F516). Either f(XIN) or f(XCIN) is
selected by bit 7 of the CPU mode register. When timer 3 overflow
signal is a count source for timer 4, the timer 3 functions as an 8-bit
prescaler.
Timer 4 interrupt request occurs at timer 4 overflow.
21
Timer Mode Register 1
b7b6 b5b4b3b2b1b0
MITSUBISHI MICROCOMPUTERS
M37207MF-XXXSP/FP, M37207M8-XXXSP
M37207EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
and ON-SCREEN DISPLAY CONTROLLER
Timer mode register 1 (TMR1) [Address 00F4
16
]
Fig. 14. Timer Mode Register 1
Timer Mode Register 2
b7b6 b5b4b3b2b1b0
B
0
NameFunctions
Timer 1 count source
selection bit 1
(TMR10, TMR15)
b5 b0
0 0: f(XIN)/16 or f(X
0 1: f(X
1 0: f(Xc
IN
)/4096 or f(X
IN
)
1 1: External clock from TIM2 pin
Count source selected by bit 4 of TM1
1
Timer 2 count source
selection bit 1
0:
1:
External clock from TIM2 pin
(TMR11)
Timer 1 count
2
stop bit (TMR12)
Timer 2 count stop
3
bit (TMR13)
4
Timer 2 count source
selection bit 2
0: Count start
1: Count stop
0: Count start
1: Count stop
0: f(XIN)/16 or f(X
1: Timer 1 overflow
(TMR14)
6
Timer 5 count source
selection bit 2 (TMR16)
7 Timer 6 internal count
source selection bit
0: Timer 2 overflow
1: Timer 4 overflow
0: f(XIN)/16 or f(X
1: Timer 5 overflow
(TMR17)
Note: Either f(XIN) or f(X
CIN
) is selected by bit 7 of the CPU mode register.
Timer mode register 2 (TMR2) [Address 00F5
CIN
)/16 (See note)
CIN
)/4096 (See note)
CIN
)/16 (See note)
CIN
)/16 (See note)
16
]
After reset
0
0
0
0
0
0WR
0WR
R
W
WR
WR
WR
WR
WR
Fig. 15. Timer Mode Register 2
B
0
NameFunctions
Timer 3 count source
selection bit (TMR20)
1 Timer 4 count source
selection bit 2
(TMR21)
Timer 3 count
2
stop bit (TMR22)
Timer 4 count stop bit
3
(TMR23)
4
Timer 4 count source
selection bit 1
(TMR24)
Timer 5 count stop bit
5
(TMR25)
Timer 6 count stop bit
6
(TMR26)
Timer 5 count source
7
selection bit 1
(TMR27)
Note: Either f(XIN) or f(X
After reset
0 : f(X
IN
)/16 or f(X
CIN
)/16 (See note)
1 : External clock from TIM3 pin
0 : Timer 3 overflow signal
1 : f(X
IN
)/16 or f(X
CIN
)/16 (See note)
0: Count start
1: Count stop
0: Count start
1: Count stop
0: Count source selected by bit 1
of TMR2
1 : f(X
IN
)/2 or f(X
CIN
)/2 (See note)
0: Count start
1: Count stop
0: Count start
1: Count stop
0: Count source selected by bit 0
of TMR3
1: Count source selected by bit 6
of TMR1
CIN
) is selected by bit 7 of the CPU mode register.
RW
0RW
0RW
0
RW
0
RW
0RW
0
RW
0
RW
0
RW
22
Timer Mode Register 3
b7b6 b5b4b3 b2b1b0
M37207MF-XXXSP/FP, M37207M8-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
Timer mode register 3 (TMR3) [Address 020B
MITSUBISHI MICROCOMPUTERS
M37207EFSP/FP
and ON-SCREEN DISPLAY CONTROLLER
16
]
Fig. 16. Timer Mode Register 3
B
0
Timer 5 count source
selection bit 3
(TMR30)
1
Nothing is assigned. These bits are write disable bits.
to
When these bits are read out, the values are “0.”
7
Note: Either f(XIN) or f(X
NameFunctions
0 : f(XIN)/16 or f(X
1 : f(X
CIN
CIN
) is selected by bit 7 of the CPU mode register.
CIN
)
)/16 (See note)
After reset
RW
0RW
0R—
23
X
CIN
X
IN
TIM2
TIM3
CM
7
1/4096
1/2
MITSUBISHI MICROCOMPUTERS
M37207MF-XXXSP/FP, M37207M8-XXXSP
M37207EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
Notes 1: HIGH pulse width of external clock inputs TIM2 and TIM3 needs 4 machine cycles or more.
2: When the external clock source is selected, timers 1, 2, and 3 are counted at a rising edge of input signal.
3: In the stop mode or the wait mode, external clock inputs TIM2 and TIM3 cannot be used.
Timer 4
interrupt request
Timer 5
interrupt request
Timer 6
interrupt request
Fig. 17. Timer Block Diagram
24
MITSUBISHI MICROCOMPUTERS
M37207MF-XXXSP/FP, M37207M8-XXXSP
M37207EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
and ON-SCREEN DISPLAY CONTROLLER
SERIAL I/O
This microcomputer has a built-in serial I/O which can either transmit
or receive 8-bit data serially in clock synchronous mode.
The serial I/O block diagram is shown in Figure 18. The synchronous
clock I/O pin (SCLK), and data I/O pins (SOUT, SIN), receive enable
signal output pin (SRDY) also function as port P4.
Bit 2 of the serial I/O mode register (address 00DE16) selects whether
the synchronous clock is supplied internally or externally (from the
pins SCLK1, SCLK2). When an internal clock is selected, bits 1 and 0
select whether f(XIN) or f(XCIN) is divided by 8, 16, 32, or 64. To use
pins for serial I/O, set the corresponding bits of the port P4 direction
register (address 00C916) to “0.”
S
S
S
S
S
X
CIN
X
RDY2
CLK2
OUT2
IN2
S
RDY1
CLK1
IN
____
P43 latch
SM4
P41 latch
SM3
P40 latch
SM3
SM6
0
latch
P4
P47 latch
SIC7
P45 latch
SIC5
CM7
SCL2 CSIO
SM6
SCL3
SM7
SDA3
SM7
SDA2
PWM8
SIC3
SCL1
SIC4
1/2
CSIO
CSIO
Synchronous
circuit
CSIO
1/2
SM5
Serial I/O shift register (8)
CM : CPU mode register
SM : Serial I/O mode register
SIC : Serial I/O control register
CSIO : Bit 1 of serial I/O control register
The operation of the serial I/O is described below. The operation
differs depending on the clock source; external clock or internal clock.
Frequency divider
1/2
SM2
S
Serial I/O counter (8)
: LSBMSB
1/81/41/16
SM
SM
(Note)
(Address 00DF16)
8
Data bus
1
0
Selection gate : Connected to
black side at
reset.
Serial I/O
interrupt request
P44 latch
S
OUT1
S
IN1
SIC5
SIC6
PWM9
6
latch
P4
Note : When the data is set in the serial I/O register (address 00DF
Fig. 18. Serial I/O Block Diagram
SDA1
SIC4
16
), the register functions as the serial I/O shift register.
25
MITSUBISHI MICROCOMPUTERS
M37207MF-XXXSP/FP, M37207M8-XXXSP
M37207EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
and ON-SCREEN DISPLAY CONTROLLER
Internal clock : The SRDY signal goes to HIGH during the write cycle
by writing data into the serial I/O register (address 00DD16). After the
write cycle, the SRDY signal goes to “L” (receive enable state). The
____
SRDY signal goes to “H” at the next falling edge of the transfer clock
____
____
for the serial I/O register.
The serial I/O counter is set to “7” during write cycle into the serial I/
O register (address 00DD16), and transfer clock goes HIGH forcibly.
At each falling edge of the transfer clock after the write cycle, serial
data is output from the SOUT pin. Transfer direction can be selected
by bit 5 of the serial I/O mode register. At each rising edge of the
transfer clock, data is input from the SIN pin and data in the serial I/O
register is shifted 1 bit.
After the transfer clock has counted 8 times, the serial I/O counter
becomes “0” and the transfer clock stops at HIGH. At this time the
interrupt request bit is set to “1.”
External clock : When an external clock is selected as the clock source,
the interrupt request is set to “1” after the transfer clock has counted
8 counts. However, transfer operation does not stop, so the clock
should be controlled externally. Use the external clock of 1 MHz or
less with a duty cycle of 50%.
The serial I/O timing is shown in Figure 19. When using an external
clock for transfer, the external clock must be held at “H” for initializing
the serial I/O counter. When switching between an internal clock and
an external clock, do not switch during transfer. Also, be sure to initialize the serial I/O counter after switching.
Notes 1: On programming, note that the serial I/O counter is set by
writing to the serial I/O register with the bit managing instructions such as SEB and CLB.
2: When an external clock is used as the synchronous clock,
write transmit data to the serial I/O register when the transfer clock input level is HIGH.
Synchronous clock
Transfer clock
Serial I/O register
write signal
Serial I/O output
S
OUT
Serial I/O input
S
IN
Receive
signal
enable
RDY
S
Note : When an internal clock is selected, the S
Fig. 19. Serial I/O Timing (for LSB first)
D
0
D
1
D
2
D
3
D
4
D
OUT
pin is at high-impedance after transfer is completed.
(See note)
5
D
6
D
7
Interrupt request bit is set to “1”
26
Serial I/O Mode Register
b7b6 b5b4b3 b2b1b0
MITSUBISHI MICROCOMPUTERS
M37207MF-XXXSP/FP, M37207M8-XXXSP
M37207EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
and ON-SCREEN DISPLAY CONTROLLER
)/4 or f(X
)/16 or f(X
)/32 or f(X
)/64 or f(X
CIN
CIN
CIN
CIN
16]
)/4
)/16
)/32
)/64
After reset
0
RW
RW
Serial I/O mode register (SM) [Address 00DE
BNameFunctions
Internal synchronous
0, 1
clock selection bits
(SM0, SM1)
(See note 1)
b1 b0
0 0: f(X
0 1: f(X
1 0: f(X
1 1: f(X
IN
IN
IN
IN
Fig. 20. Serial I/O Mode Register
Serial I/O Control Register
b7b6 b5b4b3 b2b1b0
Synchronous clock
2
selection bit (SM2)
0, P41
Ports P4
3, 7
function selection
bits (SM3, SM7)
(See note 2)
4, 6
Ports P4
2, P43
function selection bits
(SM4, SM6)
(See note 2)
Transfer direction
5
selection bit (SM5)
Notes 1: Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU
mode register.
2: When using ports P4
the serial control register to “1.”
Serial I/O control register (SIC) [Address 0207
BNameFunctions
Input signal to sift
0
register selection bit
(SIC0)
Serial I/O pin switch
1
bit (CSIO)
2
C-BUS connection
I
2
ports switch bit
(SIC2)
7
function
Ports P4
3, 7
selection bits
(SM3, SM7)
(See note 2)
4, 5
Ports P4
4
, P45
function selection bits
(SM4, SM6)
(See note 2)
6
function
Ports P4
6
selection bits
(SIC6)
(See note 2)
Notes 1: When inputting data from the S
I/O register.
2: When using ports P4
serial I/O control register to “0.”
0: External clock
1: Internal clock
b7
b3
P40/S
OUT2
/
P41/S
CLK2
CIN
SDA3/X
0
P4
✕
0
1
b6
0
1
0
1
0: LSB first
1: MSB first
0
1
S
OUT2
SDA3
b4
P42/S
IN2
/
SDA2/AD8
0
P4
2
SDA2
1
P4
2
SDA2
0–P43 as serial I/O pins, set bit 1 of
COUT
SCL3/X
P4
1
S
CLK2
SCL3
P43/S
RDY2
SCL2/AD7
P4
3
S
RDY2
SDA2
16
]
/
/
After reset
CSIO b0
0 0: Input signal from S
0 1: Input signal from S
1 0: Input signal from S
1 1: Input signal from S
0:
S
OUT1
,
S
CLK1
1:
S
OUT2
,
S
CLK2
0:
SDA2, SCL2, SDA1, SCL1
1:
SDA3, SCL3
P47/S
b7
b3
0
✕
1
0
1
b5
b4
P44/S
OUT1
SDA1
0
P4
4
✕
1
S
OUT1
0
1
SDA1
b6
P46/S
0
1
out
4
–P47 as serial I/O pins, set bit 1 of the
IN1
OUT1
(See note 1)
IN2
OUT2
(See note 1)
,
S
IN1
,
S
RDY1
,
S
IN2
,
S
RDY2
RDY1
/PWM8
P4
7
S
RDY1
PWM8
/
P45/S
CLK1
/
SCL1
P4
5
S
CLK1
SCL1
IN1
/PWM9
P4
6
PWM9
pin, set “FF16” to the serial
0
RW
0
RW
0RW
0RW
RW
RW
0
RW
0
0RW
0RW
0RW
0RW
Fig. 21. Serial I/O Control Register
27
M37207MF-XXXSP/FP, M37207M8-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
Serial I/O Common Transmission/Reception Mode
By writing “1” to bit 0 of the serial I/O control register, signals SIN and
SOUT are switched internally to be able to transmit or receive the
serial data.
Figure 22 shows signals on serial I/O common transmission/reception mode.
Note : When receiving the serial data after writing “FF16” to the serial
I/O register.
MITSUBISHI MICROCOMPUTERS
M37207EFSP/FP
and ON-SCREEN DISPLAY CONTROLLER
S
CLK2
S
OUT2
S
IN2
S
CLK1
S
OUT1
S
IN1
Fig. 22. Signals on Serial I/O Common Transmission/Reception Mode
“1”
“0”
CSIO
“1”
“0”
“1”
“0”
CSIO
“1”
“0”
SIC0
SIC0
: Bit 0 of serialI/O control register
CSIO : Bit 1 of serial I/O control register
Clock
Serial I/O shift register (8)
28
MITSUBISHI MICROCOMPUTERS
M37207MF-XXXSP/FP, M37207M8-XXXSP
M37207EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
and ON-SCREEN DISPLAY CONTROLLER
MULTI-MASTER I2C-BUS INTERFACE
The multi-master I2C-BUS interface is a serial communications circuit, conforming to the Philips I2C-BUS data transfer format. This
interface, offering both arbitration lost detection and a synchronous
functions, is useful for the multi-master serial communications.
Figure 23 shows a block diagram of the multi-master I2C-BUS interface and Table 2 shows multi-master I2C-BUS interface functions.
This multi-master I2C-BUS interface consists of the I2C address register, the I2C data shift register, the I2C clock control register, the I2C
control register, the I2C status register and other control circuits.
I2C address register (S0D)
b7b0
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW
Table 2. Multi-master I2C-BUS Interface Functions
Item
Function
In conformity with Philips I2C-BUS
standard:
Format
10-bit addressing format
7-bit addressing format
High-speed clock mode
Standard clock mode
Note: We are not responsible for any third party’s infringement of
patent rights or other rights attributable to the use of the control function (bits 6 and 7 of the I2C control register at address
00F916) for connections between the I2C-BUS interface and
ports (SCL1, SCL2, SDA1, SDA2).
Interrupt
generating
circuit
Interrupt
request signal
(IICIRQ)
Address comparator
Serial
data
(SDA)
Noise
elimination
circuit
Data
control
circuit
b7
I C data shift register
S0
AL
circuit
BB
circuit
Serial
clock
(SCL)
Noise
elimination
circuit
Clock
control
circuit
b7b0
FAST
ACK
ACK
I2C clock control register (S2)
BIT
MODE
Fig. 23. Block Diagram of Multi-master I2C-BUS Interface
2
CCR4 CCR3 CCR2 CCR1 CCR0
Clock division
b0
Internal data bus
System clock
b7
MST TRX BB PIN
AL AAS AD0 LRB
2
I C status
(S1)
register
b7b0
BSEL1 BSEL0
10BIT
ALS
SAD
I2C clock control register (S1D)
(φ)
BC2 BC1 BC0
ESO
Bit counter
b0
29
MITSUBISHI MICROCOMPUTERS
M37207MF-XXXSP/FP, M37207M8-XXXSP
M37207EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
and ON-SCREEN DISPLAY CONTROLLER
(1) I2C Data Shift Register
The I2C data shift register (S0 : address 00D916) is an 8-bit shift
register to store receive data and write transmit data.
When transmit data is written into this register, it is transferred to the
outside from bit 7 in synchronization with the SCL clock, and each
time one-bit data is output, the data of this register are shifted one bit
to the left. When data is received, it is input to this register from bit 0
in synchronization with the SCL clock, and each time one-bit data is
input, the data of this register are shifted one bit to the left.
The I2C data shift register is in a write enable status only when the
ESO bit of the I2C control register (address 00DC16) is “1.” The bit
counter is reset by a write instruction to the I2C data shift register.
When both the ESO bit and the MST bit of the I2C status register
(address 00F816) are “1,” the SCL is output by a write instruction to
the I2C data shift register. Reading data from the I2C data shift register is always enabled regardless of the ESO bit value.
Note: To write data into the I2C data shift register after setting the
MST bit to “0” (slave mode), keep an interval of 8 machine
cycles or more.
2
I C Data Shift Register
b7 b6 b5 b4 b3 b2 b1 b0
2
I C data shift register1(S0) [Address 00D916]
(2) I2C Address Register
The I2C address register (address 00DA16) consists of a 7-bit slave
address and a read/write bit. In the addressing mode, the slave address written in this register is compared with the address data to be
received immediately after the START condition are detected.
■ Bit 0: Read/Write Bit (RBW)
Not used when comparing addresses, in the 7-bit addressing mode.
In the 10-bit addressing mode, the first address data to be received
is compared with the contents (SAD6 to SAD0 + RBW) of the I2C
address register.
The RBW bit is cleared to “0” automatically when the stop condition
is detected.
■ Bits 1 to 7: Slave Address (SAD0–SAD6)
These bits store slave addresses. Regardless of the 7-bit addressing mode and the 10-bit addressing mode, the address data transmitted from the master is compared with the contents of these bits.
___
____
Fig. 24. I2C Data Shift Register
I2C Address Register
b7 b6 b5 b4 b3 b2 b1 b0
Fig. 25. I2C Address Register
BFunctionsAfter reset R W
Name
D0 to D7
0
to
7
Note:
To write data into the I C data shift register after setting the MST bit to
“0” (slave mode), keep an interval of 8 machine cycles or more.
This is an 8-bit shift register to store
receive data and write transmit data.
2
I2C address register (S0D) [Address 00DA
BNameFunctions
0
Read/write bit
(RBW)
1
Slave address
to
(SAD0 to SAD6)
7
0: Read
1: Write
the master is compared with the
contents of these bits.
16
]
Indeterminate
After reset
RW
0
0The address data transmitted from
RW
R—
RW
30
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