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M35500BGP
Datasheet
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Mitsubishi M35500BGP, M35500AFP Datasheet

MITSUBISHI <DIGITAL ASSP>
M35500AFP/BGP
FLD(VFD) CONTROLLER
DESCRIPTION/FEATURES
High-breakdown-voltage output port ......................................... 26
•
A-D converter ................................................... 8-bit ✕ 6 channels
•
• Segment output............................................ 8 to 18
(Ports P0 to P7 are also used as ordinary output ports)
• Output breakdown.................................. Vcc – 45 V
• Output current.................. –18 mA (DIG0 to DIG17),
–7 mA (SEG0 to SEG7)
• Dimmer switch ............................................ 4 levels
• Absolute accuracy....................................... ±3 LSB
PIN CONFIGURATION (TOP VIEW)
0
1
2
1
1
1
G
G
G
/
/
/
5
4
3
1
1
1
G
G
G
D
I
D
I
S E
D
I
I
S E
S E
S E
Serial I/O ..................................... 4 (CS controller, external clock)
•
Package ................................................................. 44P6N/44P6X
•
Oscillating circuit ........... RC oscillating cirucit (external capacitor)
•
Power source voltage..................................................4.0 to 5.5 V
•
3
4
5
1
1
1
6
7
1
G
G
/
/
2
1
1
1
G
G
D
D
I
I
S E
S E
1
G
G
G
/
0
/
/
1
9
8
G
G
G
D
D
I
D
I
S E
S E
I
P
(in serial input pin and clock pin, 2 MHz sampling)
• FLD display data ............................................. input
• A-D conversion data ..................................... output
• Command ....................................................... input
• Oscillating frequency.....................................4 MHz
7
5
/
/
/
6
7
5
G
G
G
P 6D
D
I
P
D
I
D I G D I G
1 6 1 7
/ S E G / S E G
S E G S E G S E G S E G S E G S E G S E G S E G
V
D D
2
1
3
33
9
3 4
8
3 5
7
3 6
6
3 7
5
3 8
4
3 9
3
4 0
2
4 1
1
4 2
0
4 3
9
3
03
2
82
M 3 5 5 0 0 A F P
M 3 5 5 0 0 B G P
4 4
1
2
3
4
5
S
T
D D
V
U
N
T
I
S
X
O
V
X
R
6
7
2
2
52
6
7
8
5
4
3
N
N
N
A
A
A
2
42
9
2
N A
3
2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2
0
1
1
1
1
0
N
N
A
A
D I G4/ P 4 D I G
3
/ P 3
D I G
2
/ P 2
D I G
1
/ P 1
D I G
0
/ P 0
E E
V V
E E
S
C L K
S
O U T
S
I N
C S
E S E
Fig. 1. Pin configuration of M35500AFP/BGP
Package type: 44P6N-A/44P6X
1

FUNCTIONAL BLOCK

MITSUBISHI <DIGITAL ASSP>
M35500AFP/BGP
FLD(VFD) CONTROLLER
DIG7/P7
6
/P6
DIG
5
/P5
DIG DIG
4
/P4
3
/P3
DIG DIG
2
/P2
1
/P1
DIG
0
/P0
DIG
V
EE
V
EE
25 24 23 22 21 20 19 18
17
16
DIG8/SEG17 – DIG17/SEG
Mode register
Memory address
Transfer counter
8
SEG7 – SEG
0
434241403938373635343332313029282726
Display control circuit
Display RAM
Command analytic circuit
12
CS
IN
S
S
OUT
S
CLK
V
DD
V
DD
V
SS
RESET
13 14 15
44
1
3
5
Noise filter
Noise filter
Clock generating circuit
2
4
OUT
X
IN
X
Selector/A-D control circuit
6 7 8 9 10 11
FUNCTIONAL BLOCK DIAGRAM (Package: 44P6N-A)
Fig. 2. Functional block diagram
AN5 – AN
Byte end
Serial I/O
Trigger
A-D
0
2

PIN DESCRIPTION

Table. 1. Pin description
Pin VCC, VSS VEE
XIN XOUT
______
RESET
____
CS SCLK
SOUT
SIN
DIG0/P0 – DIG7/P7
DIG8/SEG17 – DIG17/SEG8
SEG0 – SEG7
Name Power source Pull-down
power source Clock input Clock output
______
RESET input
Chip select Serial clock
Serial output
Serial input
Digit/Port
Digit/Segment
Segment
Input
Input
CMOS input
CMOS input CMOS input
Noise filter
CMOS input Noise filter
Output
Output
N-channel open-drain
P-channel open-drain
P-channel open-drain
P-channel open-drain
MITSUBISHI <DIGITAL ASSP>
M35500AFP/BGP
FLD(VFD) CONTROLLER
Function
• Apply voltage of 5 V to VCC, and 0 V to VSS.
• Applies voltage supplied to pull-down resistors.
• RC oscillator pins for system clock.
• Reset input pin for active “L”.
• Internal pull-up resistors connected between the RESET and VCC pins.
• Serial transfer is possible by inputting “L” signal.
• Clock for serial transfer is input.
•
Read a clock twice with 2 MHz sampling clock and judge if it is a noise or not.
• Serial data is output.
• During reset it is in high-impedance state.
• Serial data is input.
•
Read a clock twice with 2 MHz sampling clock and judge if it is a noise or not.
• Pin for ordinary output or digit output.
• At reset this port is set to VEE level through a pull-down resistor.
• Pin for digit output or segment output.
• At reset this port is set to VEE level through a pull-down resistor.
• Pin for segment output.
• At reset this port is set to VEE level through a pull-down resistor.
PORT BLOCK
(1) Digit/Port pin
Digit/Segment pin
Shift signal from high-order
Data bus Segment data
Shift signal to low-order
(2) Digit pin
Shift signal from high-order
Shift signal to low-order
(3) Segment pin
Segment data
Dimmer signal
(Note)
latch
Dimmer signal
(Note)
latch
Dimmer signal
(Note)
latch
(4) S
OUT
pin
S
OUT
signal
✽
V
EE
✽
V
EE
✽
(5) CS pin
CS input
IN
, S
CLK
(6) S
(7) A-D input
pin
Serial input
Serial clock input
A-D conversion input
Noise filter
Noise filter
Fig. 3. Port block diagram
✽ High-breakdown-voltage P-channel transistor
V
EE
Note: Dimmer signal is for setting the Toff time.
3

COMMAND STYLE

Display data setting (Command 0)
111
MITSUBISHI <DIGITAL ASSP>
M35500AFP/BGP
FLD(VFD) CONTROLLER
b0b1b2b3b4b5b6b7
—
Number of segment setting
0 0 : 16 or less 0 1 : 17 or more
Number of digit setting
0 0 : 7 0 1 : 8 1 0 : 9 1 1 : 10
Display state setting (Command 1)
Digit selection (Command 2)
Port data setting (Command 3)
110
10
100
1
——
—
Display ON or OFF setting
1 : ON 0 : OFF
Display duty setting
1 1 : 15/16 1 0 : 14/16 0 1 : 6/16 0 0 : 5/16
Digit start pin setting
0 0 0 0 : D 0 0 0 1 : D16 0 0 1 0 : D15 0 0 1 1 : D14 0 1 0 0 : D13 0 1 0 1 : D12 0 1 1 0 : D11 0 1 1 1 : D10 1 0 0 0 : D9 1 0 0 1 : D8 1 0 1 0 : D7
17
Note: When a digit or a port has to be selected, a digit output is selected for having higher priority.
Fig. 4. Command style
4
P3 – P0/P7 – P4 output data Port selection (Note)
0 : P3 – P0 1 : P7 – P4
0

SERIAL I/O PROTOCOL

Byte protocol
MITSUBISHI <DIGITAL ASSP>
M35500AFP/BGP
FLD(VFD) CONTROLLER
CS
CLK
Command protocol
Display data setting (Command 0)
S
IN
S
OUT
CS
CLK
S
IN
S
OUT
b0 b1 b2 b3 b4 b5 b6 b7
X
b0 b1 b2 b3 b4 b5 b6 b7
OUT
Note: S
Note 1: The serial data which is transmitted after executing command
Note 2: Set the CS signal to “H” level after transferring a display data.
is in high-impedance state during CS signal is “H”.
Command 0 Data 1 Data 2
X
is recognized as a display data. “A-D data 6 or more” data is defined as an undefined “X”.
X
A-D
data 0
Data i
A-D
data j
Other setting except display data setting (Command 1 to 3)
Fig. 5. Serial I/O protocol
CS
CLK
S
IN
S
OUT
Command
X
5
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