Mitsubishi M2S56D20AKT-75, M2S56D20AKT-10L, M2S56D20AKT-10, M2S56D20ATP-75L, M2S56D20ATP-75AL Datasheet
...
DDR SDRAM
(Rev.1.44)
Mar. '02
M2S56D20/ 30/ 40ATP -75AL, -75A, -75L, -75, -10L, -10
M2S56D20/ 30/ 40AKT -75AL, -75A, -75L, -75, -10L, -10
256M Double Data Rate Synchronous DRAM
Contents are subject to change without notice.
DESCRIPTION
MITSUBISHI LSIs
M2S56D20ATP / AKT is a 4-bank x 16777216-word x 4-bit,
M2S56D30ATP / AKT is a 4-bank x 8388608-word x 8-bit,
M2S56D40ATP/ AKT is a 4-bank x 4194304-word x 16-bit,
double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are
referenced to the rising edge of CLK.Input data is registered on both edges of data strobes, and output
data and data strobe are referenced on both edges of CLK. The M2S56D20/30/40ATP achieve very high
speed data rate up to 133MHz, and are suitable for main memory in computer systems.
FEATURES
- VDD=VDDQ=2.5V+0.2V
- Double data rate architecture; two data transfers per clock cycle
- Bidirectional, data strobe (DQS) is transmitted/received with data
- Differential clock inputs (CLK and /CLK)
- DLL aligns DQ and DQS transitions
- Commands are entered on each positive CLK edge
- Data and data mask are referenced to both edges of DQS
- 4-bank operations are controlled by BA0, BA1 (Bank Address)
- /CAS latency- 2.0/2.5 (programmable)
- Burst length- 2/4/8 (programmable)
- Burst type- sequential / interleave (programmable)
- Auto precharge / All bank precharge is controlled by A10
- 8192 refresh cycles /64ms (4 banks concurrent refresh)
- Auto refresh and Self refresh
- Row address A0-12 / Column address A0-9,11(x4)/ A0-9(x8)/ A0-8(x16)
- SSTL_2 Interface
- Both 66-pin TSOP Package and 64-pin Small TSOP Package
M2S56D*0ATP: 0.8mm lead pitch 66-pin TSOP Package
M2S56D*0AKT: 0.4mm lead pitch 64-pin Small TSOP Package
- JEDEC standard
- Low Power for the Self Refresh Current ICC6 : 2mA (-75AL , -75L , -10L)
Operating Frequencies
M2S56D20/30/40ATP/AKT-75AL/-75A
M2S56D20/30/40ATP/AKT-75L/-75
M2S56D20/30/40ATP/AKT-10L/-10
* CL = CAS(Read) Latency
Max. Frequency
@CL=2.0 *
100MHz
100MHz
Max. Frequency
MITSUBISHI ELECTRIC
@CL=2.5 *
133MHz
125MHz
Standard
DDR266A133MHz133MHz
DDR266B
DDR200
1
DDR SDRAM
(Rev.1.44)
Mar. '02
MITSUBISHI LSIs
M2S56D20/ 30/ 40ATP -75AL, -75A, -75L, -75, -10L, -10
M2S56D20/ 30/ 40AKT -75AL, -75A, -75L, -75, -10L, -10
256M Double Data Rate Synchronous DRAM
PIN CONFIGURATION(TOP VIEW)
x4
x8
x16
VDD
NC
VDDQ
NC
DQ0
VSSQ
NC
NC
VDDQ
NC
DQ1
VSSQ
NC
NC
VDDQ
NC
NC
VDD
NC
NC
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
VDD
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
NC
VDDQ
NC
NC
VDD
NC
NC
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDDQ
LDQS
NC
VDD
NC
LDM
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66pin TSOP(II)
400mil width
x
875mil length
0.65mm
Lead Pitch
ROW
A0-12
Column
A0-9,11(x4)
A0-9 (x8)
A0-8 (x16)
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSSQ
UDQS
NC
VREF
VSS
UDM
/CLK
CLK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
/CLK
CLK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
VSS
NC
VSSQ
NC
DQ3
VDDQ
NC
NC
VSSQ
NC
DQ2
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
/CLK
CLK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
CLK,/CLK : Master Clock
CKE : Clock Enable
/CS : Chip Select
/RAS : Row Address Strobe
/CAS : Column Address Strobe
/WE : Write Enable
DQ0-15 : Data I/O
DQS
LDQS,UDQS
: Data Strobe
MITSUBISHI ELECTRIC
DM
LDM,UDM
VREF : Reference Voltage
A0-12 : Address Input
BA0,1 : Bank Address Input
VDD : Power Supply
VDDQ : Power Supply for Output
VSS : Ground
VSSQ : Ground for Output
: Write Mask
2
DDR SDRAM
(Rev.1.44)
Mar. '02
MITSUBISHI LSIs
M2S56D20/ 30/ 40ATP -75AL, -75A, -75L, -75, -10L, -10
M2S56D20/ 30/ 40AKT -75AL, -75A, -75L, -75, -10L, -10
256M Double Data Rate Synchronous DRAM
PIN CONFIGURATION(TOP VIEW)
X 4
X 8
X 16
VDD VDD VDD
NC DQ0 DQ0
VDDQ VDDQ VDDQ
NC NC DQ1
DQ0 DQ1 DQ2
VSSQ VSSQ VSSQ
NC NC DQ3
NC DQ2 DQ4
VDDQ VDDQ VDDQ
NC NC DQ5
DQ1 DQ3 DQ6
VSSQ VSSQ VSSQ
NC NC DQ7
VDDQ VDDQ VDDQ
NC NC LDQS
NC NC NC
VDD VDD VDD
NC NC NC
NC NC LDM
/WE /WE /WE
/CAS /CAS /CAS
/RAS /RAS /RAS
/CS /CS /CS
NC NC NC
BA0 BA0 BA0
BA1 BA1 BA1
A10/AP A10/AP A10/AP
A0 A0 A0
A1 A1 A1
A2 A2 A2
A3 A3 A3
VDD VDD VDD
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
64pin sTSOP
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
PIN PITCH 0.4 mm
42
41
40
39
38
37
36
35
34
33
VSS VSS VSS
DQ15 DQ7 NC
VSSQ VSSQ VSSQ
DQ14 NC NC
DQ13 DQ6 DQ3
VDDQ VDDQ VDDQ
DQ12 NC NC
DQ11 DQ5 NC
VSSQ VSSQ VSSQ
DQ10 NC NC
DQ9 DQ4 DQ2
VDDQ VDDQ VDDQ
DQ8 NC NC
VSSQ VSSQ VSSQ
UDQS DQS DQS
NC NC NC
VREF VREF VREF
VSS VSS VSS
UDM DM DM
/CLK /CLK /CLK
CLK CLK CLK
CKE CKE CKE
NC NC NC
A12 A12 A12
A11 A11 A11
A9 A9 A9
A8 A8 A8
A7 A7 A7
A6 A6 A6
A5 A5 A5
A4 A4 A4
VSS VSS VSS
CLK,/CLK : Master Clock
CKE : Clock Enable
/CS : Chip Select
/RAS : Row Address Strobe
/CAS : Column Address Strobe
/WE : Write Enable
DQ0-15 : Data I/O
DQS
LDQS,UDQS
: Data Strobe
MITSUBISHI ELECTRIC
DM
LDM,UDM
VREF : Reference Voltage
A0-12 : Address Input
BA0,1 : Bank Address Input
VDD : Power Supply
VDDQ : Power Supply for Output
VSS : Ground
VSSQ : Ground for Output
: Write Mask
3
DDR SDRAM
(Rev.1.44)
M2S56D20/ 30/ 40ATP -75AL, -75A, -75L, -75, -10L, -10
M2S56D20/ 30/ 40AKT -75AL, -75A, -75L, -75, -10L, -10
Mar. '02
Package Outline of sTSOP
MITSUBISHI LSIs
256M Double Data Rate Synchronous DRAM
+
0.125
0.05
-
0.02
10.65+0.2
9.05+0.1
*2
64
*1
13.1+0.1
33
A
321
1.2 MAX
B
0.25
0.8
(1)
0.125+0.075
Detail A (NTS)
0
0.4 NOM
-
10
0.1
*3
0.16
+0.1
-0.05
0.08
M
Note)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
0.5+0.1
0.6+0.15
0.35
0.55 MAX
Detail B (NTS)
MITSUBISHI ELECTRIC
4
DDR SDRAM
(Rev.1.44)
Mar. '02
M2S56D20/ 30/ 40ATP -75AL, -75A, -75L, -75, -10L, -10
M2S56D20/ 30/ 40AKT -75AL, -75A, -75L, -75, -10L, -10
256M Double Data Rate Synchronous DRAM
PIN FUNCTION
SYMBOL TYPE DESCRIPTION
Clock: CLK and /CLK are differential clock inputs. All address and control
input signals are sampled on the crossing of the positive edge of CLK and
MITSUBISHI LSIs
CLK, /CLK Input
CKE Input
/CS Input Chip Select: When /CS is high, any command means No Operation.
/RAS, /CAS, /WE Input Combination of /RAS, /CAS, /WE defines basic commands.
A0-12 Input
negative edge of /CLK. Output (read) data is referenced to the crossings of
CLK and /CLK (both directions of crossing).
Clock Enable: CKE controls internal clock. When CKE is low, internal clock
for the following cycle is ceased. CKE is also used to select auto / self
refresh.After self refresh mode is started, CKE becomes asynchronous
input. Self refresh is maintained as long as CKE is low.
A0-12 specify the Row / Column Address in conjunction with BA0,1. The
Row Address is specified by A0-12. The Column Address is specified by
A0-9,11(x4), A0-9(x8) and A0-8(x16). A10 is also used to indicate precharge
option. When A10 is high at a read / write command, an auto precharge is
performed. When A10 is high at a precharge command, all banks are
precharged.
BA0,1 Input
DQ0-15(x16),
DQ0-7(x8),
DQ0-3(x4),
DQS
DM
VDD, VSS Power Supply Power Supply for the memory array and peripheral circuitry.
VDDQ, VSSQ Power Supply VDDQ and VSSQ are supplied to the Output Buffers only.
VREF Input SSTL_2 reference voltage.
Input / Output
Input / Output
Input
Bank Address: BA0,1 specifies one of four banks to which a command is
applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands.
Data Input/Output: Data bus
Data Strobe: Output pin during Read operation, input pin during Write
operation. Edge-aligned with read data, placed at the centered of write data
to capture the write data. For the x16, LDQS corresponds to the data on
DQ0-DQ7; UDQS correspond to the data on DQ8-DQ15.
Input Data Mask: DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH along with the input data
during a WRITE operations. DM is sampled on both edges of DQS.
Although DM pins are input only, the DM loading matches the DQ
and DQS loading. For the x16, LDM corresponds to the data on DQ0-DQ7;
UDM corresponds to the data on DQ8-DQ15.
MITSUBISHI ELECTRIC
5
DDR SDRAM
(Rev.1.44)
Mar. '02
MITSUBISHI LSIs
M2S56D20/ 30/ 40ATP -75AL, -75A, -75L, -75, -10L, -10
M2S56D20/ 30/ 40AKT -75AL, -75A, -75L, -75, -10L, -10
256M Double Data Rate Synchronous DRAM
BLOCK DIAGRAM
DLL
Memory
Array
Bank #0
Mode Register
DQ0 - 15
I/O Buffer
Memory
Array
Bank #1
Control Circuitry
Memory
Array
Bank #2
UDQS,LDQS
QS Buffer
Memory
Array
Bank #3
Address Buffer
A0-12
BA0,1
Type Designation Code
M 2 S 56 D 3 0 A KT –75A L
Control Signal Buffer
Clock Buffer
/CS /RAS /CAS /WE UDM,
CLK CKE
/CLK
This rule is applied to only Synchronous DRAM family.
Power Grade L: Low power, Blank: standard
Speed Grade10: 125MHz@CL=2.5,100MHz@CL=2.0
75: 133MHz@CL=2.5,100MHz@CL=2.0
75A: 133MHz@CL=2.5,133MHz@CL=2.0
Package Type TP: TSOP(II), KT: sTSOP(Small TSOP)
Process Generation
Function Reserved for Future Use
Organization 2
DDR Synchronous DRAM
Density 56: 256M bits
Interface V:LVTTL, S:SSTL_3, _2
Memory Style (DRAM)
Mitsubishi Main Designation
n
2: x4, 3: x8, 4: x16
LDM
(DDR200)
(DDR266B)
(DDR266A)
MITSUBISHI ELECTRIC
6
DDR SDRAM
(Rev.1.44)
Mar. '02
M2S56D20/ 30/ 40ATP -75AL, -75A, -75L, -75, -10L, -10
M2S56D20/ 30/ 40AKT -75AL, -75A, -75L, -75, -10L, -10
256M Double Data Rate Synchronous DRAM
BASIC FUNCTIONS
The M2S56D20/30/40A* provides basic functions, bank (row) activate, burst read / write, bank (row)
precharge, and auto / self refresh. Each command is defined by control signals of /RAS, /CAS and /WE at
CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip select, refresh option, and
precharge option, respectively. Refer to the command truth table for the detailed definition of commands.
/CLK
CLK
MITSUBISHI LSIs
/CS
Chip Select : L=select, H=deselect
/RAS
/CAS
/WE
CKE
A10
Command
Command
Command
Refresh Option @refresh command
Precharge Option @precharge or read/write command
define basic commands
Activate (ACT) [/RAS =L, /CAS =/WE =H]
ACT command activates one row in an idle bank indicated by BA.
Read (READ) [/RAS =H, /CAS =L, /WE =H]
READ command starts burst read from the active bank indicated byBA. First output data appears after
/CAS latency. When A10 =H in this command, the bank is deactivated after the burst read (autoprecharge, READA)
Write (WRITE) [/RAS =H, /CAS =/WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data length to be written
is defined by burst length. When A10 =H in this command, the bank is deactivated after the burst write
(auto-precharge, WRITEA)
Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]
PRE command deactivates the active bank indicated by BA. This command also terminates burst read
/write operation. When A10 =H in this command, all banks are deactivated (precharge all, PREA ).
Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh addresses including bank address are generated
internally. After this command, the banks are precharged automatically.
MITSUBISHI ELECTRIC
7
DDR SDRAM
(Rev.1.44)
M2S56D20/ 30/ 40ATP -75AL, -75A, -75L, -75, -10L, -10
M2S56D20/ 30/ 40AKT -75AL, -75A, -75L, -75, -10L, -10
Mar. '02
COMMAND TRUTH TABLE
MITSUBISHI LSIs
256M Double Data Rate Synchronous DRAM
COMMAND MNEMONIC
Deselect DESEL H X H X X X X X X
No Operation NOP H X L H H H X X X
Row Address Entry &
Bank Activate
Single Bank Precharge PRE H H L L H L V L X
Precharge All Banks
Column Address Entry
& Write
Column Address Entry
& Write with
Auto-Precharge
Column Address Entry
& Read
Column Address Entry
& Read with
Auto-Precharge
Auto-Refresh REFA H H L L L H X X X
ACT H H L L H H V V V
PREA H H L L H L H X
WRITE H H L H L L V L V
WRITEA H H L H L L V H V
READ H H L H L H V L V
READA H H L H L H V H V
CKE
n-1
CKE
n
/CS /RAS /CAS /WE BA0,1
X
A10
/AP
A0-9,
11-12
note
Self-Refresh Entry REFS H L L L L H X X X
Self-Refresh Exit REFSX
Burst Terminate TERM H H L H H L X X X
Mode Register Set MRS H H L L L L L L V
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number
NOTE:
1. Applies only to read bursts while autoprecharge is disabled; this command is undefined (and should not be
used) during read bursts while autoprecharge is enabled, as well as during write bursts.
2. BA0-BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode
Register;BA0=1 ,BA1 = 0 selects Extended Mode Register; other combinations of BA0-BA1 are
reserved; A0-A12 provide the op-codes to be written to the selected Mode Register.
L H H X X X X X X
L H L H H H X X X
1
2
MITSUBISHI ELECTRIC
8
DDR SDRAM
Mode-Add
Determine Auto-Precharge
Determine Auto-Precharge
Mode-Add
(Rev.1.44)
Mar. '02
M2S56D20/ 30/ 40ATP -75AL, -75A, -75L, -75, -10L, -10
M2S56D20/ 30/ 40AKT -75AL, -75A, -75L, -75, -10L, -10
256M Double Data Rate Synchronous DRAM
FUNCTION TRUTH TABLE
Current State /CS /RAS /CAS /WE Address Command Action Notes
IDLE H X X X X DESEL NOP
L H H H X NOP NOP
L H H L BA TERM ILLEGAL 2
L H L X BA, CA, A10 READ / WRITE ILLEGAL 2
L L H H BA, RA ACT Bank Active, Latch RA
L L H L BA, A10 PRE / PREA NOP 4
L L L H X REFA Auto-Refresh 5
MITSUBISHI LSIs
L L L L
ROW ACTIVE H X X X X DESEL NOP
L H H H X NOP NOP
L H H L BA TERM NOP
L H L H BA, CA, A10 READ / READA
Op-Code,
MRS Mode Register Set 5
Begin Read, Latch CA,
READ(Auto-
Precharge
Disabled)
L H L L BA, CA, A10 WRITE / WRITEA
L L H H BA, RA ACT Bank Active / ILLEGAL 2
L L H L BA, A10 PRE / PREA Precharge / Precharge All
L L L H X REFA ILLEGAL
L L L L
H X X X X DESEL NOP (Continue Burst to END)
L H H H X NOP NOP (Continue Burst to END)
L H H L BA TERM Terminate Burst
L H L H BA, CA, A10 READ / READA
L H L L BA, CA, A10 WRITE / WRITEA ILLEGAL
L L H H BA, RA ACT Bank Active / ILLEGAL 2
L L H L BA, A10 PRE / PREA Terminate Burst, Precharge
L L L H X REFA ILLEGAL
L L L L
Op-Code,
Op-Code,
Mode-Add
MRS ILLEGAL
MRS ILLEGAL
Begin Write, Latch CA,
Terminate Burst, Latch CA, Begin
New Read, Determine AutoPrecharge
3
MITSUBISHI ELECTRIC
9
DDR SDRAM
(Rev.1.44)
Mar. '02
M2S56D20/ 30/ 40ATP -75AL, -75A, -75L, -75, -10L, -10
M2S56D20/ 30/ 40AKT -75AL, -75A, -75L, -75, -10L, -10
256M Double Data Rate Synchronous DRAM
FUNCTION TRUTH TABLE (continued)
Current State /CS /RAS /CAS /WE Address Command Action Notes
MITSUBISHI LSIs
WRITE(Auto-
Precharge
Disabled)
READ with
Auto-
Precharge
WRITE with
Auto-
Precharge
H X X X X DESEL NOP (Continue Burst to END)
L H H H X NOP NOP (Continue Burst to END)
L H H L BA TERM ILLEGAL
L H L H BA, CA, A10 READ / READA
L H L L BA, CA, A10 WRITE / WRITEA
L L H H BA, RA ACT Bank Active / ILLEGAL 2
L L H L BA, A10 PRE / PREA Terminate Burst, Precharge
L L L H X REFA ILLEGAL
L L L L
H X X X X DESEL NOP (Continue Burst to END)
L H H H X NOP NOP (Continue Burst to END)
L H H L BA TERM ILLEGAL
L H L H BA, CA, A10 READ / READA ILLEGAL for Same Bank 6
L H L L BA, CA, A10 WRITE / WRITEA ILLEGAL for Same Bank 6
L L H H BA, RA ACT Bank Active / ILLEGAL 2
L L H L BA, A10 PRE / PREA Precharge / ILLEGAL 2
L L L H X REFA ILLEGAL
L L L L
H X X X X DESEL NOP (Continue Burst to END)
L H H H X NOP NOP (Continue Burst to END)
L H H L BA TERM ILLEGAL
L H L H BA, CA, A10 READ / READA ILLEGAL for Same Bank 7
L H L L BA, CA, A10 WRITE / WRITEA ILLEGAL for Same Bank 7
L L H H BA, RA ACT Bank Active / ILLEGAL 2
L L H L BA, A10 PRE / PREA Precharge / ILLEGAL 2
L L L H X REFA ILLEGAL
L L L L
Op-Code,
Mode-Add
Op-Code,
Mode-Add
Op-Code,
Mode-Add
MRS ILLEGAL
MRS ILLEGAL
MRS ILLEGAL
Terminate Burst, Latch CA, Begin
Read, Determine Auto-Precharge
Terminate Burst, Latch CA, Begin
Write, Determine Auto-Precharge
3
3
MITSUBISHI ELECTRIC
10
DDR SDRAM
(Rev.1.44)
Mar. '02
M2S56D20/ 30/ 40ATP -75AL, -75A, -75L, -75, -10L, -10
M2S56D20/ 30/ 40AKT -75AL, -75A, -75L, -75, -10L, -10
256M Double Data Rate Synchronous DRAM
FUNCTION TRUTH TABLE (continued)
Current State /CS /RAS /CAS /WE Address Command Action Notes
MITSUBISHI LSIs
PRE-
CHARGING
ROW
ACTIVATING
WRITE RE-
COVERING
H X X X X DESEL NOP (Idle after tRP)
L H H H X NOP NOP (Idle after tRP)
L H H L BA TERM ILLEGAL 2
L H L X BA, CA, A10 READ / WRITE ILLEGAL 2
L L H H BA, RA ACT ILLEGAL 2
L L H L BA, A10 PRE / PREA NOP (Idle after tRP) 4
L L L H X REFA ILLEGAL
L L L L
H X X X X DESEL NOP (Row Active after tRCD)
L H H H X NOP NOP (Row Active after tRCD)
L H H L BA TERM ILLEGAL 2
L H L X BA, CA, A10 READ / WRITE ILLEGAL 2
L L H H BA, RA ACT ILLEGAL 2
L L H L BA, A10 PRE / PREA ILLEGAL 2
L L L H X REFA ILLEGAL
L L L L
H X X X X DESEL NOP
L H H H X NOP NOP
L H H L BA TERM ILLEGAL 2
L H L X BA, CA, A10 READ / WRITE ILLEGAL 2
L L H H BA, RA ACT ILLEGAL 2
L L H L BA, A10 PRE / PREA ILLEGAL 2
L L L H X REFA ILLEGAL
L L L L
Op-Code,
Mode-Add
Op-Code,
Mode-Add
Op-Code,
Mode-Add
MRS ILLEGAL
MRS ILLEGAL
MRS ILLEGAL
MITSUBISHI ELECTRIC
11
DDR SDRAM
(Rev.1.44)
Mar. '02
M2S56D20/ 30/ 40ATP -75AL, -75A, -75L, -75, -10L, -10
M2S56D20/ 30/ 40AKT -75AL, -75A, -75L, -75, -10L, -10
256M Double Data Rate Synchronous DRAM
FUNCTION TRUTH TABLE (continued)
Current State /CS /RAS /CAS /WE Address Command Action Notes
REFRESHING H X X X X DESEL NOP (Idle after tRFC)
L H H H X NOP NOP (Idle after tRFC)
L H H L BA TERM ILLEGAL
L H L X BA, CA, A10 READ / WRITE ILLEGAL
L L H H BA, RA ACT ILLEGAL
L L H L BA, A10 PRE / PREA ILLEGAL
L L L H X REFA ILLEGAL
MITSUBISHI LSIs
Op-Code,
Mode-Add
Op-Code,
Mode-Add
MRS ILLEGAL
MRS ILLEGAL
MODE
REGISTER
SETTING
L L L L
H X X X X DESEL NOP (Idle after tMRD)
L H H H X NOP NOP (Idle after tMRD)
L H H L BA TERM ILLEGAL
L H L X BA, CA, A10 READ / WRITE ILLEGAL
L L H H BA, RA ACT ILLEGAL
L L H L BA, A10 PRE / PREA ILLEGAL
L L L H X REFA ILLEGAL
L L L L
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No Operation
NOTES:
1. All entries are valid only when CKE was High during the preceding clock cycle and the current clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the
state of specific bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
6. Refer to Read with Auto-Precharge in page 27.
7. Refer to Write with Auto-Precharge in page 29.
ILLEGAL = Device operation and/or data-integrity are not guaranteed.
MITSUBISHI ELECTRIC
12
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