Mitsubishi M2S28D40ATP, M2S28D30ATP, M2S28D20ATP Datasheet

DDR SDRAM (Rev.0.1)

MITSUBISHI LSIs

Jun,'00

Preliminary

128M Double Data Rate Synchronous DRAM

M2S28D20/ 30/ 40A TP

PRELIMINARY

Some of contents are subject to change without notice.

DESCRIPTION

M2S28D20ATP is a 4-bank x 8388608-word x 4-bit,
M2S28D30ATP is a 4-bank x 4194304-word x 8-bit,
M2S28D40ATP is a 4-bank x 2097152-word x 16-bit,
double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are
referenced to the rising edge of CLK. Input data is registered on both edges of data strobe, and output
data and data strobe are referenced on both edges of CLK. The M2S28D20/30/40ATP achieves very
high speed data rate up to 133MHz, and are suitable for main memory in computer systems.

FEATURES

- Vdd=Vddq=2.5V+0.2V

- Double data rate architecture;
two data transfers per clock cycle

- Bidirectional, data strobe (DQS) is transmitted/received with data

- Differential clock inputs (CLK and /CLK)

- DLL aligns DQ and DQS transitions
with CLK transitions edges of DQS

- Commands entered on each positive CLK edge;

- data and data mask referenced to both edges of DQS

- 4 bank operation controlled by BA0, BA1 (Bank Address)

- /CAS latency- 2.0/2.5 (programmable)

- Burst length- 2/4/8 (programmable)

- Burst type- sequential / interleave (programmable)

- Auto precharge / All bank precharge controlled by A10

- 4096 refresh cycles /64ms (4 banks concurrent refresh)

- Auto refresh and Self refresh

- Row address A0-11 / Column address A0-9,11(x4)/ A0-9(x8)/ A0-8(x16)

- SSTL_2 Interface

- 400-mil, 66-pin Thin Small Outline Package (TSOP II)

- FET switch control(/QFC) for x4/ x8

- JEDEC standard

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DDR SDRAM (Rev.0.1)

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Jun,'00

VDD

NC

VDDQ

NC

DQ0

VSSQ

NC
NC

VDDQ

NC

DQ1

VSSQ

NC
NC

VDDQ

NC
NC

VDD

NU,/QFC

NC

/WE
/CAS
/RAS

/CS

NC

BA0

BA1

A10/AP

A0
A1

A2
A3

VDD

Preliminary

VDD
DQ0

VDDQ

NC

DQ1

VSSQ

NC

DQ2

VDDQ

NC

DQ3

VSSQ

NC
NC

VDDQ

NC
NC

VDD

NU,/QFC

NC

/WE
/CAS
/RAS

/CS

NC

BA0

BA1

A10/AP

A0
A1

A2
A3

VDD

128M Double Data Rate Synchronous DRAM

PIN CONFIGURATION(TOP VIEW)

x4
x8

x16

VDD
DQ0

VDDQ

DQ1
DQ2

VSSQ

DQ3
DQ4

VDDQ

DQ5
DQ6

VSSQ

DQ7

NC

VDDQ

LDQS

NC

VDD

NC

LDM

/WE
/CAS
/RAS

/CS

NC

BA0
BA1

A10/AP

VDD

A0
A1

A2
A3

1
2
3

4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

26
27
28
29
30

31
32
33

66pin TSOP(II)

400mil width

x

875mil length

0.65mm

Lead Pitch

ROW

A0-11

Column

A0-9,11(x4)
A0-9 (x8)
A0-8 (x16)

M2S28D20/ 30/ 40A TP

66
65
64

63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42

41
40
39
38
37

36
35
34

VSS
DQ15
VSSQ

DQ14
DQ13
VDDQ

DQ12
DQ11
VSSQ
DQ10
DQ9

VDDQ
DQ8
NC
VSSQ
UDQS

NC
VREF

VSS
UDM

/CLK

CLK
CKE
NC
NC

A11
A9
A8

A7
A6

A5
A4

VSS

VSS
DQ7
VSSQ

NC
DQ6
VDDQ

NC
DQ5
VSSQ
NC
DQ4

VDDQ
NC
NC
VSSQ
DQS

NC
VREF

VSS
DM

/CLK

CLK
CKE
NC
NC

A11
A9
A8

A7
A6

A5
A4

VSS

VSS
NC
VSSQ

NC
DQ3
VDDQ

NC
NC
VSSQ
NC
DQ2

VDDQ
NC
NC
VSSQ
DQS

NC
VREF

VSS
DM

/CLK

CLK
CKE
NC
NC

A11
A9
A8

A7
A6

A5
A4

VSS

CLK,/CLK : Master Clock
CKE : Clock Enable
/CS : Chip Select
/RAS : Row Address Strobe
/CAS : Column Address Strobe
/WE : Write Enable
DQ0-7 : Data I/O
DQS : Data Strobe
DM : Write Mask
/QFC : FET Switch Control for x4/x8
Vref : Reference Voltage

MITSUBISHI ELECTRIC

A0-11 : Address Input
BA0,1 : Bank Address Input
Vdd : Power Supply
VddQ : Power Supply for Output
Vss : Ground
VssQ : Ground for Output

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BLOCK DIAGRAM

Preliminary

DLL

Memory

Array

Bank #0

Memory

Array

Bank #1

128M Double Data Rate Synchronous DRAM

DQ0 - 15

I/O Buffer

M2S28D20/ 30/ 40A TP

/QFC for x4/x8

Memory

Array

Bank #2

UDQS,LDQS

QFC&QS Buffer

Memory

Array

Bank #3

Mode Register

Address Buffer

A0-11

BA0,1

Type Designation Code

M 2 S 28 D 3 0 A TP -75

Control Circuitry

Control Signal Buffer

Clock Buffer

/CS /RAS /CAS /WE UDM,

CLK, /CLK CKE

This rule is applied to only Synchronous DRAM family.

Speed Grade 10: 125MHz@CL=2 .5,100MHz@CL=2. 0
75: 133MHz@CL=2.5,100MHz@CL=2.0

Package Type TP: TSOP(II)
Process Generation
Function Reserved for Future Use
Organization 2n 2: x4, 3: x8, 4: x16

DDR Synchronous DRAM

Density 28: 128M bits
Interface V:LVTTL, S:SSTL_3, _2
Memory Style (DRAM)
Mitsubishi Main Designation

LDM

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Preliminary

M2S28D20/ 30/ 40A TP

128M Double Data Rate Synchronous DRAM

PIN FUNCTION

SYMBOL TYPE DESCRIPTION

Clock: CLK and /CLK are differential clock inputs. All address and

CLK, /CLK Input

CKE Input

/CS Input Chip Select: When /CS is high, any command means No Operation.

/RAS, /CAS, /WE Input Combination of /RAS, /CAS, /WE defines basic commands.

A0-11 Input

control input signals are sampled on the crossing of the positive edge
of CLK and negative edge of /CLK. Output (read) data is referenced to
the crossings of CLK and /CLK (both directions of crossing).

Clock Enable: CKE controls internal clock. When CKE is low, internal
clock for the following cycle is ceased. CKE is also used to select auto /
self refresh. After self refresh mode is started, CKE becomes
asynchronous input. Self refresh is maintained as long as CKE is low.

A0-11 specify the Row / Co lumn Address in conjunction with BA0,1.
The Row Address is specified by A0-11. The Column Address is
specified by A0-9,11(x4), A0-9(x8) and A0-8(x16). A10 is also used to
indicate precha rge option. When A10 is high at a read / write
command, an auto precharge is performed. When A10 is high at a
precharge command, all banks are precharged.

BA0,1 Input

DQ0-15(x16),
DQ0-7(x8),
DQ0-3(x4),

DQS

/QFC Output

DM

Vdd, Vss Power Supply Power Supply for the memory array and peripheral circuitry.

VddQ, VssQ Power Supply VddQ and VssQ are supplied to the Output Buffers only.

Input / Output

Input / Output

Input

Bank Address: BA0,1 specifies one of four banks to which a command is
applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands.

Data Input/Output: Data bus

Data Strobe: Output with read data, input with write data. Edge­aligned with read data, c e ntered in write data. Used to ca pture write
data. For the x16, LDQS corresponds to the data on DQ0-DQ7; UDQS
correspond to the data on DQ8-DQ15

FET Control: Optional. Output during every Read and Write acce ss. Can
be used to control isolation switches on modules. Open drain output.

Input Data Mask: DM is an input mask signal for write data. Input data
is masked when DM is sampled H I GH along with that input data
during a WRITE access. DM is sampled on both edges of DQS.
Although DM pins are inpu t only, the DM loading matche s the DQ
and DQS loading. For the x16, LDM corresponds to the data on DQ0­DQ7; UDM corresponds to the data on DQ8-DQ15.

Vref Input SSTL_2 reference voltage.

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Preliminary

M2S28D20/ 30/ 40A TP

128M Double Data Rate Synchronous DRAM

BASIC FUNCTIONS

The M2S28D20/30/40ATP provides basic functions, bank (row) activate, burst read / write, bank
(row) precharge, and auto / self refresh. Each command is defined by control signals of /RAS,
/CAS and /WE at CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip
select, refresh option, and precharge option, respectively. To know the detailed definition of
commands, please see the command truth table.

/CLK

CLK

/CS
/RAS
/CAS
/WE
CKE
A10

Chip Select : L=select, H=deselect
Command
Command
Command
Refresh Option @refresh command
Precharge Option @precharge or read/write command

define basic commands

Activate (ACT) [/RAS =L, /CAS =/WE =H]

ACT command activates a row in an idle bank indicated by BA.

Read (READ) [/RAS =H, /CAS =L, /WE =H]

READ command starts burst read from the active bank indicated by BA. First output data appears after
/CAS latency. When A10 =H at this command, the bank is deactivated after the burst read (auto­precharge,

READA)

Write (WRITE) [/RAS =H, /CAS =/WE =L]

WRITE command starts burst write to the active bank indicated by BA. Total data length to be written
is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write
(auto-precharge,

WRITEA)

.

Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]

PRE command deactivates the active bank indicated by BA. This command also terminates burst read
/write operation. When A10 =H at this command, all banks are deactivated (precharge all,

PREA

).

Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H]

REFA command starts auto-refresh cycle. Refresh address including bank address are generated
internally. After this command, the banks are precharged automatically.

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Preliminary

COMMAND TRUTH TABLE

COMMAND MNEMONIC

Deselect

No Operation

Row Address Entry &

Bank Activate

Single Bank Precharge

Precharge All Banks

Column Address Entry

& Write

Column Address Entry

& Write with

Auto-Precharge

Column Address Entry

& Read

Column Address Entry

& Read with

Auto-Precharge

DESEL HXHXXXXXX

NOP HXLHHHXXX

ACT HHLLHHVVV

PRE HHLLHLVLX

PREA H H L L H L H X

WRITE HHLHLLVLV

WRITEA H H L H L L V H V

READ HHLHL HVLV

READA HHLHLHVHV

CKE

n-1

CKE

n

M2S28D20/ 30/ 40A TP

128M Double Data Rate Synchronous DRAM

A10

/CS /RAS /CAS /WE BA0,1

X

A0-9,

/AP

note

11

Auto-Refresh REFA H H L L L H X X X

Self-Refresh Entry REFS H L L L L H X X X

Self-Refresh Exit REFSX

Burst Terminate TERM H H L H H L X X X

Mode Register Set MRS HHLLLLLLV

H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number

NOTE:

1. Applies only to read bursts with autoprecharge disabled; this command is undefined (and should not be used) for
read bursts with autoprecharge enabled, and fo r write bursts.

BA0-BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0=1 ,

2.

BA1 = 0 selects Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A11 provide the
op-code to be written to the selected Mode Register.

LHHXXXXXX
LHLHHHXXX

1
2

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Preliminary

M2S28D20/ 30/ 40A TP

128M Double Data Rate Synchronous DRAM

FUNCTION TRUTH TABLE

Current S tate /CS /RAS /CAS /WE Addr ess Command Action Notes

IDLE H X X X X DESEL NOP

LH HHX NOP NOP
L H H L BA TERM ILLEGAL 2
L H L X BA, CA, A10 READ / WRITE ILLEGAL 2
L L H H BA, RA ACT Bank Active, Latch RA
L L H L BA, A10 PRE / PREA NOP 4
LL LHX REFA Auto-Refresh 5

LL LL

RO W ACTIVE H X X X X DESEL NOP

LH HHX NOP NOP
L H H L BA TERM NOP

L H L H BA, CA, A10 READ / READA

L H L L BA, CA, A10 WRITE / WRITEA
L L H H BA, RA ACT Bank Active / ILLEGAL 2

L L H L BA, A10 PRE / PREA Precharge / Precharge All
L L L H X REFA ILLEGAL

LL LL

READ(Auto-

Precharge

Disabled)

H X X X X DESEL NOP (Continue Burst to END)

L H H H X NOP NOP (Continue Burst to END)
L H H L BA TERM Terminate Burst

L H L H BA, CA, A10 READ / READA

L H L L BA, CA, A10 WRITE / WRITEA ILLEGAL
L L H H BA, RA ACT Bank Active / ILLEGAL 2
L L H L BA, A10 PRE / PREA Terminate Burst, Precharge
L L L H X REFA ILLEGAL

LL LL

Op-Code, Mode­Add

Op-Code, Mode­Add

Op-Code, Mode­Add

MRS Mode Registe r Set 5

Begin Read, Latch CA, Determine
Auto-Precharge
Begin Wr it e, Latch CA, Det ermine
Auto-Precharge

MRS ILLEGAL

Terminate Burst, La tch CA, Begin
New Read, Determin e Auto­Precharge

MRS ILLEGAL

3

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DDR SDRAM (Rev.0.1)

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Preliminary

M2S28D20/ 30/ 40A TP

128M Double Data Rate Synchronous DRAM

FUNCTION TRUTH TABLE (continued)

Current State /CS /RAS /CAS /WE Address Command Action Notes

WRITE(Auto-

Precharge

Disabled)

READ with

Auto- P recharge

WRITE with

Auto- P recharge

H X X X X DESEL NOP (Continue Burst to END)
L H H H X NOP NOP (Continue Burst to END)
L H H L BA TERM ILLEGAL

L H L H BA, CA, A10 READ / READA

L H L L BA, CA, A10 WRITE / WRITEA
L L H H BA, RA ACT Bank Active / ILLEGAL 2

L L H L BA, A10 PRE / PREA Terminate Burst, Precharge
L L L H X REFA ILLEGAL

LL LL
H X X X X DESEL NOP (Continue Burst to END)

L H H H X NOP NOP (Continue Burst to END)
L H H L BA TERM ILLEGAL
L H L H BA, CA, A10 READ / READA ILLEGAL

L H L L BA, CA, A10 WRITE / WRITEA ILLEGAL
L L H H BA, RA ACT Bank Active / ILLEGAL 2

L L H L BA, A10 PRE / PREA Precharge / ILLEGAL 2
L L L H X REFA ILLEGAL

LL LL
H X X X X DESEL NOP (Continue Burst to END)

L H H H X NOP NOP (Continue Burst to END)
L H H L BA TERM ILLEGAL
L H L H BA, CA, A10 READ / READA ILLEGAL

L H L L BA, CA, A10 WRITE / WRITEA ILLEGAL
L L H H BA, RA ACT Bank Active / ILLEGAL 2

L L H L BA, A10 PRE / PREA Precharge / ILLEGAL 2
L L L H X REFA ILLEGAL

LL LL

Op-Code, Mode­Add

Op-Code, Mode­Add

Op-Code, Mode­Add

MRS ILLEGAL

MRS ILLEGAL

MRS ILLEGAL

Terminate Burst, Latch CA, Begin
Read, Determine Auto-Precharge
Terminate Burst, Latch CA, Begin
Write, Determine Auto-Precharge

3

3

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DDR SDRAM (Rev.0.1)

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Preliminary

M2S28D20/ 30/ 40A TP

128M Double Data Rate Synchronous DRAM

FUNCTION TRUTH TABLE (continued)

Current State /CS /RA S /CAS /WE Address Command Action Notes

PRE-

CHARGING

ROW

ACTIVATING

WRITE RE-

COVERING

H X X X X DESEL NOP (Idle after tRP)
L H H H X NOP NOP (Idle after tRP)
L H H L BA TERM ILLEGAL 2
L H L X BA, CA, A10 READ / WRITE ILLEGAL 2

L L H H BA, RA ACT ILLEGAL 2
L L H L BA, A10 PRE / PREA NOP (Idle after tRP) 4
L L L H X REFA ILLEGAL

LL LL
H X X X X DESEL NOP (Row Active after tRCD)

L H H H X NOP NOP (Row Active after tRCD )
L H H L BA TERM ILLEGAL 2
L H L X BA, CA, A10 READ / WRITE ILLEGAL 2

L L H H BA, RA ACT ILLEGAL 2
L L H L BA, A10 PRE / PREA ILLEGAL 2
L L L H X REFA ILLEGAL

LL LL
H X X X X DESEL NOP

L H H H X NOP NOP
L H H L BA TERM ILLEGAL 2
L H L X BA, CA, A10 READ / WRITE ILLEGAL 2

L L H H BA, RA ACT ILLEGAL 2
L L H L BA, A10 PRE / PREA ILLEGAL 2
L L L H X REFA ILLEGAL

LL LL

Op-Code, Mode­Add

Op-Code, Mode­Add

Op-Code, Mode­Add

MRS ILLEGAL

MRS ILLEGAL

MRS ILLEGAL

MITSUBISHI ELECTRIC

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DDR SDRAM (Rev.0.1)

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Preliminary

M2S28D20/ 30/ 40A TP

128M Double Data Rate Synchronous DRAM

FUNCTION TRUTH TABLE (continued)

Current State /CS /RAS /CAS /WE Address Command Action Notes

REFRESHING H X X X X D ESEL NOP (Idle aft er tRC)

L H H H X NOP NOP (Idle after tR C)
L H H L BA TERM ILLEGAL
L H L X BA, CA, A10 READ / WRITE ILLEGAL

L L H H BA, RA ACT ILLEGAL
L L H L BA, A10 PRE / PR EA ILLEGAL
L L L H X REFA ILLEGAL

Op-Code, Mode­Add

Op-Code, Mode­Add

MRS ILLEGAL

MRS ILLEGAL

MODE

REGISTER

SE TTING

LL LL
H X X X X DESEL NOP (Row Active after tRSC)

L H H H X NOP NOP (Row Activ e after tRSC)
L H H L BA TERM ILLEGAL
L H L X BA, CA, A10 READ / WRITE ILLEGAL

L L H H BA, RA ACT ILLEGAL
L L H L BA, A10 PRE / PR EA ILLEGAL
L L L H X REFA ILLEGAL

LL LL

ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No Operation

NOTES:

1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.

2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of
that bank.

3. Must satisfy bus contention, bus turn around, write recovery requirements.

4. NOP to bank precharging or in idle state. May precharge bank indicated by BA.

5. ILLEGAL if any bank is not idle.

ILLEGAL = Device operation and/or data-integrity are not guaranteed.

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DDR SDRAM (Rev.0.1)

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Preliminary

FUNCTION TRUTH TABLE for CKE

Current State CKE n-1 CKE n /CS /RAS /CAS /WE Address Action Notes

SELF-

REFRESHING

POWER

DOWN

ALL BANKS

IDLE

H XXXXXXINVALID 1

L HHXXXXExit Self-Refresh (Idle after tRC) 1

L H L H H H X Exit Self-Refresh (Idle after tRC) 1

L H L H H L X ILLEGAL 1

L HLHLXXILLEGAL 1

L H L L X X X ILLEGAL 1

L L XXXXXNOP (Maintain Self-Refresh) 1

H XXXXXXINVALID

L HXXXXXExit Power Down to Idle

L L XXXXXNOP (Maintain Self-Refresh)

H HXXXXXRefer to Function Truth Table 2

H L L L L H X Enter Self-Refresh 2

M2S28D20/ 30/ 40A TP

128M Double Data Rate Synchronous DRAM

H L HXXXXEnter Power Down 2

H L L H H H X Enter Power Down 2

H L L H H L X ILLEGAL 2

H L LHLXXILLEGAL 2

H L L L X X X ILLEGAL 2

L XXXXXXRefer to Current State =Power Down2

ANY STATE

other than listed

above

H HXXXXXRefer to Function Truth Table

H L XXXXXBegin CLK Suspend at Next Cycle 3

L HXXXXXExit CLK Suspend at Next Cycle 3

L L XXXXXMaintain CLK Suspend

ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care

NOTES:

1. CKE Low to High transition will re -enable CLK and other inputs asynchronously..
A minimum setup time must be satisfied before any command other than EXIT.

2. Power-Down and Self-Refresh can be entered only from the All Banks Idle State.

3. Must be legal command.

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Preliminary

SIMPLIFIED STATE DIAGRAM

POWER
APPLIED

POWER

ON

PREA

MODE

REGISTER

SET

PRE

CHARGE

ALL

MRS

MRS

Active
Power

Down

M2S28D20/ 30/ 40A TP

128M Double Data Rate Synchronous DRAM

SELF

REFRESH

REFS

REFSX

AUTO

REFRESH

POWER

DOWN

CKEL

IDLE

ACT

REFA

CKEL

CKEH

CKEH

ROW

ACTIVE

WRITE

WRITEA READA

WRITE READ

WRITEA

WRITE

WRITEA

PRE PRE

READ

PRE

PRE

CHARGE

READA

READ

READA

READA

BURST

STOP

READ

TERM

MITSUBISHI ELECTRIC

Automatic Sequence
Command Sequence

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M2S28D20/ 30/ 40A TP

128M Double Data Rate Synchronous DRAM

POWER ON SEQUENCE

Before starting normal operation, the following power on sequence is necessary to prevent a
SDRAM from damaged or multifunctioning.

1. Apply VDD before or the same time as VDDQ

2. Apply VDDQ before or at the same time as VTT & Vref

3. Maintain stable condition for 200us after stable power and CLK, apply NOP or DSEL

4. Issue precharge command for all banks of the device

5. Issue EMRS

6. Issue MRS for the Mode Register and to reset the DLL

7. Issue 2 or more Auto Refresh commands

8. Maintain stable condition for 200 cycle
After these sequence, the DDR SDRAM is idle state and ready for normal operation.

MODE REGISTER

Burst Length, Burst Type and /CAS Latency can be
programmed by setting the mode register (MRS). The mode
register stores these data until the next MRS command, which
may be issued when both banks are in idle state. After tRSC from
a MRS command, the DDR SDRAM is ready for new command.

CLK
/CLK

/CS
/RAS
/CAS
/WE

BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

00000DR0 BT

CL

000 R
001 R

010 2

Latency

Mode

DLL Re se t

011 R
100 R

101 R
110 2.5
111 R

0NO
1YES

LTMODE BL

/CAS Latency

Burst

Le ngth

Burst T ype

R: Reserved for Future Use

BA0
BA1

A11-A0

BL

000 R R
001 2 2

010 4 4
011 8 8

100 R R
101 R R
110 R R

111 R R

BT=0 BT=1

0 Sequential
1 Interleaved

V

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M2S28D20/ 30/ 40A TP

128M Double Data Rate Synchronous DRAM

EXTENDED MODE REGISTER

DLL disable / enable mode can be programmed by setting the extended
mode register (EMRS). The extended mode register stores these data
until the next EMRS command, which may be issued when all banks are
in idle state. After tRSC from a EMRS command, the DDR SDRAM is
ready for new command.

BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

00000000000

QFC DS DD

DLL Disable

CLK
/CLK

/CS
/RAS

/CAS
/WE

BA0
BA1

A11-A0

V

0 DLL Enable
1 DLL Disable

QFC

Drive

Strength

0Normal
1Weak

0Disable
1Enable

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14

DDR SDRAM (Rev.0.1)

MITSUBISHI LSIs

Jun,'00

Command

Initial Address BL

A2 A1 A0

Preliminary

/CLK

CLK

Address

DQS

DQ

CL= 2
BL= 4

M2S28D20/ 30/ 40A TP

128M Double Data Rate Synchronous DRAM

Read Write

YY

Q0 Q1 Q2 Q3 D0 D1 D2 D3

/CAS
Latency

Burst
Length

Column Addressing

Sequential Interleaved

Burst
Length

000

001
010

011

100
101

110

111

-00

-01

-10

-11

--0

--1

0123456701234567

1234567010325476
2345670123016745

3456701232107654

8

4567012345670123
5670123454761032

6701234567452301

7012
0123

1230

4

2301
30

01

2

10

3456 3210

12

7654
0123

1032

2301
32

01
10

10

MITSUBISHI ELECTRIC

15

DDR SDRAM (Rev.0.1)

pply

pply

p

g

p

p

p

g

y

MITSUBISHI LSIs

Jun,'00

Preliminary

M2S28D20/ 30/ 40A TP

128M Double Data Rate Synchronous DRAM

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Condition s Ratings Unit

Vdd Supply Voltage w ith res pect t o Vs s -0. 5 ~ 3.7 V

VddQ Supply Volta ge for Output with respect to VssQ -0.5 ~ 3.7 V

VI Input Voltage with re spec t t o Vs s - 0.5 ~ Vdd+0. 5 V

VO Output Volta ge with re spect to VssQ - 0.5 ~ VddQ+0.5 V

IO O utput Current 50 mA
Pd Power Dissipation

Topr Operating Temperature 0 ~ 70

Ts t g S t ora ge Tempe rature -65 ~ 150

Ta = 25

o

C

1000 mW

DC OPERATING CONDITIONS

(Ta=0 ~ 70oC, unless otherwise noted)

o

C

o

C

S

mbol P a rame ter U nit

Vdd Su

VddQ Su

Vref In

VIH(DC) Hi

VIL(DC) Low-Level In
VIN(DC) In
VID(DC) In

V TT I / O Te r m in at io n V olt a

ut D iffe re ntial V oltage, CL K a nd /C L K 0.36 V ddQ + 0.6 V 7

ut R efe re nc e V o ltage 0.49*V ddQ 0.50*V ddQ 0.51*V ddQ V 5

h-L eve l Input V oltage Vref + 0.18 V ddQ + 0.3 V

ut V oltage L eve l, C L K and /C LK -0.3 V ddQ + 0.3 V

Voltage 2.3 2.5 2.7 V

Voltage for Output 2.3 2.5 2.7 V

ut V oltage -0.3 V re f - 0.18 V

e Vref - 0.04 Vref + 0.04 V 6

Min. Typ.Max.

Limits

CAPACITANCE

(Ta=0 ~ 70oC, Vdd = VddQ = 2.5V + 0.2V, Vss = VssQ = 0V, unless otherwise noted)

Symbol Pa ra meter Test Condition Unit

Limits

Min . Max.
CI(A) Input Capacitance, address pin 2.0 3.0 pF 11
CI(C) Input Ca pac itance, control pin VI=1.25v 2.0 3.0 pF 11

Delta

Cap.(Max.)

0.50

Notes

Note s

CI(K) Input Capacitance, CLK pin f=100MHz 2.0 3.0 0.25 pF 11

CI/O I/O Capacitance, I/O, DQS, DM pin V I=25mVrms 4.0 5. 0 pF 11

0.50

CO( QF) Out put C apacitance, /QFC 2. 0 3.0 pF 11

MITSUBISHI ELECTRIC

16

DDR SDRAM (Rev.0.1)

MITSUBISHI LSIs

Jun,'00

Preliminary

M2S28D20/ 30/ 40A TP

128M Double Data Rate Synchronous DRAM

AVERAGE SUPPLY CURRENT from Vdd

(Ta=0 ~ 70oC, Vdd = VddQ = 2.5V + 0.2V, Vss = VssQ = 0V, Output Open, unless otherwise noted)

Symbol OrganizationParameter/Test Conditions

OPERATING CURRENT: One Bank; Active-Precharge; t RC = t RC MIN; t CK
= t CK MIN; DQ, DM and DQS inputs changing twice per clock cycle; address

IDD0

and control inputs changing once per clock cycle

OPERATING CURRENT: One Bank; Active-Read-Precharge;

IDD1

Burst = 2; t RC = t RC MIN; CL = 2.5; t CK = t CK MIN; IOUT= 0mA;
Address and control inputs changing once per clock cycle

PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; power­down mode; CKE <

IDLE STANDBY CURRENT: /CS > VIH (MIN); All banks idle;

IDD2N

IDD3P

IDD3N

IDD4R

IDD4W

CKE >

VIH (MIN); t CK = t CK MIN; Address and other control inputs changing

once per clock cycle
ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; power-

down mode; CKE <
ACTIVE STANDBY CURRENT: /CS >

bank; Active-Precharge; t RC = t RAS MAX; t CK = t CK MIN; DQ,DM and
DQS inputs changing twice per clock cycle; address and other control inputs
changing once per clock cycle

OPERATING CURRENT: Burst = 2; Reads; Continuous burst;One bank active;
Address and control inputs changing once per clock cycle;CL=2.5; t CK = t CK
MIN; IOUT = 0 mA

OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank active;
Address and control inputs changing once per clock cycle; CL=2.5; t CK = t CK
MIN;DQ, DM and DQS inputs changing twice per clock cycle

IDD5 AUTO REFRESH CURRENT: t RC = t RFC (MIN) x4/x8/x16 190 180

VIL (MAX); t CK = t CK MIN

VIL (MAX); t CK = t CK MIN

VIH (MIN); CKE > VIH (MIN); One

x4 105 95
x8 110 105

x16 120 115

x4 110 100
x8 115 110

x16 135 130

x4/x8/x16 IDD2P

x4/x8/x16

x4/x8/x16 40 40

x4 60 55
x8 65 60

x16 75 70

x4 150 140
x8 170 160

x16 210 200

x4 145 135
x8 165 155

x16 200 180

Limits(Max.)

-75 -10

20 20

40 40

Uni t Notes

mA

IDD6 SELF REFRESH CURRENT: CKE <

0.2V x4/x8/x16 3 3 9

AC OPERATING CONDITIONS AND CHARACTERISTICS

(Ta=0 ~ 70oC, Vdd = VddQ = 2.5V + 0.2V, Vss = VssQ = 0V, Output Open, unless otherwise noted)

Sym b ol P ar a m e t e r / T e st C o n d it io ns U n it

Min. Max.
VIH(AC) High- Leve l Input V o ltage (AC ) Vref + 0.35
VIL(AC ) Low-Level Input V o ltage (AC ) Vref - 0 .35
VID(AC) Input D ifferential Vo ltage, C LK and /C LK 0.7 VddQ + 0.6 7
VIX(AC) Input C ro ssing P o in t Volt age, CLK and /CLK 0.5*VddQ - 0.2 0.5*VddQ + 0.2 8
IO Z Off- s ta te O u tput Current /Q flo a ting Vo=0~VddQ -5 5
II Input C urrent / VIN=0 ~ VddQ -2 2
IOH O utput H igh C urrent (VO UT = 1.95 V) -16.8
IOL O utput H igh C urrent (VO UT = 0.35 V) 16.8

MITSUBISHI ELECTRIC

Limits

V
V
V
V

µ
µ

mA
mA

A
A

Notes

17

DDR SDRAM (Rev.0.1)

MITSUBISHI LSIs

Jun,'00

Preliminary

M2S28D20/ 30/ 40A TP

128M Double Data Rate Synchronous DRAM

AC TIMING REQUIREMENTS

(Ta=0 ~ 70oC, Vdd = VddQ = 2.5V +0.2V, Vss = VssQ = 0V, unless otherwise noted)

Symbol AC Characteristics Parameter

tAC DQ Output Valid data delay time from CLK//CLK -0.75 0.75 -0.8 0.8 ns

tDQSCK DQ Output Valid data delay time from CLK//CLK -0.75 0.75 -0.8 0.8 ns

tCH CLK High level width 0.45 0.55 0.45 0.55 ns
tCL CLK Low level width 0.45 0.55 0.45 0.55 ns

tCK CLK cycle time

tDH Input Setup time (DQ,DM ) 0.5 0.6 ns
tDS Input Hold time(DQ, DM) 0.5 0.6 ns

tDIPW DQ and DM inpu t pulse width (for each input) 1.75 2 ns

tHZ Data-out-high impedance time from CLK//CLK -0.75 0.75 -0.8 0.8 ns 14

tLZ Data-out-low impedance time from CLK//CLK -0.75 0.75 -0.8 0.8 ns 14

tDQSQ DQ Valid data delay time from DQS -0.5 0.5 -0.6 0.6 ns

-75

Min. Max Min. Max

7.515815ns
10 15 10 15 ns

-10
Unit Notes

tHP Clock half period

tQH Output DQS valid window tHP-0.75 tHP-1.0 ns
tDQSS Write command to first DQS latching t ransi tion 0.75 1.25 0.75 1.25 tCK
tDQSH DQS input High level width 0.35 0.35 tCK
tDQSL DQS input Low level width 0.35 0.35 tCK

tDSS DQS falling edge to CLK setup time 0.2 0.2 tCK

tDSH D Q S falling edge hold time from CLK 0.2 0.2 tCK

tMRD Mode Register Set command cycle time 15 15 ns

tWPRES Write preamble setup time 0 0 ns 16

tWPST Write postamble 0.4 0.6 0.4 0.6 tCK 15
tWPRE Write pr eamble 0.25 0.25 tCK

tIS Input Setup time (ad dress and cont rol) 0.9 1.2 ns 19

tIH Input Hold time (address and control) 0.9 1.2 ns 19
tRPST Read postamble 0.4 0.6 0.4 0.6 tCK
tRPRE Read preamble 0.9 1.1 0.9 1.1 tCK
tQPST /QFC postamble during reads 0.4 0.6 0.4 0.6 tCK
tQPRE /QFC preambl e during reads 0.9 1.1 0.9 1.1 tCK

tQCK /QFC output access time from CLK//CLK, for write 4 4 ns
tQOH /QFC output hold time for writes 1.25 2 1.25 2 ns

tCLmin or
tCHmin

tCLmin or
tCHmin

ns

MITSUBISHI ELECTRIC

18

DDR SDRAM (Rev.0.1)

µ

MITSUBISHI LSIs

Jun,'00

Preliminary

M2S28D20/ 30/ 40A TP

128M Double Data Rate Synchronous DRAM

AC TIMING REQUIREMENTS(Continues)

(Ta=0 ~ 70oC, Vdd = VddQ = 2.5V +0.2V, Vss = VssQ = 0V, unless otherwise noted)

-75

Mi n. Max Min. Max

tRAS Row Active time 45 120,000 50 120,000 ns

tRC Row Cycle time(operation) 65 70 ns
tRFC Auto Ref. t o Active/Auto Ref. command period 75 80 ns
tRCD Row to Column Delay 20 20 ns

tRP Row Precharge time 20 20 ns

tRRD Act to Act Delay time 15 15 ns

tWR Write Recovery time 15 15 ns
tDAL Auto Precharge write recovery + precharge time 35 35 ns
tWT R Inter nal Write to Read Command Delay 1 1 tCK

tXSNR Exit Self Ref. to non-Read command 75 80 ns
tXSRD Exit Self Ref. to -Read command 200 200 tCK
tXPNR Exit Power down to command 1 1 tCK
tXPRD Exit Power down to -Read co mmand 1 1 tCK 18

tREFI Average Periodic Refresh interval 15.6 15.6

-10
Unit N otesSymbol AC Characteristics Parame ter

s17

Output Load Condition

V

TT=VREF

V

OUT

Zo=50

Ω

30pF

V

DQS

REF

DQ

50

Ω

V

REF

V

REF

Output Timing
Measurement
Reference Point

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DDR SDRAM (Rev.0.1)

MITSUBISHI LSIs

Jun,'00

Preliminary

M2S28D20/ 30/ 40A TP

128M Double Data Rate Synchronous DRAM

Notes

1. All voltages referenced to Vss.

2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply
voltage levels, but the related specifications and device operation are guar anteed for the full voltage range specified.

3. AC timing and IDD tests may u se a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still
referenced to VREF (or to the crossing point for CK//CK), and parameter specifications are guaranteed for the
specified AC input levels under n ormal use conditions. The minimum slew rate for the input signals is 1V/ns in the
range between VIL(AC) and VIH(AC).

4. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiv er will effectively
switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not
ring back above (below) the DC input LOW (HIGH) level.

5. VREF is expected to be equal to 0.5*VddQ of the transmitting device, and to track variations in the DC lev e l of the
same. Peak-to-peak noise on VREF may not exceed

6. VTT is not applied directly to the device. VTT is a system supply for signal termina tion resistors, is expected to be
set equal to VREF, and must track variations in the DC level of VREF.

7. VID is the magnitude of the difference between the input level on CLK an d the input level on /CLK.

8. The value of VIX is expected to equal 0.5*VddQ of the transmitting device and must track variations in the DC level
of the same.

9. Enables on-chip refresh and address counters.

10. IDD specifications ar e tested after the device is p r operly initialized.

11. This parameter is sample d. VddQ = 2.5V
VddQ/2, VOUT(PEAK TO PEAK) = 25mV. DM inputs are grouped with I/O pins - reflecting the fact that they are
matched in loading (to facilitate trace matching at the board level).

12. The CLK//CLK input reference level (for timing referenced to CLK//CLK) is the point at which CLK and /CLK
cross; the input reference level for signals other tha n CLK//CLK, is VREF.

13. Inputs are not recognized as valid until VREF stabilizes. Exception: during the pe riod before VREF stabilizes,
CKE

< 0.3VddQ is recognized as LOW.

14. t HZ and tLZ transitions occur in the sa me access time windows as valid data transitions. These parameters are not
referenced to a specific voltage level, but specify when the device output is no longer driving (HZ), or begins driving
(LZ).

15. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this
parameter, but system performance (bus turnaround) will degrade accordingly.

16. The specific requiremen t is that D Q S be valid (HIGH, LOW, or at some point on a valid transition) on or before
this CLK edge. A valid transition is defined as monotonic, and meeting the inpu t slew rate specifications of the device.
When no writes were previously in progress on the bus, DQS will be transitioning from High-Z to logic LOW . If a
previous write was in prog r ess, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time,
depending on tDQSS.

17. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.

18. tXPRD should be 200 tCLK in the condition of the unstable CLK operation during the power down mode.

19. For command/address and CK & /CK slew rate > 1.0V/ns.

+2% of the DC value.

+0.2V, Vdd = 2.5V + 0.2V , f = 100 MHz, Ta = 25oC, VOUT(DC) =

MITSUBISHI ELECTRIC

20

DDR SDRAM (Rev.0.1)

MITSUBISHI LSIs

Jun,'00

Preliminary

Read Operation

/CLK

CLK

Cmd &

Add.

DQS

/QFC

DQ

tRPRE

tQPRE

tDQSCK

tQH

M2S28D20/ 30/ 40A TP

128M Double Data Rate Synchronous DRAM

tCLtCHtCK

tIS tIH

Valid Data

tRPST

tQPST
tDQSQ

tAC

VREF

Write Operation / tDQSS=max.

/CLK

CLK

tDQSS

tWPRES

DQS

tQCK

/QFC

tWPRE

DQ

Write Operation / tDQSS=min.

/CLK

CLK

DQS

/QFC

tDQSS

tWPRES

tQCK

tWPRE

tDSS

tDQSL tDQSH

tDS tDH

tDSH

tDQSL tDQSH

tWPST

tQOH(min)

tWPST

tQOH(max)

DQ

tDS tDH

MITSUBISHI ELECTRIC

21

DDR SDRAM (Rev.0.1)

MITSUBISHI LSIs

Jun,'00

Preliminary

M2S28D20/ 30/ 40A TP

128M Double Data Rate Synchronous DRAM

OPERATIONAL DESCRIPTION

BANK ACTIVATE

The DDR SDRAM has four independent banks. Each bank is activated by the ACT command with
the bank addresses (BA0,1). A row is indicated by the row address A11-0. The minimum activation
interval between one bank and the other bank is tRRD. Maximum 2 ACT commands are allowed
within tRC,although the number of banks which are active concurrently is not limited.

PRECHARGE

The PRE command deactivates the bank indicated by BA0,1. When multiple banks are active, the
precharge all command (PREA,PRE+A10=H) is available to deactivate them at the same time. After
tRP from the precharge, an ACT command to the same bank can be issued.

Bank Activation and Precharge All (BL=8, CL=2)

/CLK

CLK

2 ACT command / tRCmin

tRCmin

Command

A0-9,11

ACT

tRRD

Xa

tRCD

ACT

Xb

READ

Y

tRAS

BL/2

PRE

ACT

tRP

Xb

A10

BA0,1

DQS

DQ

Xa

00

Xb

01

0

00

Qa0

Qa1 Qa2 Qa3 Qa4 Qa5 Qa6 Qa7

1

Precharge all

Xb

01

A precharge command can be issued at BL/2 from a read command without data loss.

MITSUBISHI ELECTRIC

22

DDR SDRAM (Rev.0.1)

MITSUBISHI LSIs

Jun,'00

Preliminary

M2S28D20/ 30/ 40A TP

128M Double Data Rate Synchronous DRAM

READ

After tRCD from the bank activation, a READ command can be issued. 1st Output data is available
after the /CAS Latency from the READ, followed by (BL-1) consecutive data when the Burst Length
is BL. The start address is specified by A11,A9-A0(x4)/A9-A0(x8)/A8-A0(x16), and the address
sequence of burst data is defined by the Burst Type. A READ command may be applied to any
active bank, so the row precharge time (tRP) can be hidden behind continuous output data by
interleaving the multiple banks. When A10 is high at a READ command, the auto-precharge
(READA) is performed. Any command(READ,WRITE,PRE,ACT) to the same bank is inhibited till
the internal precharge is complete. The internal precharge starts at BL/2 after READA. The next
ACT command can be issued after (BL/2+tRP) from the previous READA.

Multi Bank Interleaving READ (BL=8, CL=2)

/CLK

CLK

Command

A0-9,11

A10

BA0,1

DQS

DQ

ACT

Xa

Xa

00

tRCD

READ

Y

0

00

/CAS latency

ACT

Xb

Xb

10

READ

Qa0

Qa1 Qa2 Qa3 Qa4 Qa5 Qa6 Qa7 Qb0 Qb1 Qb2 Qb3 Qb4 Qb5 Qb7 Qb8

Burst Length

Y

0

10

PRE

0

00

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DDR SDRAM (Rev.0.1)

MITSUBISHI LSIs

Jun,'00

Command

A0-9,11

Preliminary

/CLK

CLK

A10

BA0,1

DQS

DQ

128M Double Data Rate Synchronous DRAM

READ with Auto-Precharge (BL=8, CL=2)

ACT

Xa

Xa

00

READ

tRCD tRP

Y

1

00

BL/2

Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 Qa6 Qa7

Internal precharge start

M2S28D20/ 30/ 40A TP

BL/2 + tRP

ACT

Xb

Xb

00

Command

CL=2.5

/CLK

CLK

DQ

DQCL=2

READ Auto-Precharge Timing (BL=8)

ACT READ

BL/2

Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 Qa6 Qa7

Qa0

Qa1 Qa2 Qa3 Qa4 Qa5 Qa6 Qa7

Internal Precharge Start Timing

MITSUBISHI ELECTRIC

24

DDR SDRAM (Rev.0.1)

MITSUBISHI LSIs

Jun,'00

Preliminary

M2S28D20/ 30/ 40A TP

128M Double Data Rate Synchronous DRAM

WRITE

After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set from
the WRITE command with data strobe input, following (BL-1) data are written into RAM, when
the Burst Length is BL. The start address is specified by A11,A9-A0(x4)/A9-A0(x8)/A8-A0(x16),
and the address sequence of burst data is defined by the Burst Type. A WRITE command may be
applied to any active bank, so the row precharge time (tRP) can be hidden behind continuous input
data by interleaving the multiple banks. From the last data to the PRE command, the write recovery
time (tWRP) is required. When A10 is high at a WRITE command, the auto-precharge(WRITEA) is
performed. Any command(READ,WRITE,PRE,ACT) to the same bank is inhibited till the internal
precharge is complete. The next ACT command can be issued after tDAL from the last input data
cycle.

Multi Bank Interleaving WRITE (BL=8)

/CLK

CLK

Command

A0-9,11

ACT

Xa Ya YbXb

WRITE

tRCD

D

ACT

tRCD

D

WRITE

PRE

PRE

A10

BA0,1

DQS

DQ

/CLK

CLK

Command

A0-9,11

A10

BA0,1

DQS

DQ

0 0

Xa 0

Xa

00

Xb

00

10

Da0 Da1 Da2 Da3 Da4 Da5 Da6 Da7 Db0 Db1 Db2 Db3

10

00

Db4 Db5 Db6 Db7

WRITE with Auto-Precharge (BL=8)

ACT

Xa Y Xb

Xa

00

tRC

D

WRITE

1

00

Da0

Da1 Da2 Da3 Da4 Da5 Da6 Da7

tDAL

0

10

ACT

Xb

00

MITSUBISHI ELECTRIC

25

DDR SDRAM (Rev.0.1)

MITSUBISHI LSIs

Jun,'00

Preliminary

M2S28D20/ 30/ 40A TP

128M Double Data Rate Synchronous DRAM

BURST INTERRUPTION

[Read Interrupted by Read]

Burst read operation can be interrupted by new read of any bank. Random column access is allowed.
READ to READ interval is minimum 1CLK.

Read Interrupted by Read (BL=8, CL=2)

/CLK

CLK

Command

A0-9,11

A10

BA0,1

READ READ READ READ

Yi

Yj Yk Yl

0000

00 1000 01

DQS

DQ

Qai0 Qai1 Qaj0 Qaj1 Qaj2 Qaj3 Qak0 Qak1 Qak2 Qak3 Qak4 Qak5 Qal0 Qal1 Qal2 Qal3 Qal4 Qal5 Qal6 Qal7

[Read Interrupted by precharge]

Burst read operation can be interrupted by precharge of the same bank. READ to PRE interval is
minimum 1 CLK. A PRE command to output disable latency is equivalent to the /CAS Latency.
As a result, READ to PRE interval determines valid data length to be output. The figure below
shows examples of BL=8.

Read Interrupted by Precharge (BL=8)

/CLK

CLK

PREREAD

Q0 Q1 Q2 Q3 Q4 Q5

CL=2.5

Command

DQS

DQ

Command

DQS

READ PRE

DQ

Command

DQS

DQ

Q0 Q1 Q2 Q3

READ PRE

Q0 Q1

MITSUBISHI ELECTRIC

26

DDR SDRAM (Rev.0.1)

MITSUBISHI LSIs

Jun,'00

CL=2.0

Preliminary

Command

Command

Command

/CLK

CLK

DQS

DQ

DQS

DQ

DQS

DQ

M2S28D20/ 30/ 40A TP

128M Double Data Rate Synchronous DRAM

Read Interrupted by Precharge (BL=8)

PREREAD

Q0 Q1 Q2 Q3 Q4 Q5

READ

READ PRE

PRE

Q0 Q1 Q2 Q3

Q0 Q1

MITSUBISHI ELECTRIC

27

DDR SDRAM (Rev.0.1)

MITSUBISHI LSIs

Jun,'00

Preliminary

M2S28D20/ 30/ 40A TP

128M Double Data Rate Synchronous DRAM

[Read Interrupted by Burst Stop]

Burst read operation can be interrupted by a burst stop command(TERM). READ to TERM interval
is minimum 1 CLK. A TERM command to output disable latency is equivalent to the /CAS Latency.
As a result, READ to TERM interval determines valid data length to be output. The figure below
shows examples of BL=8.

Read Interrupted by TERM (BL=8)

/CLK

CLK

Command

DQS

DQ

Command

READ

READ

TERM

Q0 Q1 Q2 Q3 Q4 Q5

TERM

CL=2.5

CL=2.0

DQS

DQ

Command

DQS

DQ

Command

DQS

DQ

Command

DQS

DQ

Command

DQS

READ

READ

READ

READ

Q0 Q1 Q2 Q3

TERM

Q0 Q1

TERM

Q0 Q1 Q2 Q3 Q4 Q5

TERM

Q0 Q1 Q2 Q3

TERM

DQ

Q0 Q1

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28

DDR SDRAM (Rev.0.1)

MITSUBISHI LSIs

Jun,'00

Preliminary

[Read Interrupted by Write with TERM]

Read Interrupted by TERM (BL=8)

/CLK

CLK

READ TERM

READ TERM

CL=2.5

CL=2.0

Command

DQS

DQ

Command

DQS

DQ

M2S28D20/ 30/ 40A TP

128M Double Data Rate Synchronous DRAM

WRITE

Q0 Q1 Q2 Q3

WRITE

Q0 Q1 Q2 Q3

D0 D1 D2 D3 D4 D5

D0 D1 D2 D3 D4 D5 D6 D7

MITSUBISHI ELECTRIC

29

DDR SDRAM (Rev.0.1)

MITSUBISHI LSIs

Jun,'00

Preliminary

M2S28D20/ 30/ 40A TP

128M Double Data Rate Synchronous DRAM

[Write interrupted by Write]

Burst write operation can be interrupted by write of any bank. Random column access is allowed.
WRITE to WRITE interval is minimum 1 CLK.

Write Interrupted by Write (BL=8)

/CLK

CLK

Command

A0-9,11

A10

BA0,1

DQS

WRITE

Yi

0

00

WRITE

Yj

0

00

WRITE

Yk

0

10

WRITE

Yl

0

00

DQ

Dai1 Daj1 Daj3 Dak1 Dak3 Dak5 Dal1

Daj0 Daj2

Dai0

Dal2 Dal3 Dal5 Dal6 Dal7Dal4Dal0Dak4Dak2Dak0

[Write interrupted by Read]

Burst write operation can be interrupted by read of the same or the other bank. Random column
access is allowed. Internal WRITE to READ command interval(tWTR) is minimum 1 CLK. The
input data on DQ at the interrupting READ cycle is "don't care". tWTR is referenced from the first
positive edge after the last data input.

Write Interrupted by Read (BL=8, CL=2.5)

/CLK

CLK

Command

A0-9,11

A10

BA0,1

WRITE

Yi

0

00

READ

Yj

0

00

DM

DQ

tWTR

Dai0 Dai1 Qaj0 Qaj1 Qaj2 Qaj3QSQaj4 Qaj5 Qaj6 Qaj7

MITSUBISHI ELECTRIC

30

DDR SDRAM (Rev.0.1)

MITSUBISHI LSIs

Jun,'00

Preliminary

M2S28D20/ 30/ 40A TP

128M Double Data Rate Synchronous DRAM

[Write interrupted by Precharge]

Burst write operation can be interrupted by precharge of the same or all bank. Random column
access is allowed. tWR is referenced from the first positive CLK edge after the last data input.

Write Interrupted by Precharge (BL=8, CL=2.5)

/CLK

CLK

Command

A0-9,11

A10

BA0,1

DM

WRITE

Yi

0

00

tWR

PRE

00

QS

DQ

Dai0 Dai1

MITSUBISHI ELECTRIC

31

DDR SDRAM (Rev.0.1)

MITSUBISHI LSIs

Jun,'00

Preliminary

[Initialize and Mode Register sets]

/CLK

CLK

CKE

Command

A0-9,11

A10

BA0,1

DQS

DQ

1

M2S28D20/ 30/ 40A TP

128M Double Data Rate Synchronous DRAM

Initialize and MRS

EMRSPRENOP MRS PRE AR AR MRS ACT

Code Code Xa

Code

1 0

Code Xa

0 0

1

Code

0 0

Xa

tMRD tMRD tRP tRFC tRFC tMRD

Extended Mode

Register Set

Mode Register Set,

Reset DLL

[AUTO REFRESH]

Single cycle of auto-refresh is initiated with a REFA(/CS=/RAS=/CAS=L,/WE=CKE=H)
command. The refresh address is generated internally. 4096 REFA cycles within 64ms refresh
128Mbits memory cells. The auto-refresh is performed on 4 banks concurrently. Before performing
an auto refresh, all banks must be in the idle state. Auto-refresh to auto-refresh interval is minimum
tRFC . Any command must not be supplied to the device before tRFC from the REFA command.

Auto-Refresh

/CLK

CLK

/CS

/RAS

/CAS

/WE

NOP or DESELECT

CKE

A0-11

BA0,1

Auto Refresh on All Banks

MITSUBISHI ELECTRIC

tRFC

Auto Refresh on All Banks

32

DDR SDRAM (Rev.0.1)

MITSUBISHI LSIs

Jun,'00

Preliminary

M2S28D20/ 30/ 40A TP

128M Double Data Rate Synchronous DRAM

[SELF REFRESH]

Self -refresh mode is entered by issuing a REFS command (/CS=/RAS=/CAS=L,/WE=H,CKE=L).
Once the self-refresh is initiated, it is maintained as long as CKE is kept low. During the self­refresh mode, CKE is asynchronous and the only enable input, all other inputs including CLK are
disabled and ignored, so that power consumption due to synchronous inputs is saved. To exit the
self-refresh, supplying stable CLK inputs, asserting DESEL or NOP command and then asserting
CKE for longer than tXSNR/tXSRD.

Self-Refresh

/CLK

CLK

/CS

/RAS

/CAS

/WE

CKE

A0-11

BA0,1

XY
XY

tXSRD

tXSNR

Self Refresh Exit

MITSUBISHI ELECTRIC

33

DDR SDRAM (Rev.0.1)

MITSUBISHI LSIs

Jun,'00

Preliminary

M2S28D20/ 30/ 40A TP

128M Double Data Rate Synchronous DRAM

[Asynchronous SELF REFRESH]

Asynchronous Self -refresh mode is entered by CKE=L within 2 tCLK after issuing a REFA
command (/CS=/RAS=/CAS=L,/WE=H). Once the self-refresh is initiated, it is maintained as long as
CKE is kept low. During the self-refresh mode, CKE is asynchronous and the only enable input, all
other inputs including CLK are disabled and ignored, so that power consumption due to synchronous
inputs is saved. To exit the self-refresh, supplying stable CLK inputs, asserting DESEL or NOP
command and then asserting CKE for longer than tXSNR/tXSRD.

Asynchronous Self-Refresh

/CLK

CLK

/CS

/RAS

/CAS

/WE

CKE

A0-11
BA0,1

max 2 tCLK

tXSNR

Self Refresh Exit

MITSUBISHI ELECTRIC

34

DDR SDRAM (Rev.0.1)

MITSUBISHI LSIs

Jun,'00

Preliminary

M2S28D20/ 30/ 40A TP

128M Double Data Rate Synchronous DRAM

[Power DOWN]

The purpose of CLK suspend is power down. CKE is synchronous input except during the self­refresh mode. A command at cycle is ignored. From CKE=H to normal function, DLL recovery time
is NOT required in the condition of the stable CLK operation during the power down mode.

Power Down by CKE

/CLK

CLK

CKE

Command

CKE

PRE

NOP

Standby Power Down

Active Power Down

NOP

Valid

tXPNR/tXPRD

Command

ACT

NOP

NOP Valid

[DM CONTROL]

DM is defined as the data mask for writes. During writes,DM masks input data word by word. DM
to write mask latency is 0.

DM Function(BL=8,CL=2)

/CLK

CLK

Command

DM

DQS

DQ

WRITE

D0 D1 D3 D4 D5 D6 D7

READ

Don't Care

Q2 Q3 Q4 Q5

Q0 Q1 Q6

masked by DM=H

MITSUBISHI ELECTRIC

35

DDR SDRAM (Rev.0.1)

MITSUBISHI LSIs

Jun,'00

Preliminary

M2S28D20/ 30/ 40A TP

128M Double Data Rate Synchronous DRAM

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but there is always th e possibility that trouble may occur with them. Trouble with semiconductors may lead to personal
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MITSUBISHI ELECTRIC

36