MITEL SP8854EIGHCAR, SP8854EKGHCAR Datasheet
SP8854E
2·7GHz Parallel Load Professional Synthesiser
Preliminary Information
Supersedes January 1996 version, DS4238 - 1.2 DS4238 - 2.0 June 1998
The SP8854E is one of a family of parallel load synthesisers
containing all the elements apart from the loop amplifier to
fabricate a PLL synthesis loop. Other parts in the series are
the SP8852E which is fully programmable, requiring tw0 16bit words to set the RF and reference counters and the
SP8855E which is fully programmable using hard wired links
or switches.
The SP8854E is programmed using a 16-bit parallel data
bus. Data is stored in an internal buffer. The 10-bit programmable reference divider is programmed by connecting the 10
programming pins either to ground or 15V. The device can
therefore be programmed with a single transfer from the
control microprocessor. Hard wired inputs can also control
the F
and F
PD
outputs and the control sense of the loop.
REF
FEATURES
■ 2·7 GHz Operating Frequency
■ Single 5V Supply
■ Low Power Consumption <1·3W
■ High Comparison Frequency : 20MHz
■ High Gain Phase Detector : 1mA/rad
■ Zero ‘Dead Band’ Phase Detector
■ Wide Range of RF and Reference Division Ratios
■ Programming by Single Word Data Transfer
DATA BIT 4
DATA BIT 3
DATA BIT 2
DATA BIT 1
DATA BIT 0
0V (PRESCALER)
RF INPUT
RF INPUT
(PRESCALER)
V
CC
LOCK DETECT
V
EE
DATA BIT 5
DATA BIT 6
DATA BIT 7
DATA BIT 8
DATA BIT 9
DATA BIT 10
144
SP8854E
SET
R
ENABLE
REF
C-LOCK DETECT
/F
PD
F
CHARGE PUMP REF
CHARGE PUMP OUTPUT
CONTROL DIRECTION
DATA BIT 11
*
PD
F
DATA BIT 12
DATA BIT 13
*
CC
V
REF
F
DATA BIT 14
DATA BIT 15
REF IN/CRYSTAL
REF OSC CAPACITOR
STROBE
REF DIV BIT 0
REF DIV BIT 1
REF DIV BIT 2
REF DIV BIT 3
REF DIV BIT 4
REF DIV BIT 5
REF DIV BIT 6
REF DIV BIT 7
REF DIV BIT 8
REF DIV BIT 9
HC44
ABSOLUTE MAXIMUM RATINGS
Supply voltage
Operating temperature
Storage temperature
Prescaler and reference input voltage
Data inputs
Junction temperature
20·3V to 16V
255°C to1100°C
265°C to 1150°C
2·5V p-p
V
10·3V
CC
V
20·3V
EE
1175°C
ORDERING INFORMATION
SP8854E KG HCAR Non-standard temperature range,
255°C to 1100°C, standard product screening
SP8854E IG HCAR Industrial temperature range,
240°C to 185°C, standard product screening
*FPD and F
outputs are reversed using the control
REF
direction input, pin 23. The above diagram is correct
when pin 23 is high.
Fig. 1 Pin connections - top view
THERMAL DATA
u
= 5°C/W
JC
u
= 53°C/W
JA
ESD PROTECTION
1000V, human body model
SP8854E
V
CC
PRESCALER
RF INPUT
RF INPUT
0V
PRESCALER
STROBE
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
15
13
14
14
39
11
10
9
8
7
6
5
4
3
2
1
44
43
42
41
40
INPUT
INTERFACE
MODULUS
CONTROL
48/9
LOAD
28 27
REFERENCE
CRYSTAL
3-BIT
A COUNTER
B0 B2 B3
11-BIT
M COUNTER
B13
B14
B15
RF BUFFER
*F
and FPD outputs are reversed using
REF
the control direction input. The pin allocations
shown are correct when bit 12 is high.
10-BIT REFERENCE DIVIDER
38 37 36 35 34 33 32 31 30 29
REFERENCE
CAPACITOR
BIT 0
REFERENCE DIVIDER PROGRAMMING
F
PD
BIT 9
PHASE
DETECTOR
F
REF
20
CHARGE PUMP OUTPUT
21
CHARGE PUMP REFERENCE
17
LOCK DETECT OUTPUT
19
R
SET
18
C-LOCK DETECT
24
F
*
PD
25
F
*
REF
22
FPD/FREF ENABLE
23
CONTROL DIRECTION
26
V
CC
16
V
EE
Fig. 2 Block diagram
2
SP8854E
Pin
1-11, 42-44
13 (RF INPUT)
14 (RF INPUT)
17 (LOCK DETECT INPUT)
18 (C-LOCK DETECT)
19 (R
SET
)
20 (CHARGE PUMP OUTPUT)
21 (CHARGE PUMP REF)
22 (F
/ FPD ENABLE)
REF
23 (CONTROL DIRECTION)
Description
These pins are the data inputs to set the RF divider ratio (MN1A). High is open circuit on these
pins. Data is transparent from pins to RF buffer when pin 39 (STROBE) is high and frozen in
buffers when pin 39 is low.
Balanced inputs to the RF preamplifier. For single-ended operation the signal is AC-coupled into
pin 13 with pin 14 AC-decoupled to ground (or vice-versa). Pins 13 and 14 are internally DC
biased.
A current sink into this pin is enabled when the lock detect circuit indicates lock. Used to give
an external indication of phase lock.
A capacitor connected to this point determines the lock detect integrator time constant and can
be used to vary the sensitivity of the phase lock indicator.
An external resistor from pin 19 to V
sets the charge pump output current.
CC
The phase detector output is a single ended charge pump sourcing or sinking current to the
inverting input of an external loop filter.
Connected to the non-inverting input of the loop filter to set the optimum DC bias.
Part of the input bus. When this pin is high, the F
/ FPD outputs are enabled.
REF
High is open circuit.
This pin controls charge pump output direction. When pin 23 is high, the output sinks current
when F
PD
> F
or when the RF phase leads the reference phase. When pin 23 is low, the
REF
relationship is reversed (see Table 3).
24 F
25 F
if pin 23 is high
PD
F
if pin 23 is low
REF
if pin 23 is low
PD
F
if pin 23 is high
REF
27 (Ref. oscillator capacitor)
28 (REF IN/XTAL)
29-38
39 (STROBE)
40, 41 (PD gain)
RF divider output pulses. F
= RF input frequency/(M.N1A). Pulse width = 8 RF input cycles
PD
(1 cycle of the divide by 8 prescaler output).
Reference divider output pulses. F
= reference input frequency/R. Pulse width = high period
REF
of Ref input.
Leave open circuit if an external reference is used. See Fig. 5 for typical connection for use as
an onboard crystal oscillator.
This pin is the input buffer amplifier for an external reference signal. This amplifier provides the
active element if an onboard crystal oscillator is used.
These pins set the reference divider ratio R. High is open circuit.
When pin 39 is high the A, M, and R counters are held in the reset state and the charge pump
output is disabled. When pin 39 is low the data on the RF data and PD gain pins is fixed in the
buffers, the buffers are loaded into the RF counters and the PD gain control, all the counters are
active, and the charge pump is enabled. High is open circuit.
These pins set the charhe pump current multiplication factor (see Table 2). The data is
transparent into the buffers when pin 39 is high and frozen when pin 39 is low.
High is open circuit.
Table 1 Pin descriptions
3
SP8854E
ELECTRICAL CHARACTERISTICS
The Electrical Characteristics are guaranteed over the following range of operating conditions unless otherwise stated
T
= 2 55°C to 1100°C (KG parts), 2 40°C to 185°C (IG parts); VCC = 4·75V to 5·25V
AMB
Characteristic Conditions
Supply current
RF input sensitivity
RF division ratio
Reference division ratio
Comparison frequency
Reference input frequency
Reference input voltage
F
F
output voltage high
REF/FPD
output voltage low
REF/FPD
LOCK DETECT output voltage
CHARGE PUMP current
Input bus logic level high
Input bus logic level low
Input bus current source
Input bus current sink
Up/down current matching
CHARGE PUMP REFERENCE voltage
current
R
SET
R
voltage
SET
C-LOCK DETECT current
STROBE pulse width
Data setup time
Pin
18, 26
13,14
13,14, 24
28, 25
28, 24, 25
28
28
24, 25
24, 25
17
19, 20, 21
1-11, 22,
23, 29, 44
1-11, 22,
23, 29, 44
1-11, 22,
23, 29, 44
1-11, 22,
23, 29, 44
20
21
19
19
18
Min.
25
56
1
10
0
61·4
62·0
63·4
65·4
3·5
2200
VCC21·6
0·5
50
100
Value
Typ. Max.
180
240
17
16383
1023
50
100
16
110
20·8
21·4
300
61·5
62·3
63·8
66·1
500
61·7
62·5
64·1
66·5
1
10
65
20·5
V
CC
2
1·6
110
Units
mA
dBm
MHz
MHz
dBm
V
V
mV
mA
mA
mA
mA
V
V
µA
µA
%
V
V
mA
V
µA
ns
ns
100MHz to 2·7GHz. See note 3.
Ref division ratio >2. See note 1
WRT V
, 2·2kΩ to 0V
CC
WRT VCC, 2·2kΩ to 0V
= 3mA
I
OUT
V
PIN20
= V
PIN21
, I
PIN19
= 1·6mA,
multiplication factor = 1
V
PIN20
= V
PIN21
, I
PIN19
= 1·6mA,
multiplication factor = 1·5
V
PIN20
= V
PIN21
, I
PIN19
= 1·6mA,
multiplication factor = 2·5
V
PIN20
= V
PIN21
, I
PIN19
= 1·6mA,
multiplication factor = 4·0
VIN = 0V
V
= V
IN
CC
V
= V
PIN20
= 1·6mA, current
I
PIN19
PIN21
, I
PIN19
= 1·6mA
multiplication factor = 1·0
= 1·6mA, current
I
PIN19
multiplication factor = 4·0
Note 2
= 1·6mA
I
PIN19
= 4·7V
V
PIN18
Note 3
Note 3
NOTES
1. Lower frequencies may be used provided that slew rates are maintained.
2. Pin 19 current3multiplication factor must be less than 5mA if charge pump accuracy is to be maintained.
3. Guranteed but not tested.
4
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