Microsoft Surface 1769 Schematics

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Table of Contents

4

3

2

1

Page

D D

01 Table of Contents
02 CHANGE HISTORY
03 BLOCK DIAGRAM
04 CLOCK DISTRIBUTION
05 SYSTEM POWER STATE DIAGRAM
06 POWER DISTRIBUTION
07 INPUT POWER DIAGRAM
08 POWER SYSTEM/CONTROL DIAG
09 I2C MAP
10 CPU(1)_MISC,JTAG,DDI.EDP

C C

11 CPU(2)_LPDDR3
12 CPU(3)_SKL POWER1

Title

Page

Title

31 Debug mux
32 Debug buttons
33 SW Debug Conn
34 EE Debug Connector
35 SM BUS, DIAGNOSTIC CONN
36 Power Monitor
37 SPI ROM UEFI
38 TPM
39 Temp Sensor/System Fan
40 REALTEK ALC3269 CODEC
41 Audio Jack/Spkr
42 Audio Amplifier

Page

Title

61 Discrete Load Switches
62 1.8VSB & Load SW
63 CHARGER
64 5V Load SW
65 3P3V Load SW
66 VCPU Controller
67 VCORE VCCSA
68 VCVGT
69 SL Power
70 BATT CONN, power input
71 Empty

72 LCD backlight/TB
13 CPU(4)_SKL_POWER2
14 CPU(5)_GND
15 CPU(6)_CFG_RESERVED
16 LPDDR3(1)_MEMORY DOWN
17 LPDDR3(2)_MEMORY DOWN
18 XDP
19 LPDDR3(3)_CA/DQ Voltage
20 PCH(1)_SD,HDA,RTC, CLK

B B

21 PCH(2)_CLK,SMB,LPC, SPI
22 PCH(3)_SYS PWR CONTR
23 PCH(4)_CCI, HWID
24 PCH(5)_PCIE,USB
25 PCH(6)_CPU,GPIO,MISC
26 PCH(7)_POWER

43 SSD page 1
44 SSD Page 2
45 USB3.0, TYPE A
46 SL HDMI MUX/3P3V_HPD
47 SurfLink Connector
48 BLADE
49 G5 touch circuitry
50 Wi-Fi_BT
51 Empty
52 Empty
53 mDP
54 Camera/Sensor Conn.
55 eDP connector
56 3P3VA & Reset

73 Empty

74 Empty

75 Empty

76 TP's and Mech

27 SAM_1, K22
28 SAM_2, K22
29 SAM_3, K22
30 INSTANT_ON

A A

57 VCCEDRAM & VCCEOPIO
58 PMIC 1
59 PMIC 2
60 PMIC 3

CAD Note:

Default component footprint is SMD 0201, X5R, 1% resistors.

01. Table of Contents

01. Table of Contents

Property: BUILD-OPT
DNP = Do Not Place

5

Title:

Title:

S or DB = Replace after Debug

4

3

2

Microsoft Confidential

Microsoft Confidential

Microsoft Confidential

Size Project Name Rev

Size Project Name Rev

Size Project Name Rev

A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

A

A

A

Title:

Engineer:

Engineer:

Engineer:

01. Table of Contents

Surface

Surface

Surface

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Schematics Change History

Schematics Change is maintained in spreadsheet, and would not fit on this page.

D D

C C

B B

A A

CAD Note:

Default component footprint is SMD 0201, X5R, 1% resistors

Property: BUILD-OPT

DNP = Not Installed Part.

5

4

S = Short after design fixed

3

02. CHANGE HISTORY

02. CHANGE HISTORY

Title:

Title:

Title:

Microsoft Confidential

Microsoft Confidential

Microsoft Confidential

Size Project Name Rev

Size Project Name Rev

Size Project Name Rev

A3

A3

A3

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

A

A

A

Engineer:

Engineer:

Engineer:

02. CHANGE HISTORY

Surface

Surface

Surface

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Front IR

(OV7251)

Debug UART, external connector

D D

Power Monitor Components

(DEBUG)

MIPI CSIx1

(1Gbps)

I2C

Illuminator

MIPI CSIx1

HD Audio

I2C

Front RGB

(720p – OV9734)

Codec

SSD2 BGA chip

Architectural Diagram I-Core

Analog audio combo jack (3.5mm)

Audio

R

L

AMP

Right

ALC1304

Left

Rev 2.5

128GB, 256GB

512GB, 1TB

UART2

CSI2x2

Memory/

SSD BGA chip

128GB, 256GB

512GB, 1TB

2/4 x PCIe

2/4 x PCIe

ALS

I2C

I2C1

I2C3

PCIe 11/12

PCIe 7/8

LPDDR3 x32

Storage

C C

LPDDR3 x32

LPDDR3 x32

LPDDR3 x32

16,8,4 GB (4x)

16MB

128-bit (32b x 4) – 2 Chl -64 bit each

Quad SPI

SPI ROM

Backlight Controller

LCD

13.5"

TrackPad

KeyBoard

B B

UART

INT

TCON

NTRIG G5

eDP 1.4a

SPI

I2C

INT

UART

SC

Freescale

DDR0x64, DD1x64

SPI0

GPIOs

I2C5

eDP

SPI1

I2C0

UART1

SKL-U

15W

2+2/2+3E

O

I
P
G

K22

SL UART

MUX

PWM/Tach

Hall Effect

Fan/Fan

Connection

Temp

Power/PMIC

BD9992GW

(sep Block Dia)

I2C

7.4V

Battery

45WH

w/Fuel G

SC Debug

I2C

7.4V

Battery
Charger
ISL9237

Debug XDP

SC,K22

Greenpak

CSI2x2

XDP

P
D
X

I2C2

HDA

I2C4

DMIC

DDI1

DDI1_AUX

DDPB_CTRL

USB3p2
USB2p2

DDI2

DDI2_AUX

DDPC_CTRL

USB3p1
USB2p1

PCIe9

USB2p5

LPC

LPC

DDI2_A UX
DDPC_CTRL

DDI2_A UX

DDPC_CTRL

1XPCIe

USB2

TPM

Infineon

Nuvaton

NationZ

Surflink

DP1.2

MUX

USB2/USB3.0/DP1.2x4

AUX/DDPC

MUX

Debug

Signals

USB3.0

USB2

Wifi abgn+ac

Marvell 88W8897

BT

IMVP8 PMIC

ISL95857

W/2+3E support

POR CHANGES

2xTPS62134

VCCEDRAM/VCCEOPIO

2 Mic

AUX/DDPC

Debug

MUX

CMC + ESD

CMC + ESD

CMC + ESD

CMC + ESD

3.3V@0.8A OUT

POWER IN/OUT

SurfLink

5V@1.78A OUT

Antennas

mDP

USB3.0
Type-A

LEGEND

External

Connectors

POR CHANGES

Power path updates

Separate Block Diagram

POR CHANGES

Mostly same as P

Changed Feature/Implementation

New Feature/Implementation

A A

5

4

3

SD FLUSH

03. BLOCK DIAGRAM

03. BLOCK DIAGRAM

Title:

Title:

Title:

Microsoft Confidential

Microsoft Confidential

Microsoft Confidential

Size Project Name Rev

Size Project Name Rev

Size Project Name Rev

B

B

B

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

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A

A

Engineer:

Engineer:

Engineer:

03. BLOCK DIAGRAM

Surface

Surface

Surface

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4

3

2

1

C C

B B

A A

04. CLOCK DISTRIBUTION

04. CLOCK DISTRIBUTION

Title:

Title:

Title:

Microsoft Confidential

Microsoft Confidential

Microsoft Confidential

Size Project Name Rev

Size Project Name Rev

Size Project Name Rev

A3

A3

A3

Date: Sheet of

Date: Sheet of

5

4

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2

Date: Sheet of

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A

A

Engineer:

Engineer:

Engineer:

04. CLOCK DISTRIBUTION

Surface

Surface

Surface

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C C

B B

A A

05. SIGNAL & RESET MAP

05. SIGNAL & RESET MAP

05. SIGNAL & RESET MAP

Surface

Surface

Surface

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Title:

Title:

Microsoft Conf idential

Microsoft Conf idential

Microsoft Conf idential

Size Project Name Rev

Size Project Name Rev

Size Project Name Rev

C

C

C

Date: Sheet of

Date: Sheet of

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2

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Engineer:

Engineer:

Engineer:

A

A

A

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J47001

SurfLink Connector

PWR_SL1

D D

PWR_SL1_F

VDD_BAT

C C

B B

U56002

TPS62177

3P3VA

Always On

PWR_SL1

3P3VA

Imax = .5A

R56007
100mєÀ

Q63008/Q63009

Back to Back FETS

U56005

NX3P1108

3P3VA_SW_EN

DeepSleep Rail

S4/S5 Rail

Power Monitor Input

S0 Rail

Load switch

Control Signal

DC-DC

Regulator

A A

Linear

Regulator

5

External

Regulator /Load

Switch

U63001
ISL9237

Buck/Boost Charger

R36023

100mєA

R28001

100mєA

R31023

0mє À

VCC_RTC

Imax=100uA

R99999

20mєA

4

PWR_SL1_R

R63001

20mєA

VSYS_R

R63009

10mєA

VDD_BAT

J70001/J70002/J70003

Battery Connector

2S

Battery

7.6V typ

R56031
100mєA

R39016
100mєA

3P3V_PMI_DBG

3P3VA_SAM

3P3V_DEBUG

4

3P3VA_SW
Imax = .3A

3P3VA_TEMP

R63042

10mє À

Vsys

R67007

20mє À

R68001

20mє À

R67008

50mє À

R58034

10mє À

R58019

5mєA

R58012

20mє À

R58002

10mє À

R59023

25m㤿

R59003

25mє À

R58023

10mє À

R58032

25mєA

R58004

25mєA

R72001

20mє À

3

VCCGT/GTx

Platform PMIC

V3P3A_PCH

V1P8U_2P5U

L_BKLTEN

3

IMVP8

VCORE

VCCSA

U58001

V3P3_DSW

V6

V5A

V5

V1P8A

V8

V7

V0P85A

V12

V1P00A

V11

V9

V1P2U

V10

V0P6DX_LPDDR3

VCCIO

V4

U72001
RT8555

3P3V_SWPWR

V13

VCORE

VCCGT

VCCSA

V3P3_DSW

R58039

20mєA

V5A

R58024

10mєA

V1P8A

R58016

20mєA

V3P3A_PCH

R58008

50mєA

V0P85A

R59027

10mєA

V1P00A

R59007

10mєA

V1P8U_2P5U

R58026

50mєA

V1P2U

R58037

5mєA

R59032

10mєA

R59035

20mєA

VCCIO

R58009

10mєA

2

R64006

50mєA

2

R26004

10mєA

U65003

TPS22920

3P3V_SSD_EN

U65001

TPS22920

EDP_VDD_EN

R53007

0єÀ

R54005
100mєA

R45003

5mє À

R48022
100mєÀ

R64016

20mє À

R64020

20mєA

U62001

SLG59 M1448V

PCH_AUD_1V8_EN

U62003

NX3 P1108

PCH_TPANEL_PWR_EN

TPS22920

WWAN_ PWREN

U61002

SLG5NT1477

VCCSTG_EN

U61003

SLG5NT1477

SKL_SLP_S4_N +

XDP_PR ESENT _LOGIC

U61001

SLG5NT1477

SOiX_EN

SKL

VCORE

Imax = 20A

VCCGT/GTx

Imax = 20A

VCCSA

Imax = 7A

3VSUS_ORG

R38001
100mєÀ

U43005
TPS62085
1P8V_SSD

U43006
TPS62085
1P2V_SSD

R65002

50mєA

ML_V3P3_PWRU53005

3P3V_SSD

R65010 10mє A

R43017

25mєA

R43016

25mєA

NCP380

mDP_PWR_EN

3P3V_CAM

U45004

5V_USBPWR_A

AP2553

SKL_SLP_S4_N

SLG59M1448V

PCH_TPANEL_ PWR_EN

U64002

SLG59M1448V

PCH_TPANEL_PWR_EN

SLG59M1448V

PCH_AUD_5V_EN

SLG59M1448V

SAM_FAN_PWR_EN

U65004

U48002

U64004

U64006

R64019

10mєA

R26003

10mєA

R62002

20mєA

R40005

20mє À

R62007

20mєA

R65012

40mєA

5V0_OFFBOARD

5V_SWPWR

5V_TS

5V_AUDIO

5V_FAN (i-core only)

1P8VSUS_ORG

1P8V_AUDIO

1P8V_AUDIO_DVDD

1P8V_TS

3P3V_WWAN

V0P85A

V1P00A

1V_MODPHY

R61007
20mє À

VCCSTG

R61003
10 mєÀ

VCCST_CPU

R61006
10 mєÀ

V1P00A_XDP

R18001

0 mєA

V1P8U_2P5U

V1P2U

VCCPLL_OC

R61001

10mєA

V0P6DX_LPDDR3

VCCIO

VCC_EDP_BKLT_OUT

DVi7U7660s16s512x2Retail

DVi7U7660s16s512x2Retail

DVi7U7660s16s512x2Retail

Title:

Title:

Microsoft Confidential

Microsoft Confidential

Microsoft Confidential

Size Project Name Rev

Size Project Name Rev

Size Project Name Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Title:

Engineer:

Engineer:

Engineer:

A

A

A

1

3P3V_TPM

1P8V_SSD

1P2V_SSD

3P3V_PANEL

J53001

mDP

Connector

J45001
USB 3.0 A
Connector

(keyboard)

06. POWER DISTRIBUTION

06. POWER DISTRIBUTION

06. POWER DISTRIBUTION

Surface

Surface

Surface

6 79Thursday, April 26, 2018

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D D

4

3

2

1

C C

B B

A A

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07. POW ER SEQUENCE 1

07. POW ER SEQUENCE 1

07. POW ER SEQUENCE 1

Title:

Title:

Microsoft Confidential

Microsoft Confidential

Microsoft Confidential

Size Project Name Rev

Size Project Name Rev

Size Project Name Rev

D

D

D

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

1

Title:

Engineer:

Engineer:

Engineer:

A

A

A

Surface

Surface

Surface

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4

3

2

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C C

B B

A A

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08. POWER SEQUENCE

08. POWER SEQUENCE

08. POWER SEQUENCE

Title:

Title:

Microsoft Confidential

Microsoft Confidential

Microsoft Confidential

Size Project Name Rev

Size Project Name Rev

Size Project Name Rev

D

D

D

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

1

Title:

Engineer:

Engineer:

Engineer:

A

A

A

Surface

Surface

Surface

8 79Thursday, April 26, 2018

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DVi7U7660s16s512x2Retail

DVi7U7660s16s512x2Retail

DVi7U7660s16s512x2Retail

Microsoft Confidential

Microsoft Confidential

Microsoft Confidential

Size Project Name Rev

Size Project Name Rev

Size Project Name Rev

A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

2
0
0
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Te m p S en sor S TT S7 5 1

0x4A

09. I2C MAP

09. I2C MAP

Title:

Title:

Title:

Engineer:

Engineer:

Engineer:

09. I2C MAP

1

Surface

Surface

Surface

9 79Thursday, April 26, 2018

9 79Thursday, April 26, 2018

9 79Thursday, April 26, 2018

4
0
0
9
3

U

1.0.0.1

1.0.0.1

1.0.0.1

5

Vinafix.com

VCCSTG

R10001
1K

0201

D D

C C

PROCHOT_N[34,60,63,66]

R10004

100

0402

D

SAM_PROCHOT[29]

G

RUM002N02GT2L

0201

R10029 100K

Q10001

S

VCCST_CPU

R10019
1K

0201

XDP_TP10001

TS_IRQ_3V3_N[49]

XDP_TP10002

TRACKPAD_INT_N[27,48]

mDP_PWR_EN[53]

0201

R10011 49.9

R10012 49.9

0201

R10003 499

EE SQ 13.8mil

EE SQ 13.8mil

0201

0201

R10013 49.9

4

VCCST_CPU

SMD RND 22.8mil

0201

R10014 49.9

DNP

R10002

49.9

0201

GTP10006

PM_THERMTRIP_N[10,56]

XDP_BPM0[18]
XDP_BPM1[18]

PROC_POPIRCOMP
PCH_OPIRCOMP
OPCE_RCOMP
OPC_RCOMP

R10035 330 0201

TP_CATERR_R_N

H_PROCHOT_R_N

GPP_E3

U10001D

D63

CATERR#

A54

PECI

C65

PROCHOT#

C63

THERMTRIP#

A65

SKTOCC#

C55

BPM#[0]

D55

BPM#[1]

B54

BPM#[2]

C56

BPM#[3]

A6

GPP_E3/CPU_GP0

A7

GPP_E7/CPU_GP1

BA5

GPP_B3/CPU_GP2

AY5

GPP_B4/CPU_GP3

AT16

PROC_POPIRCOMP

AU16

PCH_OPIRCOMP

H66

OPCE_RCOMP

H65

OPC_RCOMP

KBL-R U42

<$LOCATION>
<MATERIAL>
4 OF 20
REV = 1

3

CPU MISC

KBL_R_U42

JTAG

PROC_TCK

PROC_TDI
PROC_TDO
PROC_TMS

PROC_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS

PCH_TRST#

JTAGX

VCCSTG

R10032 100

B61
D60
A61
C60
B59

B56
D59
A56
C59
C61
A59

0201

2

MTP10001 SMD RND 22.8mil
MTP10002 SMD RND 22.8mil
MTP10003 SMD RND 22.8mil
MTP10004 SMD RND 22.8mil
MTP10005 SMD RND 22.8mil

PROC_TCK [10,18]
PROC_TDI [10,18]

PROC_TDO [10,18]
PROC_TMS [10,18]
PROC_TRST_N [10,18]

0201

PLACE TP's on BOTTOM,

1

PLACE TP's on BOTTOM,

R10008 51

0201

0201

R10015 51

R10016 100

0201

R10017 51

VCCSTG

MTP10007 SMD RND 22.8mil
MTP10008 SMD RND 22.8mil
MTP10009 SMD RND 22.8mil
MTP10010 SMD RND 22.8mil
MTP10011 SMD RND 22.8mil
MTP10012 SMD RND 22.8mil

PCH_JTAG_TCK [18]
PROC_TDI [10,18]
PROC_TDO [10,18]
PROC_TMS [10,18]
PROC_TRST_N [10,18]
PROC_TCK [10,18]

TBL1002

PM_THERMTRIP_N[10,56]

U10001A

MDP_DDI1_ML0_DN[53]
MDP_DDI1_ML0_DP[53]
MDP_DDI1_ML1_DN[53]
MDP_DDI1_ML1_DP[53]
MDP_DDI1_ML2_DN[53]
MDP_DDI1_ML2_DP[53]
MDP_DDI1_ML3_DN[53]
MDP_DDI1_ML3_DP[53]

SL_DDI2_ML0_DN[47]
SL_DDI2_ML0_DP[47]

B B

DDPB_CTRL_CLK[53]

VCCIO

R10025

24.9

0201

SAM_PCH_HALL_INT[27]

DDPB_CTRL_DATA[53]

SL_DDI2_ML1_DN[47]
SL_DDI2_ML1_DP[47]
SL_DDI2_ML2_DN[47]
SL_DDI2_ML2_DP[47]
SL_DDI2_ML3_DN[47]
SL_DDI2_ML3_DP[47]

DDPC_CTRL_CLK[46]

DDPC_CTRL_DATA[46]

EDP_COMP

INT. PD

INT. PD

TBL1001

A A

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

L13

GPP_E18/DDPB_CTRLCLK

L12

GPP_E19/DDPB_CTRLDATA

N7

GPP_E20/DDPC_CTRLCLK

N8

GPP_E21/DDPC_CTRLDATA

N11

GPP_E22/DDPD_CTRLCLK

N12

GPP_E23/DDPD_CTRLDATA

E52

EDP_RCOMP

KBL-R U42

1 OF 20
REV = 1

KBL_R_U42

DDI

DISPLAY SIDEBANDS

EDP

EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
EDP_TXP[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]

EDP_AUXN
EDP_AUXP

EDP_DISP_UTIL

DDI1_AUXN
DDI1_AUXP
DDI2_AUXN
DDI2_AUXP

RSVD_G46

RSVD_F46

GPP_E13/DDPB_HPD0
GPP_E14/DDPC_HPD1
GPP_E15/DDPD_HPD2
GPP_E16/DDPE_HPD3

GPP_E17/EDP_HPD

EDP_BKLTEN

EDP_BKLTCTL

EDP_VDDEN

C47
C46
D46
C45
A45
B45
A47
B47

E45
F45

B52

G50
F50
E48
F48
G46
F46

L9
L7
L6
N9
L10

R12
R11
U13

EDP_TX0_DN [55]
EDP_TX0_DP [55]
EDP_TX1_DN [55]
EDP_TX1_DP [55]
EDP_TX2_DN [55]
EDP_TX2_DP [55]
EDP_TX3_DN [55]
EDP_TX3_DP [55]

EDP_AUX_DN [55]
EDP_AUX_DP [55]

eDP x 4

MDP_DDI1_AUX_DN [53]
MDP_DDI1_AUX_DP [53]
SL_DDI2_AUX_DN [46]
SL_DDI2_AUX_DP [46]

SOC_BKLTEN [30]

SOC_BKLT_CTRL_IN [30]

SOC_DISPLAY_VDD_EN [30]

EDP_DISP_UTIL

0201DNP

0201DNP

R10026 100K

R10027 100K

0201

R10028 100K

DNP

R10022
0

0201

0201

R10037 49.9K

V5A

R10033
10K

0201

5

34

Q10002B
NX3008NBKS

SOT-363

BL_INST_ON_HNDSHK [29,30]

EDP_HPD [55]

3VSUS_ORG

R10039 49.9K

0201

V5A

2

R10034
10K

0201

61

Q10002A
NX3008NBKS

SOT-363

GPP_A 3.3V
GPP_B 3.3V
GPP_C 3.3V
GPP_D 1.8V
GPP_E 3.3V
GPP_F 1.8V
GPP_G 3.3V
GDP 3.3V

MDP_SNK1_HPD [53]

SL_SNK0_HPD [47]

SAM_PCH_RSV1 [27]

10. CPU(1)_MISC,JTAG,DDI.EDP

10. CPU(1)_MISC,JTAG,DDI.EDP

Title:

Title:

Title:

Microsoft Confidential

Microsoft Confidential

Microsoft Confidential

Size Project Name Rev

Size Project Name Rev

Size Project Name Rev

B

B

U SPECIFIC

5

4

3

2

B

Date: Sheet of

Date: Sheet of

Date: Sheet of

A

A

A

Engineer:

Engineer:

Engineer:

10. CPU(1)_MISC,JTAG,DDI.EDP

Surface

Surface

Surface

10 79Friday, April 27, 2018

10 79Friday, April 27, 2018

1

10 79Friday, April 27, 2018

1.0.0.1

1.0.0.1

1.0.0.1

5

Vinafix.com

4

3

2

1

U10001C

U10001B

M_A_D[7:0][16]

D D

C C

M_A_D[15:8][16]

M_A_D[39:32][16]

M_A_D[47:40][16]

M_B_D[7:0][17]

M_B_D[15:8][17]

M_B_D[39:32][17]

M_B_D[47:40][17]

M_A_D0
M_A_D1
M_A_D2
M_A_D3
M_A_D4
M_A_D5
M_A_D6
M_A_D7
M_A_D8
M_A_D9
M_A_D10
M_A_D11
M_A_D12
M_A_D13
M_A_D14
M_A_D15
M_A_D32
M_A_D33
M_A_D34
M_A_D35
M_A_D36
M_A_D37
M_A_D38
M_A_D39
M_A_D40
M_A_D41
M_A_D42
M_A_D43
M_A_D44
M_A_D45
M_A_D46
M_A_D47
M_B_D0
M_B_D1
M_B_D2
M_B_D3
M_B_D4
M_B_D5
M_B_D6
M_B_D7
M_B_D8
M_B_D9
M_B_D10
M_B_D11
M_B_D12
M_B_D13
M_B_D14
M_B_D15
M_B_D32
M_B_D33
M_B_D34
M_B_D35
M_B_D36
M_B_D37
M_B_D38
M_B_D39
M_B_D40
M_B_D41
M_B_D42
M_B_D43
M_B_D44
M_B_D45
M_B_D46
M_B_D47

DDR4(IL)/LP3-DDR4(NIL)

AL71

DDR0_DQ[0]

AL68

DDR0_DQ[1]

AN68

DDR0_DQ[2]

AN69

DDR0_DQ[3]

AL70

DDR0_DQ[4]

AL69

DDR0_DQ[5]

AN70

DDR0_DQ[6]

AN71

DDR0_DQ[7]

AR70

DDR0_DQ[8]

AR68

DDR0_DQ[9]

AU71

DDR0_DQ[10]

AU68

DDR0_DQ[11]

AR71

DDR0_DQ[12]

AR69

DDR0_DQ[13]

AU70

DDR0_DQ[14]

AU69

DDR0_DQ[15]

BB65

DDR0_DQ[16]/DDR0_DQ[32]

AW65

DDR0_DQ[17]/DDR0_DQ[33]

AW63

DDR0_DQ[18]/DDR0_DQ[34]

AY63

DDR0_DQ[19]/DDR0_DQ[35]

BA65

DDR0_DQ[20]/DDR0_DQ[36]

AY65

DDR0_DQ[21]/DDR0_DQ[37]

BA63

DDR0_DQ[22]/DDR0_DQ[38]

BB63

DDR0_DQ[23]/DDR0_DQ[39]

BA61

DDR0_DQ[24]/DDR0_DQ[40]

AW61

DDR0_DQ[25]/DDR0_DQ[41]

BB59

DDR0_DQ[26]/DDR0_DQ[42]

AW59

DDR0_DQ[27]/DDR0_DQ[43]

BB61

DDR0_DQ[28]/DDR0_DQ[44]

AY61

DDR0_DQ[29]/DDR0_DQ[45]

BA59

DDR0_DQ[30]/DDR0_DQ[46]

AY59

DDR0_DQ[31]/DDR0_DQ[47]

AY39

DDR0_DQ[32]/DDR1_DQ[0]

AW39

DDR0_DQ[33]/DDR1_DQ[1]

AY37

DDR0_DQ[34]/DDR1_DQ[2]

AW37

DDR0_DQ[35]/DDR1_DQ[3]

BB39

DDR0_DQ[36]/DDR1_DQ[4]

BA39

DDR0_DQ[37]/DDR1_DQ[5]

BA37

DDR0_DQ[38]/DDR1_DQ[6]

BB37

DDR0_DQ[39]/DDR1_DQ[7]

AY35

DDR0_DQ[40]/DDR1_DQ[8]

AW35

DDR0_DQ[41]/DDR1_DQ[9]

AY33

DDR0_DQ[42]/DDR1_DQ[10]

AW33

DDR0_DQ[43]/DDR1_DQ[11]

BB35

DDR0_DQ[44]/DDR1_DQ[12]

BA35

DDR0_DQ[45]/DDR1_DQ[13]

BA33

DDR0_DQ[46]/DDR1_DQ[14]

BB33

DDR0_DQ[47]/DDR1_DQ[15]

AY31

DDR0_DQ[48]/DDR1_DQ[32]

AW31

DDR0_DQ[49]/DDR1_DQ[33]

AY29

DDR0_DQ[50]/DDR1_DQ[34]

AW29

DDR0_DQ[51]/DDR1_DQ[35]

BB31

DDR0_DQ[52]/DDR1_DQ[36]

BA31

DDR0_DQ[53]/DDR1_DQ[37]

BA29

DDR0_DQ[54]/DDR1_DQ[38]

BB29

DDR0_DQ[55]/DDR1_DQ[39]

AY27

DDR0_DQ[56]/DDR1_DQ[40]

AW27

DDR0_DQ[57]/DDR1_DQ[41]

AY25

DDR0_DQ[58]/DDR1_DQ[42]

AW25

DDR0_DQ[59]/DDR1_DQ[43]

BB27

DDR0_DQ[60]/DDR1_DQ[44]

BA27

DDR0_DQ[61]/DDR1_DQ[45]

BA25

DDR0_DQ[62]/DDR1_DQ[46]

BB25

DDR0_DQ[63]/DDR1_DQ[47]

KBL-R U42

<$LOCATION>
<MATERIAL>
2 OF 20
REV = 1

KBL_R_U42

DDR CH - A

LP3/DDR4

DDR0_CKN[0]
DDR0_CKP[0]
DDR0_CKN[1]
DDR0_CKP[1]

LP3/DDR4

DDR0_CKE[0]

DDR0_CKE[1]
DDR0_CKE[2]/NC
DDR0_CKE[3]/NC

LP3/DDR4

DDR0_CS#[0]

DDR0_CS#[1]

DDR0_ODT[0]
NC/DDR0_ODT[1]

LP3/DDR4

DDR0_CAA[0]/DDR0_MA[5]
DDR0_CAA[1]/DDR0_MA[9]
DDR0_CAA[2]/DDR0_MA[6]
DDR0_CAA[3]/DDR0_MA[8]
DDR0_CAA[4]/DDR0_MA[7]

DDR0_CAA[5]/DDR0_BG[0]
DDR0_CAA[6]/DDR0_MA[12]
DDR0_CAA[7]/DDR0_MA[11]

DDR0_CAA[8]/DDR0_ACT#
DDR0_CAA[9]/DDR0_BG[1]

DDR0_CAB[0]/DDR0_MA[13]
DDR0_CAB[1]/DDR0_MA[15]
DDR0_CAB[2]/DDR0_MA[14]
DDR0_CAB[3]/DDR0_MA[16]

DDR0_CAB[7]/DDR0_MA[10]

DDR0_DQSN[2]/DDR0_DQSN[4]
DDR0_DQSP[2]/DDR0_DQSP[4]
DDR0_DQSN[3]/DDR0_DQSN[5]
DDR0_DQSP[3]/DDR0_DQSP[5]
DDR0_DQSN[4]/DDR1_DQSN[0]
DDR0_DQSP[4]/DDR1_DQSP[0]
DDR0_DQSN[5]/DDR1_DQSN[1]
DDR0_DQSP[5]/DDR1_DQSP[1]
DDR0_DQSN[6]/DDR1_DQSN[4]
DDR0_DQSP[6]/DDR1_DQSP[4]
DDR0_DQSN[7]/DDR1_DQSN[5]
DDR0_DQSP[7]/DDR1_DQSP[5]

LP3/DDR4

DDR0_CAB[4]/DDR0_BA[0]

DDR0_CAB[5]/DDR0_MA[2]

DDR0_CAB[6]/DDR0_BA[1]

DDR0_CAB[8]/DDR0_MA[1]
DDR0_CAB[9]/DDR0_MA[0]

NC/DDR0_MA[3]
NC/DDR0_MA[4]

DDR4(IL)/LP3-DDR4(NIL)

DDR0_DQSN[0]
DDR0_DQSP[0]
DDR0_DQSN[1]
DDR0_DQSP[1]

LP3/DDR4

NC/DDR0_ALERT#

NC/DDR0_PAR

DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ

DDR_VTT_CNTL

AU53
AT53
AU55
AT55

BA56
BB56
AW56
AY56

AU45
AU43
AT45
AT43

M_A_CAA0

BA51

M_A_CAA1

BB54

M_A_CAA2

BA52

M_A_CAA3

AY52

M_A_CAA4

AW52

M_A_CAA5

AY55

M_A_CAA6

AW54

M_A_CAA7

BA54

M_A_CAA8

BA55

M_A_CAA9

AY54

M_A_CAB0

AU46

M_A_CAB1

AU48

M_A_CAB2

AT46

M_A_CAB3

AU50

M_A_CAB4

AU52

M_A_CAB5

AY51

M_A_CAB6

AT48

M_A_CAB7

AT50

M_A_CAB8

BB50

M_A_CAB9

AY50
BA50
BB52

AM70
AM69
AT69
AT70
BA64
AY64
AY60
BA60
BA38
AY38
AY34
BA34
BA30
AY30
AY26
BA26

AW50
AT52

AY67

DIMM_VREF_C A [19]

AY68

DIMM0_VREF_D Q [19]

BA67

DIMM1_VREF_D Q [19]

AW67

M_A_DIM0_CLKN 0 [16]
M_A_DIM0_CLKP0 [16]
M_A_DIM0_CLKN 1 [16]
M_A_DIM0_CLKP1 [16]

M_A_DIM0_CKE0 [16]
M_A_DIM0_CKE1 [16]
M_A_DIM0_CKE2 [16]
M_A_DIM0_CKE3 [16]

M_A_DIM0_CS0_N [16]
M_A_DIM0_CS1_N [16]
M_A_DIM0_ODT0 [16]

M_A_CAA[9:0] [16]

M_A_CAB[9:0] [16]

M_A_DQSN0 [16]
M_A_DQSP0 [16]
M_A_DQSN1 [16]
M_A_DQSP1 [16]
M_A_DQSN4 [16]
M_A_DQSP4 [16]
M_A_DQSN5 [16]
M_A_DQSP5 [16]
M_B_DQSN0 [17]

M_B_DQSN1 [17]
M_B_DQSP1 [17]
M_B_DQSN4 [17]
M_B_DQSP4 [17]
M_B_DQSN5 [17]
M_B_DQSP5 [17]

DDR_VTT_CTL [34,59]

M_A_D[23:16][16]

M_A_D[31:24][16]

M_A_D[55:48][16]

M_A_D[63:56][16]

M_B_D[23:16][17]

M_B_D[31:24][17]

M_B_D[55:48][17]

M_B_D[63:56][17]

M_A_D16
M_A_D17
M_A_D18
M_A_D19
M_A_D20
M_A_D21
M_A_D22
M_A_D23
M_A_D24
M_A_D25
M_A_D26
M_A_D27
M_A_D28
M_A_D29
M_A_D30
M_A_D31
M_A_D48
M_A_D49
M_A_D50
M_A_D51
M_A_D52
M_A_D53
M_A_D54
M_A_D55
M_A_D56
M_A_D57
M_A_D58
M_A_D59
M_A_D60
M_A_D61
M_A_D62
M_A_D63
M_B_D16
M_B_D17
M_B_D18
M_B_D19
M_B_D20
M_B_D21
M_B_D22
M_B_D23
M_B_D24
M_B_D25
M_B_D26
M_B_D27
M_B_D28
M_B_D29
M_B_D30
M_B_D31
M_B_D48
M_B_D49
M_B_D50
M_B_D51
M_B_D52
M_B_D53
M_B_D54
M_B_D55
M_B_D56
M_B_D57
M_B_D58
M_B_D59
M_B_D60
M_B_D61
M_B_D62
M_B_D63

DDR4(IL)/LP3-DDR4(NIL) LP3/DDR4

AF65

DDR1_DQ[0]/DDR0_DQ[16]

AF64

DDR1_DQ[1]/DDR0_DQ[17]

AK65

DDR1_DQ[2]/DDR0_DQ[18]

AK64

DDR1_DQ[3]/DDR0_DQ[19]

AF66

DDR1_DQ[4]/DDR0_DQ[20]

AF67

DDR1_DQ[5]/DDR0_DQ[21]

AK67

DDR1_DQ[6]/DDR0_DQ[22]

AK66

DDR1_DQ[7]/DDR0_DQ[23]

AF70

DDR1_DQ[8]/DDR0_DQ[24]

AF68

DDR1_DQ[9]/DDR0_DQ[25]

AH71

DDR1_DQ[10]/DDR0_DQ[26]

AH68

DDR1_DQ[11]/DDR0_DQ[27]

AF71

DDR1_DQ[12]/DDR0_DQ[28]

AF69

DDR1_DQ[13]/DDR0_DQ[29]

AH70

DDR1_DQ[14]/DDR0_DQ[30]

AH69

DDR1_DQ[15]/DDR0_DQ[31]

AT66

DDR1_DQ[16]/DDR0_DQ[48]

AU66

DDR1_DQ[17]/DDR0_DQ[49]

AP65

DDR1_DQ[18]/DDR0_DQ[50]

AN65

DDR1_DQ[19]/DDR0_DQ[51]

AN66

DDR1_DQ[20]/DDR0_DQ[52]

AP66

DDR1_DQ[21]/DDR0_DQ[53]

AT65

DDR1_DQ[22]/DDR0_DQ[54]

AU65

DDR1_DQ[23]/DDR0_DQ[55]

AT61

DDR1_DQ[24]/DDR0_DQ[56]

AU61

DDR1_DQ[25]/DDR0_DQ[57]

AP60

DDR1_DQ[26]/DDR0_DQ[58]

AN60

DDR1_DQ[27]/DDR0_DQ[59]

AN61

DDR1_DQ[28]/DDR0_DQ[60]

AP61

DDR1_DQ[29]/DDR0_DQ[61]

AT60

DDR1_DQ[30]/DDR0_DQ[62]

AU60

DDR1_DQ[31]/DDR0_DQ[63]

AU40

DDR1_DQ[32]/DDR1_DQ[16]

AT40

DDR1_DQ[33]/DDR1_DQ[17]

AT37

DDR1_DQ[34]/DDR1_DQ[18]

AU37

DDR1_DQ[35]/DDR1_DQ[19]

AR40

DDR1_DQ[36]/DDR1_DQ[20]

AP40

DDR1_DQ[37]/DDR1_DQ[21]

AP37

DDR1_DQ[38]/DDR1_DQ[22]

AR37

DDR1_DQ[39]/DDR1_DQ[23]

AT33

DDR1_DQ[40]/DDR1_DQ[24]

AU33

DDR1_DQ[41]/DDR1_DQ[25]

AU30

DDR1_DQ[42]/DDR1_DQ[26]

AT30

DDR1_DQ[43]/DDR1_DQ[27]

AR33

DDR1_DQ[44]/DDR1_DQ[28]

AP33

DDR1_DQ[45]/DDR1_DQ[29]

AR30

DDR1_DQ[46]/DDR1_DQ[30]

AP30

DDR1_DQ[47]/DDR1_DQ[31]

AU27

DDR1_DQ[48]

AT27

DDR1_DQ[49]

AT25

DDR1_DQ[50]

AU25

DDR1_DQ[51]

AP27

DDR1_DQ[52]

AN27

DDR1_DQ[53]

AN25

DDR1_DQ[54]

AP25

DDR1_DQ[55]

AT22

DDR1_DQ[56]

AU22

DDR1_DQ[57]

AU21

DDR1_DQ[58]

AT21

DDR1_DQ[59]

AN22

DDR1_DQ[60]

AP22

DDR1_DQ[61]

AP21

DDR1_DQ[62]

AN21

DDR1_DQ[63]

KBL-R U42

<$LOCATION>
<MATERIAL>
3 OF 20
REV = 1

KBL_R_U42

DDR CH - B

DDR1_CKN[0]
DDR1_CKN[1]
DDR1_CKP[0]
DDR1_CKP[1]

LP3/DDR4

DDR1_CKE[0]

DDR1_CKE[1]
DDR1_CKE[2]/NC
DDR1_CKE[3]/NC

LP3/DDR4

DDR1_CS#[0]
DDR1_CS#[1]

DDR1_ODT[0]
NC/DDR1_ODT[1]

DDR1_CAA[0]/DDR1_MA[5]
DDR1_CAA[1]/DDR1_MA[9]
DDR1_CAA[2]/DDR1_MA[6]
DDR1_CAA[3]/DDR1_MA[8]
DDR1_CAA[4]/DDR1_MA[7]

DDR1_CAA[5]/DDR1_BG[0]
DDR1_CAA[6]/DDR1_MA[12]
DDR1_CAA[7]/DDR1_MA[11]

DDR1_CAA[8]/DDR1_ACT#

DDR1_CAA[9]/DDR1_BG[1]

DDR1_CAB[0]/DDR1_MA[13]
DDR1_CAB[1]/DDR1_MA[15]
DDR1_CAB[2]/DDR1_MA[14]
DDR1_CAB[3]/DDR1_MA[16]

DDR1_CAB[4]/DDR1_BA[0]

DDR1_CAB[5]/DDR1_MA[2]

DDR1_CAB[6]/DDR1_BA[1]

DDR1_CAB[7]/DDR1_MA[10]

DDR1_CAB[8]/DDR1_MA[1]

DDR1_CAB[9]/DDR1_MA[0]

DDR1_DQSN[0]/DDR0_DQSN[2]
DDR1_DQSP[0]/DDR0_DQSP[2]
DDR1_DQSN[1]/DDR0_DQSN[3]
DDR1_DQSP[1]/DDR0_DQSP[3]
DDR1_DQSN[2]/DDR0_DQSN[6]
DDR1_DQSP[2]/DDR0_DQSP[6]
DDR1_DQSN[3]/DDR0_DQSN[7]
DDR1_DQSP[3]/DDR0_DQSP[7]
DDR1_DQSN[4]/DDR1_DQSN[2]
DDR1_DQSP[4]/DDR1_DQSP[2]
DDR1_DQSN[5]/DDR1_DQSN[3]
DDR1_DQSP[5]/DDR1_DQSP[3]

LP3/DDR4

LP3/DDR4

NC/DDR1_MA[3]
NC/DDR1_MA[4]

DDR4(IL)/LP3-DDR4(NIL)

DDR1_DQSN[6]

DDR1_DQSP[6]

DDR1_DQSN[7]

DDR1_DQSP[7]

LP3/DDR4

NC/DDR1_ALERT#

NC/DDR1_PAR

DRAM_RESET#
DDR_RCOMP[0]
DDR_RCOMP[1]
DDR_RCOMP[2]

AN45
AN46
AP45
AP46

AN56
AP55
AN55
AP53

BB42
AY42
BA42
AW42

AY48
AP50
BA48
BB48
AP48
AP52
AN50
AN48
AN53
AN52

BA43
AY43
AY44
AW44
BB44
AY47
BA44
AW46
AY46
BA46
BB46
BA47

AH66
AH65
AG69
AG70
AR66
AR65
AR61
AR60
AT38
AR38
AT32
AR32
AR25
AR27
AR22
AR21

AN43
AP43
AT13
AR18
AT18
AU18

M_B_CAA0
M_B_CAA1
M_B_CAA2
M_B_CAA3
M_B_CAA4
M_B_CAA5
M_B_CAA6
M_B_CAA7
M_B_CAA8
M_B_CAA9

M_B_CAB0
M_B_CAB1
M_B_CAB2
M_B_CAB3
M_B_CAB4
M_B_CAB5
M_B_CAB6
M_B_CAB7
M_B_CAB8
M_B_CAB9

M_A_DQSN2 [16]
M_A_DQSP2 [16]
M_A_DQSN3 [16]
M_A_DQSP3 [16]
M_A_DQSN6 [16]
M_A_DQSP6 [16]
M_A_DQSN7 [16]
M_A_DQSP7 [16]
M_B_DQSN2 [17]
M_B_DQSP2 [17]
M_B_DQSN3 [17]M_B_DQSP0 [17]
M_B_DQSP3 [17]
M_B_DQSN6 [17]
M_B_DQSP6 [17]
M_B_DQSN7 [17]
M_B_DQSP7 [17]

SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2

M_B_DIM0_CLKN 0 [17]
M_B_DIM0_CLKN 1 [17]
M_B_DIM0_CLKP0 [17]
M_B_DIM0_CLKP1 [17]

M_B_DIM0_CKE0 [17]
M_B_DIM0_CKE1 [17]
M_B_DIM0_CKE2 [17]
M_B_DIM0_CKE3 [17]

M_B_DIM0_CS0_N [17]
M_B_DIM0_CS1_N [17]
M_B_DIM0_ODT0 [17]

M_B_CAA[9:0] [17]

M_B_CAB[9:0] [17]

R110042001%
R1100580.6
R110061621%

0201
0201
0402

B B

A A

11. CPU(2)_LPDDR3

11. CPU(2)_LPDDR3

11. CPU(2)_LPDDR3

Title:

Title:

Microsoft Conf idential

Microsoft Conf idential

Microsoft Conf idential

Size Project Name Rev

Size Project Name Rev

Size Project Name Rev

C

C

5

4

3

2

U SPECIFIC

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

Title:

Surface

Surface

Surface

Engineer:

Engineer:

Engineer:

1.0.0.1

1.0.0.1

A

A

A

1

11 79Friday, April 27, 2018

11 79Friday, April 27, 2018

11 79Friday, April 27, 2018

1.0.0.1

V1P2U

Vinafix.com

5

4

3

2

1

0402

C12004 10u

4V

0603

C12002 22u

4V

0402

C12005 10u

4V

0402

C12024 10u

0603

C12003 22u

4V

4V

5

6.3V

0402

C12011 10u

4V

DNP

C12025 10u

0402

VCCPLL_OC

VCCST_CPU

from 1VSB, control SLP_S4 (S3 rail)

C12040

6.3V

1u

0402

VCCSTG

0402

C12041 10u

4V

VCCST_CPU

C12049
1u

0402

REMOVED +VCCEDRAM & +VCCEOPIO RAILS

4

6.3V

C12042
1u

0402

VCORE

AU23
AU28
AU35
AU42

BB23
BB32
BB41
BB47
BB51

AM40

A18

A22

AL23

K20
K21

6.3V

A30
A34
A39

A44
AK33
AK35
AK37
AK38
AK40
AL33
AL37
AL40

AM32
AM33
AM35
AM37
AM38

G30

K32

AK32

AB62

P62

V62

H63

G61

AC63

AE63

AE62

AG62

AL63

AJ62

U10001N

VDDQ_AU23
VDDQ_AU28
VDDQ_AU35
VDDQ_AU42
VDDQ_BB23
VDDQ_BB32
VDDQ_BB41
VDDQ_BB47
VDDQ_BB51

VDDQC

VCCST

VCCSTG_A22

VCCPLL_OC

VCCPLL_K20
VCCPLL_K21

KBL-R U42

<$LOCATION>
<MATERIAL>
14 OF 20
REV = 1

KBL_R_U42

CPU POWER 3 OF 4

U10001L

VCCCORE_A30
VCCCORE_A34
VCCCORE_A39
VCCCORE_A44
VCCCORE_AK33
VCCCORE_AK35
VCCCORE_AK37
VCCCORE_AK38
VCCCORE_AK40
VCCCORE_AL33
VCCCORE_AL37
VCCCORE_AL40
VCCCORE_AM32
VCCCORE_AM33
VCCCORE_AM35
VCCCORE_AM37
VCCCORE_AM38
VCCCORE_G30

RSVD_K32

RSVD_AK32

VCCOPC_AB62
VCCOPC_P62
VCCOPC_V62

VCC_OPC_1P8_H63

VCC_OPC_1P8_G61

VCCOPC_SENSE
VSSOPC_SENSE

VCCEOPIO_AE62
VCCEOPIO_AG62

VCCEOPIO_SENSE
VSSEOPIO_SENSE

KBL-R U42

<$LOCATION>
<MATERIAL>
12 OF 20
REV = 1

KBL_R_U42

CPU POWER 1 OF 4

VCCIO_AK28
VCCIO_AK30
VCCIO_AL30

VCCIO_AL42
VCCIO_AM28
VCCIO_AM30
VCCIO_AM42

VCCSA_AK23
VCCSA_AK25

VCCSA_G23
VCCSA_G25
VCCSA_G27
VCCSA_G28

VCCSA_J22
VCCSA_J23

VCCSA_J27
VCCSA_K23
VCCSA_K25
VCCSA_K27
VCCSA_K28
VCCSA_K30

VCCIO_SENSE

VSSIO_SENSE

VSSSA_SENSE

VCCSA_SENSE

3

AK28
AK30
AL30
AL42
AM28
AM30
AM42

AK23
AK25
G23
G25
G27
G28
J22
J23
J27
K23
K25
K27
K28
K30

AM23
AM22

H21
H20

VCCCORE_G32
VCCCORE_G33
VCCCORE_G35
VCCCORE_G37
VCCCORE_G38
VCCCORE_G40
VCCCORE_G42

VCCCORE_J30
VCCCORE_J33
VCCCORE_J37

VCCCORE_J40
VCCCORE_K33
VCCCORE_K35
VCCCORE_K37
VCCCORE_K38
VCCCORE_K40
VCCCORE_K42
VCCCORE_K43

VCC_SENSE

VSS_SENSE

VIDALERT#

VIDSCK

VIDSOUT

VCCSTG_G20

C12089
10p 50V

0201

VCCIO_SENSE [58]
VSSIO_SENSE [58]

VSSSA_SENSE [66]

VCCSA_SENSE [66]

VCORE

G32
G33
G35
G37
G38
G40
G42
J30
J33
J37
J40
K33
K35
K37
K38
K40
K42
K43

E32
E33

B63
A63
D64

G20

H_CPU_SVIDALERT_N
H_CPU_SVIDCLK
H_CPU_SVIDDAT

VCCSTG

VCCIO

6.3V

0402

C12020 1u

C12090
10p 50V

0201

VCC_CORE_SENSE [66]

VSS_CORE_SENSE [66]

+VCCSTG is control by SLP_S0,
but it can overwrite by XDP, that
means it need power for XDP intrafece

6.3V

0402

C12021 1u

C12043
10u 6.3V

0402

6.3V

0402

C12022 1u

R12005 220 0201
R12006 0 0201
R12007 0 0201

6.3V

0402

C12023 1u

C12044
10u 6.3V

0402

C12045
10u 6.3V

0402

U SPECIFIC

2

C12050
22u 6.3V

0603

C12046
10u 6.3V

0402

0201

Microsoft Confidential

Microsoft Confidential

Microsoft Confidential

Size Project Name Rev

Size Project Name Rev

Size Project Name Rev

B

B

B

Date: Sheet of

Date: Sheet of

Date: Sheet of

C12051
22u 6.3V

0603

C12047
10u 6.3V

0402

VCCST_CPU

R12004 56

R12003 100

A

A

A

0201

Title:

Title:

Title:

Engineer:

Engineer:

Engineer:

VCCSA

C12048
10u 6.3V

0402

SVID_ALERT# [66]
VIDSCLK [66]
VIDSOUT [66]

C12034
47u 6.3V

0603

VCCSA

C12069
10u 6.3V

0402

12. CPU(3)_SKL POWER1

12. CPU(3)_SKL POWER1

12. CPU(3)_SKL POWER1

Surface

Surface

Surface

12 79Tuesday, May 01, 2018

12 79Tuesday, May 01, 2018

1

12 79Tuesday, May 01, 2018

C12033
47u 6.3V

0603

DNP

C12070
10u 6.3V

0402

1.0.0.1

1.0.0.1

1.0.0.1

4V

0603

C12001 22u

D D

4V

0402

C12010 10u

C C

B B

A A

5

Vinafix.com

KBL_R_U42

A48
A53
A58
A62

A66
AA63
AA64
AA66
AA67
AA69
AA70
AA71

AC64
AC65
AC66
AC67
AC68
AC69
AC70
AC71

J43

J45

J46

J48

J50

J52

J53

J55

J56

J58

J60

K48

K50

K52

K53

K55

K56

K58

K60

L62

L63

L64

L65

L66

L67

L68

L69

L70

L71

M62
N63
N64
N66
N67
N69

J70

J69

U10001M

CPU POWER 2 OF 4

VCCCORE_A48
VCCCORE_A53
VCCGT_A58
VCCGT_A62
VCCGT_A66
VCCGT_AA63
VCCGT_AA64
VCCGT_AA66
VCCGT_AA67
VCCGT_AA69
VCCGT_AA70
VCCGT_AA71
VCCGT_AC64
VCCGT_AC65
VCCGT_AC66
VCCGT_AC67
VCCGT_AC68
VCCGT_AC69
VCCGT_AC70
VCCGT_AC71
VCCCORE_J43
VCCCORE_J45
VCCCORE_J46
VCCCORE_J48
VCCCORE_J50
VCCCORE_J52
VCCGT_J53
VCCGT_J55
VCCGT_J56
VCCGT_J58
VCCGT_J60
VCCCORE_K48
VCCCORE_K50
RSVD_K52
VCCGT_K53
VCCGT_K55
VCCGT_K56
VCCGT_K58
VCCGT_K60
VCCGT_L62
VCCGT_L63
VCCGT_L64
VCCGT_L65
VCCGT_L66
VCCGT_L67
VCCGT_L68
VCCGT_L69
VCCGT_L70
VCCGT_L71
VCCGT_M62
VCCGT_N63
VCCGT_N64
VCCGT_N66
VCCGT_N67
VCCGT_N69

VCCGT_SENSE
VSSGT_SENSE

VCCGT_N70
VCCGT_N71
VCCGT_R63
VCCGT_R64
VCCGT_R65
VCCGT_R66
VCCGT_R67
VCCGT_R68
VCCGT_R69
VCCGT_R70
VCCGT_R71

VCCGT_T62
VCCGT_U65
VCCGT_U68
VCCGT_U71

VCCGT_W63
VCCGT_W64
VCCGT_W65
VCCGT_W66
VCCGT_W67
VCCGT_W68
VCCGT_W69
VCCGT_W70
VCCGT_W71

VCCGT_Y62

VCCCORE_AK42
VCCCORE_AK43
VCCCORE_AK45
VCCCORE_AK46
VCCCORE_AK48
VCCCORE_AK50

RSVD_AK52

VCCGTX_AK53
VCCGTX_AK55
VCCGTX_AK56
VCCGTX_AK58
VCCGTX_AK60

VCCGTX_AK70
VCCCORE_AL43
VCCCORE_AL46
VCCCORE_AL50

VCCGTX_AL53

VCCGTX_AL56

VCCGTX_AL60

VCCCORE_AM48
VCCCORE_AM50
VCCCORE_AM52

VCCGTX_AM53
VCCGTX_AM56
VCCGTX_AM58
VCCGTX_AU58
VCCGTX_AU63

VCCGTX_BB57

VCCGTX_BB66

VCCGTX_SENSE

VSSGTX_SENSE

N70
N71
R63
R64
R65
R66
R67
R68
R69
R70
R71
T62
U65
U68
U71
W63
W64
W65
W66
W67
W68
W69
W70
W71
Y62

AK42
AK43
AK45
AK46
AK48
AK50
AK52
AK53
AK55
AK56
AK58
AK60
AK70
AL43
AL46
AL50
AL53
AL56
AL60
AM48
AM50
AM52
AM53
AM56
AM58
AU58
AU63
BB57
BB66

AK62
AL61

VCORE

D D

C C

VCCGT_SENSE[66]
VSSGT_SENSE[66]

4

VCCGTVCCGT

VCORE

VCCGT

3

2

1

Place on primary side, beside the package

C13017
10u 6.3V

0402

C13322
10u 6.3V

0402

C13018
10u 6.3V

0402

C13323
10u 6.3V

0402

C13019
10u 6.3V

0402

C13335
10u 6.3V

0402

C13020
10u 6.3V

0402

C13336
10u 6.3V

0402

C13021
10u 6.3V

0402

C13337
10u 6.3V

0402

C13022
10u 6.3V

0402

C13338
10u 6.3V

0402

C13023
10u 6.3V

0402

C13024
10u 6.3V

0402

C13025
10u 6.3V

0402

C13026
10u 6.3V

0402

Place on secondary side
under the package

C13027
10u 6.3V

0402

VCCGT

C13028
10u 6.3V

0402

VCORE

KBL-R U42

<$LOCATION>
<MATERIAL>
13 OF 20
REV = 1

REMOVED GTX Connections

C13164

1u

6.3V
0201

C13165

1u

6.3V
0201

C13166

1u

6.3V
0201

VCCGT

Place on primary side, beside the package

C13083
10u 6.3V

0402

C13090
10u 6.3V

0402

B B

VCORE

C13190
47u 6.3V

0603

C13197
47u 6.3V

0603

C13084
10u 6.3V

0402

C13091

6.3V

10u

0402

C13191
47u 6.3V

0603

C13198
47u 6.3V

0603

C13330
10u 6.3V

0402

C13085
10u 6.3V

0402

C13097
10u 6.3V

0402

C13192
47u 6.3V

0603

C13199
47u 6.3V

0603

C13332
10u 6.3V

0402

C13086
10u 6.3V

0402

C13098
10u 6.3V

0402

C13193
47u 6.3V

0805

C13200
47u 6.3V

0603
DNP

C13333
10u 6.3V

0402

C13087
10u 6.3V

0402

C13099
10u 6.3V

0402

C13194
47u 6.3V

0805

C13201
47u 6.3V

0603

C13329
10u 6.3V

0402

C13088
10u 6.3V

0402

C13195
47u 6.3V

0603

C13202
47u 6.3V

0603

C13331
10u 6.3V

0402

C13089
10u 6.3V

0402

C13196
47u 6.3V

0603

C13203
47u 6.3V

0603

C13334
10u 6.3V

0402

VCCGT

Place on primary side, beside the package

C13300
22u

0603

C13306
22u

0603
DNP

6.3V

6.3V

C13301
22u

0603

C13307
22u

0603
DNP

6.3V

6.3V

C13302
22u

0603

C13308
22u

0603
DNP

6.3V

6.3V

C13303
22u

0603

C13309
22u

0603
DNP

6.3V

6.3V

C13304
22u

0603

C13310
22u

0603
DNP

6.3V

6.3V

C13311
22u

0603

C13314
22u

0603
DNP

6.3V

6.3V

C13312
22u

0603

C13315
22u

0603
DNP

6.3V

6.3V

C13313
22u

0603
DNP

C13316
22u

0603
DNP

6.3V

6.3V

C13317
22u

0603
DNP

6.3V

C13167

1u

6.3V
0201

C13168

1u

6.3V
0201

C13169

1u

6.3V
0201

DNP

DNP

C13343
10u 6.3V

0402

C13348
10u 6.3V

0402

DNP

DNP

C13341
10u 6.3V

0402

C13346
10u 6.3V

0402

C13340
10u 6.3V

0402

DNP

C13345
10u 6.3V

0402

A A

DNP

VCORE

C13339

6.3V

10u

0402

DNP

C13344

6.3V

10u

0402

DNP

Place on secondary side
under the package

C13171

1u

0201

6.3V

5

C13172

1u

0201

6.3V

C13170

1u

0201

6.3V

DNP

DNP

C13342
10u 6.3V

0402

C13347
10u 6.3V

0402

VCORE

Place on secondary side
under the package

C13173

1u

0201

6.3V

C13174

1u

0201

6.3V

4

C13175

1u

0201

6.3V

VCCGT

Place on primary side, beside the package

C13122
47u 6.3V

DNP

3

0603

C13123
47u 6.3V

0805

DNP

C13131
47u 6.3V

0805

DNP

C13106
47u 6.3V

0603

C13107
47u 6.3V

0603

C13108
47u 6.3V

2

C13109

47u 6.3V

0603
DNP

DNP
0603

U SPECIFIC

C13305
47u 6.3V

0805

DNP

C13318
47u 6.3V

0603

DNP

Size Project Name Rev

Size Project Name Rev

Size Project Name Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

C13319
47u 6.3V

0805
DNP

Microsoft Conf idential

Microsoft Conf idential

Microsoft Conf idential

C

C

C

C13320
47u 6.3V

0603

DNP

Title:

Title:

Title:

Engineer:

Engineer:

Engineer:

A

A

A

C13321
47u 6.3V

0805

DNP

13. CPU(4)_SKL_POWER2

13. CPU(4)_SKL_POWER2

13. CPU(4)_SKL_POWER2

Surface

Surface

Surface

13 79Tuesday, May 01, 2018

13 79Tuesday, May 01, 2018

1

13 79Tuesday, May 01, 2018

1.0.0.1

1.0.0.1

1.0.0.1

5

Vinafix.com

U10001P

KBL_R_U42

GND 1 OF 3

A5

VSS_A5

A67

VSS_A67

A70

VSS_A70

AA2

D D

C C

AG16
AG17
AG18
AG19
AG20
AG21
AG71

B B

AA4
AA65
AA68
AB15
AB16
AB18
AB21

AB8
AD13
AD16
AD19
AD20
AD21
AD62

AD8
AE64
AE65
AE66
AE67
AE68
AE69

AF1
AF10
AF15
AF17

AF2

AF4
AF63

AH13

AH6
AH63
AH64
AH67

AJ15
AJ18
AJ20

AJ4
AK11
AK16
AK18
AK21
AK22
AK27
AK63
AK68
AK69

AK8

AL2

AL28
AL32
AL35
AL38

AL4

AL45
AL48
AL52
AL55
AL58
AL64

VSS_AA2
VSS_AA4
VSS_AA65
VSS_AA68
VSS_AB15
VSS_AB16
VSS_AB18
VSS_AB21
VSS_AB8
VSS_AD13
VSS_AD16
VSS_AD19
VSS_AD20
VSS_AD21
VSS_AD62
VSS_AD8
VSS_AE64
VSS_AE65
VSS_AE66
VSS_AE67
VSS_AE68
VSS_AE69
VSS_AF1
VSS_AF10
VSS_AF15
VSS_AF17
VSS_AF2
VSS_AF4
VSS_AF63
VSS_AG16
VSS_AG17
VSS_AG18
VSS_AG19
VSS_AG20
VSS_AG21
VSS_AG71
VSS_AH13
VSS_AH6
VSS_AH63
VSS_AH64
VSS_AH67
VSS_AJ15
VSS_AJ18
VSS_AJ20
VSS_AJ4
VSS_AK11
VSS_AK16
VSS_AK18
VSS_AK21
VSS_AK22
VSS_AK27
VSS_AK63
VSS_AK68
VSS_AK69
VSS_AK8
VSS_AL2
VSS_AL28
VSS_AL32
VSS_AL35
VSS_AL38
VSS_AL4
VSS_AL45
VSS_AL48
VSS_AL52
VSS_AL55
VSS_AL58
VSS_AL64

VSS_AL65

VSS_AL66
VSS_AM13
VSS_AM21
VSS_AM25
VSS_AM27
VSS_AM43
VSS_AM45
VSS_AM46
VSS_AM55
VSS_AM60
VSS_AM61
VSS_AM68
VSS_AM71

VSS_AM8
VSS_AN20
VSS_AN23
VSS_AN28
VSS_AN30
VSS_AN32
VSS_AN33
VSS_AN35
VSS_AN37
VSS_AN38
VSS_AN40
VSS_AN42
VSS_AN58
VSS_AN63
VSS_AP10
VSS_AP18
VSS_AP20
VSS_AP23
VSS_AP28
VSS_AP32
VSS_AP35
VSS_AP38
VSS_AP42
VSS_AP58
VSS_AP63
VSS_AP68
VSS_AP70
VSS_AR11
VSS_AR15
VSS_AR16
VSS_AR20
VSS_AR23
VSS_AR28
VSS_AR35
VSS_AR42
VSS_AR43
VSS_AR45
VSS_AR46
VSS_AR48

VSS_AR5
VSS_AR50
VSS_AR52
VSS_AR53
VSS_AR55
VSS_AR58
VSS_AR63

VSS_AR8

VSS_AT2
VSS_AT20
VSS_AT23
VSS_AT28
VSS_AT35

VSS_AT4
VSS_AT42
VSS_AT56
VSS_AT58

AL65
AL66
AM13
AM21
AM25
AM27
AM43
AM45
AM46
AM55
AM60
AM61
AM68
AM71
AM8
AN20
AN23
AN28
AN30
AN32
AN33
AN35
AN37
AN38
AN40
AN42
AN58
AN63
AP10
AP18
AP20
AP23
AP28
AP32
AP35
AP38
AP42
AP58
AP63
AP68
AP70
AR11
AR15
AR16
AR20
AR23
AR28
AR35
AR42
AR43
AR45
AR46
AR48
AR5
AR50
AR52
AR53
AR55
AR58
AR63
AR8
AT2
AT20
AT23
AT28
AT35
AT4
AT42
AT56
AT58

4

AT63
AT68

AT71
AU10
AU15
AU20
AU32
AU38

AV1
AV68
AV69
AV70
AV71

AW10
AW12
AW14
AW16
AW18
AW21
AW23
AW26
AW28
AW30
AW32
AW34
AW36
AW38
AW41
AW43
AW45
AW47
AW49
AW51
AW53
AW55
AW57

AW6
AW60
AW62
AW64
AW66

AW8

AY66

B10
B14
B18
B22
B30
B34
B39
B44
B48
B53
B58
B62
B66
B71

BA1
BA10
BA14
BA18

BA2
BA23
BA28
BA32
BA36

F68

BA45

U10001Q

KBL_R_U42

GND 2 OF 3

VSS_AT63
VSS_AT68
VSS_AT71
VSS_AU10
VSS_AU15
VSS_AU20
VSS_AU32
VSS_AU38
VSS_AV1
VSS_AV68
VSS_AV69
VSS_AV70
VSS_AV71
VSS_AW10
VSS_AW12
VSS_AW14
VSS_AW16
VSS_AW18
VSS_AW21
VSS_AW23
VSS_AW26
VSS_AW28
VSS_AW30
VSS_AW32
VSS_AW34
VSS_AW36
VSS_AW38
VSS_AW41
VSS_AW43
VSS_AW45
VSS_AW47
VSS_AW49
VSS_AW51
VSS_AW53
VSS_AW55
VSS_AW57
VSS_AW6
VSS_AW60
VSS_AW62
VSS_AW64
VSS_AW66
VSS_AW8
VSS_AY66
VSS_B10
VSS_B14
VSS_B18
VSS_B22
VSS_B30
VSS_B34
VSS_B39
VSS_B44
VSS_B48
VSS_B53
VSS_B58
VSS_B62
VSS_B66
VSS_B71
VSS_BA1
VSS_BA10
VSS_BA14
VSS_BA18
VSS_BA2
VSS_BA23
VSS_BA28
VSS_BA32
VSS_BA36
VSS_F68
VSS_BA45

VSS_BA49
VSS_BA53
VSS_BA57

VSS_BA6
VSS_BA62
VSS_BA66
VSS_BA71
VSS_BB18
VSS_BB26
VSS_BB30
VSS_BB34
VSS_BB38
VSS_BB43
VSS_BB55

VSS_BB6
VSS_BB60
VSS_BB64
VSS_BB67
VSS_BB70

VSS_C1

VSS_C25

VSS_C5
VSS_D10
VSS_D11
VSS_D14
VSS_D18
VSS_D22
VSS_D25
VSS_D26
VSS_D30
VSS_D34
VSS_D39
VSS_D44
VSS_D45
VSS_D47
VSS_D48
VSS_D53
VSS_D58

VSS_D6
VSS_D62
VSS_D66
VSS_D69
VSS_E11
VSS_E15
VSS_E18
VSS_E21
VSS_E46
VSS_E50
VSS_E53
VSS_E56

VSS_E6
VSS_E65
VSS_E71

VSS_F1

VSS_F13

VSS_F2
VSS_F22
VSS_F23
VSS_F27
VSS_F28
VSS_F32
VSS_F33
VSS_F35
VSS_F37
VSS_F38

VSS_F4
VSS_F40
VSS_F42

VSS_BA41

BA49
BA53
BA57
BA6
BA62
BA66
BA71
BB18
BB26
BB30
BB34
BB38
BB43
BB55
BB6
BB60
BB64
BB67
BB70
C1
C25
C5
D10
D11
D14
D18
D22
D25
D26
D30
D34
D39
D44
D45
D47
D48
D53
D58
D6
D62
D66
D69
E11
E15
E18
E21
E46
E50
E53
E56
E6
E65
E71
F1
F13
F2
F22
F23
F27
F28
F32
F33
F35
F37
F38
F4
F40
F42
BA41

3

U10001R

KBL_R_U42

GND 3 OF 3

F8
G10
G22
G43
G45
G48

G5
G52
G55
G58

G6
G60
G63
G66
H15
H18
H71

J11
J13
J25
J28
J32
J35
J38
J42

J8
K16
K18
K22
K61
K63
K64
K65
K66
K67
K68
K70
K71

L11
L16
L17

KBL-R U42

<$LOCATION>
<MATERIAL>
18 OF 20
REV = 1

VSS_F8
VSS_G10
VSS_G22
VSS_G43
VSS_G45
VSS_G48
VSS_G5
VSS_G52
VSS_G55
VSS_G58
VSS_G6
VSS_G60
VSS_G63
VSS_G66
VSS_H15
VSS_H18
VSS_H71
VSS_J11
VSS_J13
VSS_J25
VSS_J28
VSS_J32
VSS_J35
VSS_J38
VSS_J42
VSS_J8
VSS_K16
VSS_K18
VSS_K22
VSS_K61
VSS_K63
VSS_K64
VSS_K65
VSS_K66
VSS_K67
VSS_K68
VSS_K70
VSS_K71
VSS_L11
VSS_L16
VSS_L17

VSS_L18

VSS_L2

VSS_L20

VSS_L4

VSS_L8
VSS_N10
VSS_N13
VSS_N19
VSS_N21

VSS_N6
VSS_N65
VSS_N68
VSS_P17
VSS_P19
VSS_P20
VSS_P21
VSS_R13

VSS_R6
VSS_T15
VSS_T17
VSS_T18

VSS_T2
VSS_T21

VSS_T4
VSS_U10
VSS_U63
VSS_U64
VSS_U66
VSS_U67
VSS_U69
VSS_U70
VSS_V16
VSS_V17
VSS_V18

VSS_W13

VSS_W6

VSS_W9
VSS_Y17
VSS_Y19
VSS_Y20
VSS_Y21

L18
L2
L20
L4
L8
N10
N13
N19
N21
N6
N65
N68
P17
P19
P20
P21
R13
R6
T15
T17
T18
T2
T21
T4
U10
U63
U64
U66
U67
U69
U70
V16
V17
V18
W13
W6
W9
Y17
Y19
Y20
Y21

2

1

KBL-R U42

A A

<$LOCATION>
<MATERIAL>
16 OF 20
REV = 1

5

4

KBL-R U42

<$LOCATION>
<MATERIAL>
17 OF 20
REV = 1

14. CPU(5)_GND

14. CPU(5)_GND

Title:

Title:

Title:

Microsoft Confidential

Microsoft Confidential

Microsoft Confidential

Size Project Name Rev

Size Project Name Rev

Size Project Name Rev

B

B

U SPECIFIC

3

2

B

Date: Sheet of

Date: Sheet of

Date: Sheet of

A

A

A

Engineer:

Engineer:

Engineer:

14. CPU(5)_GND

Surface

Surface

Surface

14 79Friday, April 27, 2018

14 79Friday, April 27, 2018

1

14 79Friday, April 27, 2018

1.0.0.1

1.0.0.1

1.0.0.1

5

Vinafix.com

Vinafix.com

4

3

2

1

KBL_R_U42

RSVD_TP_BB68
RSVD_TP_BB69

RSVD_TP_AK13
RSVD_TP_AK12

RSVD_BB2
RSVD_BA3

TP5
TP6

RSVD_D5
RSVD_D4
RSVD_B2
RSVD_C2

RSVD_B3
RSVD_A3

RSVD_AW1

RSVD_E1
RSVD_E2

RSVD_BA4
RSVD_BB4

RSVD_A4
RSVD_C4

TP4

RSVD_A69
RSVD_B69

RSVD_AY3

RSVD_D71
RSVD_C70

RSVD_C54
RSVD_D54

TP1
TP2

VSS_AY71

ZVM#

RSVD_TP_AW71
RSVD_TP_AW70

MSM#

PROC_SELECT#

BB68
BB69

AK13
AK12

BB2
BA3

AU5
AT5

D5
D4
B2
C2

B3
A3

AW1

E1
E2

BA4
BB4

A4
C4

BB5

A69
B69

AY3

D71
C70

C54
D54

AY4
BB3

AY71
AR56

AW71
AW70

AP56
C64

RSVD_TP_AK13
RSVD_TP_AK12

SMD RND 22.8mil

GTP15002
GTP15003

SMD RND 22.8mil

GTP15004

SMD RND 22.8mil

ZVM# and MSM# may need to
control the VCCOPC and VCCEOPIO

E68

B67
D65
D67

E70
C68
D68
C67

F71

G69

F70

G68

H70

G71

H69

G70

E63

F63

E66

F66

E60

E8

AY2
AY1

D1
D3

K46

K45

AL25
AL27

C71

B70

F60

A52

BA70
BA68

J71
J68

F65

G65

F61

E61

U10001S

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]

CFG[16]
CFG[17]

CFG[18]
CFG[19]

CFG_RCOMP

ITP_PMODE

RSVD_AY2
RSVD_AY1

RSVD_D1
RSVD_D3

RSVD_K46
RSVD_K45

RSVD_AL25
RSVD_AL27

RSVD_C71
RSVD_B70

RSVD_F60

RSVD_A52

RSVD_TP_BA70
RSVD_TP_BA68

RSVD_J71
RSVD_J68

VSS_F65
VSS_G65

RSVD_F61
RSVD_E61

KBL-R U42

<$LOCATION>
<MATERIAL>
19 OF 20
REV = 1

RESERVED SIGNALS-1

GTP15001

SMD RND 22.8mil

CFG0[18]
CFG1[18]
CFG2[18]
CFG3[18]

D D

CFG4

0 enable eDP

Default

C C

B B

1

Disable eDP

CFG4[18]
CFG5[18]
CFG6[18]
CFG7[18]
CFG8[18]
CFG9[18]
CFG10[18]
CFG11[18]
CFG12[18]
CFG13[18]
CFG14[18]
CFG15[18]

CFG16[18]
CFG17[18]

CFG18[18]
CFG19[18]

AW69
AW68

AU56

AW48

U10001T

C7
U12
U11
H11

KBL-R U42

<$LOCATION>
<MATERIAL>
20 OF 20
REV = 1

KBL_R_U42

RSVD_AW69
RSVD_AW68
RSVD_AU56
RSVD_AW48
XTAL24_OUT
RSVD_U12
RSVD_U11
RSVD_H11

R15001 49.9

R15002
1K

0201

RSVD/XTAL

0201

ITP_PMODE[18]

RSVD_F6
XTAL24_IN
RSVD_C11
RSVD_B11
RSVD_A11
RSVD_D12
RSVD_C12

RSVD_F52

F6
E3
C11
B11
A11
D12
C12
F52

XTAL_24M_OUT

CFG_RCOMP

XTAL_24M_IN

R1504 1M

0201S_P28-W35

X150124MHz

R1503 0

0201S_P28-W35

C1503

A A

5

50V

0201S_P33

10p

4

3 1

GND

X948599-001

24

C1502

50V

10p

0201S_P33

15. CPU(6)_CFG_RESERVED

15. CPU(6)_CFG_RESERVED

Title:

Title:

Title:

Microsoft Confidential

Microsoft Confidential

Microsoft Confidential

Size Project Name Rev

Size Project Name Rev

Size Project Name Rev

B

B

U SPECIFIC

3

2

B

Date: Sheet of

Date: Sheet of

Date: Sheet of

A

A

A

Engineer:

Engineer:

Engineer:

15. CPU(6)_CFG_RESERVED

Surface

Surface

Surface

1.0.0.1

1.0.0.1

1.0.0.1

15 79Friday, April 27, 2018

15 79Friday, April 27, 2018

1

15 79Friday, April 27, 2018

5

Vinafix.com

U16001
H9CCNNN BLTBLAR-NUD

M_A_CAA0
M_A_CAA1
M_A_CAA2
M_A_CAA3
M_A_CAA4
M_A_CAA5
M_A_CAA6
M_A_CAA7
M_A_CAA8
M_A_CAA9

D D

M_A_DIM0_CLKP1[11,16]
M_A_DIM0_CLKN 1[11,16]

M_A_DIM0_CKE2[11,16]
M_A_DIM0_CKE3[11,16] M_A_DIM0_CKE1[11,16]

M_A_DIM0_CS0_N[11,16]
M_A_DIM0_CS1_N[11,16]

M_A_DQSP2[11]
M_A_DQSN2[11]

C C

B B

V0P6DX_LPDDR3

A A

M_A_DQSP0[11]
M_A_DQSN0[11]

M_A_DQSP3[11]
M_A_DQSN3[11]

M_A_DQSP1[11]
M_A_DQSN1[11]

C16072
1u

6.3V
0402

distributed along terminations. Shown in blue
Figure 4-57 in PDG2.0

C16073
1u

6.3V
0402

C16074
1u

6.3V
0402

R2
P2
N2
N3

M3

F3
E3
E2
D2
C2

J3
J2

K3
K4

L3
L4

L8

G8

P8
D8

A1

A2
A12
A13

B1
B13

T1
T13

U1

U2
U12
U13

L10
L11

G10
G11

P10
P11

D10
D11

B2

B5

C5

E4

E5

F5

H2
J12

K2

L6

M5

N4

N5

R4

R5

T2

T3

T4

T5

C3

D3

F4

G3
G4

J4

M4

P3

B6

B12

C6

D12

E6

F6
F12

G6

G9
H10
K10

L9

M6
M12

N6

P12

R6
T6

T12

C16075
1u

6.3V
0402

CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
CA9

CK
CK#

CKE0
CKE1

CS#0
CS#1

DM0
DM1
DM2
DM3/NC

DNU1
DNU2
DNU3
DNU4
DNU5
DNU6
DNU7
DNU8
DNU9
DNU10
DNU11
DNU12

DQS0
DQS0#

DQS1
DQS1#

DQS2/NC
DQS2#/NC

DQS3/NC
DQS3#/NC

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19

VSSCA1
VSSCA2
VSSCA3
VSSCA4
VSSCA5
VSSCA6
VSSCA7
VSSCA8

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ15
VSSQ16
VSSQ17
VSSQ18
VSSQ19

TBL1601

C16076
1u

6.3V
0402

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

DQ16/NC
DQ17/NC
DQ18/NC
DQ19/NC
DQ20/NC
DQ21/NC
DQ22/NC
DQ23/NC
DQ24/NC
DQ25/NC
DQ26/NC
DQ27/NC
DQ28/NC
DQ29/NC
DQ30/NC
DQ31/NC

VDD1_1
VDD1_3
VDD1_5
VDD1_7
VDD1_9
VDD1_2
VDD1_4
VDD1_6
VDD1_8

VDD1_10

VDD2_1
VDD2_2
VDD2_3
VDD2_4
VDD2_5
VDD2_6
VDD2_7
VDD2_8

VDD2_9
VDD2_10
VDD2_11
VDD2_12
VDD2_13
VDD2_14
VDD2_15
VDD2_16
VDD2_17
VDD2_18
VDD2_19
VDD2_20

VDDCA1
VDDCA2
VDDCA3
VDDCA4
VDDCA5

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17

VREFCA
VREFDQ

ODT

ZQ0
ZQ1

NC1
NC2
NC3

C16077
1u

6.3V
0402

P9
N9
N10
N11
M8
M9
M10
M11
F11
F10
F9
F8
E11
E10
E9
D9
T8
T9
T10
T11
R8
R9
R10
R11
C11
C10
C9
C8
B11
B10
B9
B8

A3
A4
A5
A6
A10
U3
U4
U5
U6
U10

A8
A9
D4
D5
D6
G5
H5
H6
H12
J5
J6
K5
K6
K12
L5
P4
P5
P6
U8
U9

F2
G2
H3
L2
M2

A11
C12
E8
E12
G12
H8
H9
H11
J9
J10
K8
K11
L12
N8
N12
R12
U11

H4
J11

J8

B3
B4

C4
K9
R3

ZQ1601
ZQ1602

C16078
1u

6.3V
0402

M_A_D16
M_A_D17
M_A_D23
M_A_D18
M_A_D21
M_A_D20
M_A_D22
M_A_D19
M_A_D7
M_A_D0
M_A_D4
M_A_D1
M_A_D6
M_A_D3
M_A_D5
M_A_D2

M_A_D29
M_A_D28
M_A_D31
M_A_D26
M_A_D25
M_A_D24
M_A_D27
M_A_D30
M_A_D9
M_A_D12
M_A_D15
M_A_D11
M_A_D13
M_A_D8
M_A_D14
M_A_D10

V1P2U

V1P2U

V1P2U

M_A_DIM0_ODT0 [11,16]

R16034 2431%
R16035 2431%

C16079
1u

6.3V
0402

0402

0402
TBL1601

DNP For 4GB System
Memory: R16035, R16036

M_A_D[23:16] [11]

M_A_D[7:0] [11]

M_A_D[31:24] [11]

M_A_D[15:8] [11]

V1P8U_2P5U

V_VREF_CA_DIM M

C16090
1u

6.3V
0402
DNP

4

M_A_CAB[9:0][11,16]

V_VREF_DQ_DIM M0

C16091
1u

6.3V
0402
DNP

C16092
1u

6.3V
0402
DNP

3

U16002
H9CCNNN BLTBLAR-NUD

M_A_CAB0
M_A_CAB1
M_A_CAB2
M_A_CAB3
M_A_CAB4
M_A_CAB5
M_A_CAB6
M_A_CAB7
M_A_CAB8
M_A_CAB9

M_A_DIM0_CLKP0[11,16]
M_A_DIM0_CLKN 0[11,16]

M_A_DIM0_CKE0[11,16]

M_A_DIM0_CS0_N[11,16]
M_A_DIM0_CS1_N[11,16]

M_A_DQSP7[11]
M_A_DQSN7[11]

M_A_DQSP4[11]
M_A_DQSN4[11]

M_A_DQSP6[11]
M_A_DQSN6[11]

M_A_DQSP5[11]
M_A_DQSN5[11]

C16093
1u

6.3V
0402
DNP

C16094
1u

6.3V
0402
DNP

C16095
1u

6.3V
0402
DNP

R2

CA0

P2

CA1

N2

CA2

N3

CA3

M3

CA4

F3

CA5

E3

CA6

E2

CA7

D2

CA8

C2

CA9

J3

CK

J2

CK#

K3

CKE0

K4

CKE1

L3

CS#0

L4

CS#1

L8

DM0

G8

DM1

P8

DM2

D8

DM3/NC

A1

DNU1

A2

DNU2

A12

DNU3

A13

DNU4

B1

DNU5

B13

DNU6

T1

DNU7

T13

DNU8

U1

DNU9

U2

DNU10

U12

DNU11

U13

DNU12

L10

DQS0

L11

DQS0#

G10

DQS1

G11

DQS1#

P10

DQS2/NC

P11

DQS2#/NC

D10

DQS3/NC

D11

DQS3#/NC

B2

VSS1

B5

VSS2

C5

VSS3

E4

VSS4

E5

VSS5

F5

VSS6

H2

VSS7

J12

VSS8

K2

VSS9

L6

VSS10

M5

VSS11

N4

VSS12

N5

VSS13

R4

VSS14

R5

VSS15

T2

VSS16

T3

VSS17

T4

VSS18

T5

VSS19

C3

VSSCA1

D3

VSSCA2

F4

VSSCA3

G3

VSSCA4

G4

VSSCA5

J4

VSSCA6

M4

VSSCA7

P3

VSSCA8

B6

VSSQ1

B12

VSSQ2

C6

VSSQ3

D12

VSSQ4

E6

VSSQ5

F6

VSSQ6

F12

VSSQ7

G6

VSSQ8

G9

VSSQ9

H10

VSSQ10

K10

VSSQ11

L9

VSSQ12

M6

VSSQ13

M12

VSSQ14

N6

VSSQ15

P12

VSSQ16

R6

VSSQ17

T6

VSSQ18

T12

VSSQ19

TBL1601

C16080

6.3V

22u

0603

Edge of vtt island.
Caps shown in green
Figure 4-57 in PDG2.0

DQ16/NC
DQ17/NC
DQ18/NC
DQ19/NC
DQ20/NC
DQ21/NC
DQ22/NC
DQ23/NC
DQ24/NC
DQ25/NC
DQ26/NC
DQ27/NC
DQ28/NC
DQ29/NC
DQ30/NC
DQ31/NC

VDD1_1
VDD1_3
VDD1_5
VDD1_7
VDD1_9
VDD1_2
VDD1_4
VDD1_6
VDD1_8

VDD1_10

VDD2_1
VDD2_2
VDD2_3
VDD2_4
VDD2_5
VDD2_6
VDD2_7
VDD2_8

VDD2_9
VDD2_10
VDD2_11
VDD2_12
VDD2_13
VDD2_14
VDD2_15
VDD2_16
VDD2_17
VDD2_18
VDD2_19
VDD2_20

VDDCA1
VDDCA2
VDDCA3
VDDCA4
VDDCA5

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17

VREFCA
VREFDQ

C16081
22u

0603

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

ODT

ZQ0

ZQ1

NC1

NC2

NC3

6.3V

M_A_D58

P9

M_A_D61

N9

M_A_D56

N10

M_A_D57

N11

M_A_D60

M8

M_A_D59

M9

M_A_D62

M10

M_A_D63

M11

M_A_D37

F11

M_A_D38

F10

M_A_D32

F9

M_A_D36

F8

M_A_D33

E11

M_A_D39

E10

M_A_D34

E9

M_A_D35

D9

M_A_D52

T8

M_A_D51

T9

M_A_D50

T10

M_A_D48

T11

M_A_D53

R8

M_A_D54

R9

M_A_D55

R10

M_A_D49

R11

M_A_D41

C11

M_A_D45

C10

M_A_D44

C9

M_A_D46

C8

M_A_D40

B11

M_A_D47

B10

M_A_D42

B9

M_A_D43

B8

A3
A4
A5
A6
A10
U3
U4
U5
U6
U10

A8
A9
D4
D5
D6
G5
H5
H6
H12
J5
J6
K5
K6
K12
L5
P4
P5
P6
U8
U9

F2
G2
H3
L2
M2

A11
C12
E8
E12
G12
H8
H9
H11
J9
J10
K8
K11
L12
N8
N12
R12
U11

H4
J11

J8

M_A_DIM0_ODT0 [11,16]

B3

ZQ1603

B4

ZQ1604

C4
K9
R3

V1P2U

V1P2U

R16033 2431%
R16036 2431%

M_A_D[63:56] [11]M_A_CAA[9:0][11,16]

V_VREF_CA_DIM M V_VREF_DQ_DIM M0

C16005
10u

6.3V

0402

C16065
1u

6.3V
0402

C16001
47000p

6.3V
0201

V1P8U_2P5U

C16011
1u

6.3V
0402

V1P2U

C16083
10u

6.3V

0402

M_A_D[39:32] [11]

M_A_D[55:48] [11]

M_A_D[47:40] [11]

V1P8U_2P5U

5 distributed. the Figure 4-56 at PDG2.0 the pink circle.

V1P8U_2P5U

C16010
1u

6.3V
0402

5 distributed.
Look the Figure
4-56 at PDG2.0
the blue circle.

3 near each
DRAM. Look
the Figure
4-55 at
PDG2.0 the

V1P2U

0402

0402
TBL1601

V1P2U

blue circle.

V_VREF_CA_DIM M

V_VREF_DQ_DIM M0

C16064
1u

6.3V
0402

C16082
10u

6.3V

0402

C16096
10p

50V
0201

C16023
1u

6.3V
0402

V1P2U

C16066
1u

6.3V
0402

C16002
47000p

6.3V
0201

R16021

0

0603

For 1.8V sensing

C16006
10u

6.3V

0402

C16018
10u

6.3V

0402

C16012
1u

6.3V
0402

C16024
1u

6.3V
0402

C16067
1u

6.3V
0402

C16084
10u

6.3V

0402

C16035

0.1u

6.3V
0201

C16043
1u

6.3V
0402

C16051
1u

6.3V
0402

C16061
10u

6.3V

0402

C16007
10u

6.3V

0402

2

C16003
47000p

6.3V
0201

1P8V_DUAL_VR_FB_R [58]

C16008
10u

6.3V

0402

GND

C16013
1u

6.3V
0402

C16014
1u

6.3V
0402

C16019
10u

6.3V

0402

C16025
1u

6.3V
0402

C16036

0.1u

6.3V
0201

C16044
1u

6.3V
0402

C16052
1u

6.3V
0402

C16068
1u

6.3V
0402

C16026
1u

6.3V
0402

C16059
10u

6.3V

0402

C16069
1u

6.3V
0402

3 distributed.
Look the Figure
4-56 at PDG2.0
the yellow
circle.

C16004
47000p

6.3V
0201

C16037

0.1u

6.3V
0201

C16045
1u

6.3V
0402

C16053
1u

6.3V
0402

C16009
10u

6.3V

0402

C16015
1u

6.3V
0402

C16020
10u

6.3V

0402

C16027
1u

6.3V
0402

C16038

0.1u

6.3V
0201

C16046
1u

6.3V
0402

C16054
1u

6.3V
0402

C16062
10u

6.3V

0402

C16070
1u

6.3V
0402

C16097
2p

25V
0201

M_A_CAB[9:0][11,16]

C16016
1u

6.3V
0402

10u
C16021

0402

6.3V

C16028
1u

6.3V
0402

C16039

0.1u

6.3V
0201

C16047
1u

6.3V
0402

C16055
1u

6.3V
0402

C16071
1u

6.3V
0402

C16017
1u

6.3V
0402

C16029
1u

6.3V
0402

C16040

0.1u

6.3V
0201

C16048
1u

6.3V
0402

C16056
1u

6.3V
0402

C16063
10u

6.3V

0402

2 near each DRAM.
Look the Figure
4-55 at PDG2.0
the yellow
circle.

M_A_CAA[9:0][11,16]

C16022
10u

6.3V

0402

M_A_DIM0_ODT0[11,16]
M_A_DIM0_CS0_N[11,16]
M_A_DIM0_CS1_N[11,16]
M_A_DIM0_CKE0[11,16]
M_A_DIM0_CKE1[11,16]
M_A_DIM0_CKE2[11,16]
M_A_DIM0_CKE3[11,16]

M_A_DIM0_CLKP0[11,16]
M_A_DIM0_CLKN 0[11,16]
M_A_DIM0_CLKP1[11,16]
M_A_DIM0_CLKN 1[11,16]

V1P2U

C16030
1u

6.3V
0402

C16041

0.1u

6.3V
0201

C16049
1u

6.3V
0402

C16057
1u

6.3V
0402

C16060
10u

6.3V

0402

1

M_A_CAA0
M_A_CAA1
M_A_CAA2
M_A_CAA3
M_A_CAA4
M_A_CAA5
M_A_CAA6
M_A_CAA7
M_A_CAA8
M_A_CAA9

M_A_CAB0
M_A_CAB1
M_A_CAB2
M_A_CAB3
M_A_CAB4
M_A_CAB5
M_A_CAB6
M_A_CAB7
M_A_CAB8
M_A_CAB9

2 near each DRAM.
Look the Figure
4-55 at PDG2.0
the pink circle.

R16037

0603

C16031
1u

6.3V
0402

C16042

0.1u

6.3V
0201

C16058
1u

6.3V
0402

5 distributed. Look
the Figure 4-56 at
PDG2.0 the red
circle (VDDQ).

R16001 68 5% 0201
R16002 68 5% 0201
R16003 68 5% 0201
R16004 68 5% 0201
R16005 68 5% 0201
R16006 68 5% 0201
R16007 68 5% 0201
R16008 68 5% 0201
R16009 68 5% 0201
R16010 68 5% 0201

R16011 68 5% 0201
R16012 68 5% 0201
R16013 68 5% 0201
R16014 68 5% 0201
R16015 68 5% 0201
R16016 68 5% 0201
R16017 68 5% 0201
R16018 68 5% 0201
R16019 68 5% 0201
R16020 68 5% 0201

R16022 80.6 0201
R16023 80.6 0201
R16024 80.6 0201
R16025 80.6 0201
R16026 80.6 0201
R16027 80.6 0201
R16028 80.6 0201

R16029 37.4 0201
R16030 37.4 0201
R16031 37.4 0201

R16032 37.4 0201

0

V1P2U_VR_FB_R [58]

For 1.2V sensing

C16032
1u

6.3V
0402

2 near each
DRAM. Look
the Figure
4-55 at
PDG2.0 the
red circle.

C16050
1u

6.3V
0402

4 near each DRAM.
Look the Figure 4-55
at PDG2.0 the red
circle (big one).

C16033
1u

6.3V
0402

TBL1601, SEE PAGE 23

V0P6DX_LPDDR3

C16034
1u

6.3V
0402

16. LPDDR3(1)_M EMORY DOW N

16. LPDDR3(1)_M EMORY DOW N

16. LPDDR3(1)_M EMORY DOW N

Title:

Title:

Microsoft Conf idential

Microsoft Conf idential

Microsoft Conf idential

Size Project Name Rev

Size Project Name Rev

Size Project Name Rev

C

C

5

4

3

2

U SPECIFIC

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

Title:

Surface

Surface

1

Surface

1.0.0.1

1.0.0.1

16 79Thursday, April 26, 2018

16 79Thursday, April 26, 2018

16 79Thursday, April 26, 2018

1.0.0.1

Engineer:

Engineer:

Engineer:

A

A

A

5

Vinafix.com

4

3

2

1

U17001

M_B_CAA[9:0][11,17] M_B_CAB[9:0][11,17]

D D

M_B_DIM0_CLKP0[11,17]
M_B_DIM0_CLKN 0[11,17]

M_B_DIM0_CKE0[11,17]
M_B_DIM0_CKE1[11,17]

M_B_DIM0_CS0_N[11,17]
M_B_DIM0_CS1_N[11,17]

M_B_DQSP0[11]

C C

B B

M_B_DQSN0[11]

M_B_DQSP3[11]
M_B_DQSN3[11]

M_B_DQSP2[11]
M_B_DQSN2[11]

M_B_DQSP1[11]
M_B_DQSN1[11]

M_B_CAA0
M_B_CAA1
M_B_CAA2
M_B_CAA3
M_B_CAA4
M_B_CAA5
M_B_CAA6
M_B_CAA7
M_B_CAA8
M_B_CAA9

H9CCNNN BLTBLAR-NUD

R2

CA0

P2

CA1

N2

CA2

N3

CA3

M3

CA4

F3

CA5

E3

CA6

E2

CA7

D2

CA8

C2

CA9

J3

CK

J2

CK#

K3

CKE0

K4

CKE1

L3

CS#0

L4

CS#1

L8

DM0

G8

DM1

P8

DM2

D8

DM3/NC

A1

DNU1

A2

DNU2

A12

DNU3

A13

DNU4

B1

DNU5

B13

DNU6

T1

DNU7

T13

DNU8

U1

DNU9

U2

DNU10

U12

DNU11

U13

DNU12

L10

DQS0

L11

DQS0#

G10

DQS1

G11

DQS1#

P10

DQS2/NC

P11

DQS2#/NC

D10

DQS3/NC

D11

DQS3#/NC

B2

VSS1

B5

VSS2

C5

VSS3

E4

VSS4

E5

VSS5

F5

VSS6

H2

VSS7

J12

VSS8

K2

VSS9

L6

VSS10

M5

VSS11

N4

VSS12

N5

VSS13

R4

VSS14

R5

VSS15

T2

VSS16

T3

VSS17

T4

VSS18

T5

VSS19

C3

VSSCA1

D3

VSSCA2

F4

VSSCA3

G3

VSSCA4

G4

VSSCA5

J4

VSSCA6

M4

VSSCA7

P3

VSSCA8

B6

VSSQ1

B12

VSSQ2

C6

VSSQ3

D12

VSSQ4

E6

VSSQ5

F6

VSSQ6

F12

VSSQ7

G6

VSSQ8

G9

VSSQ9

H10

VSSQ10

K10

VSSQ11

L9

VSSQ12

M6

VSSQ13

M12

VSSQ14

N6

VSSQ15

P12

VSSQ16

R6

VSSQ17

T6

VSSQ18

T12

VSSQ19

TBL1601

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

DQ16/NC
DQ17/NC
DQ18/NC
DQ19/NC
DQ20/NC
DQ21/NC
DQ22/NC
DQ23/NC
DQ24/NC
DQ25/NC
DQ26/NC
DQ27/NC
DQ28/NC
DQ29/NC
DQ30/NC
DQ31/NC

VDD1_1
VDD1_3
VDD1_5
VDD1_7
VDD1_9
VDD1_2
VDD1_4
VDD1_6
VDD1_8

VDD1_10

VDD2_1
VDD2_2
VDD2_3
VDD2_4
VDD2_5
VDD2_6
VDD2_7
VDD2_8

VDD2_9
VDD2_10
VDD2_11
VDD2_12
VDD2_13
VDD2_14
VDD2_15
VDD2_16
VDD2_17
VDD2_18
VDD2_19
VDD2_20

VDDCA1
VDDCA2
VDDCA3
VDDCA4
VDDCA5

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17

VREFCA

VREFDQ

ODT

ZQ0
ZQ1

NC1
NC2
NC3

P9
N9
N10
N11
M8
M9
M10
M11
F11
F10
F9
F8
E11
E10
E9
D9
T8
T9
T10
T11
R8
R9
R10
R11
C11
C10
C9
C8
B11
B10
B9
B8

A3
A4
A5
A6
A10
U3
U4
U5
U6
U10

A8
A9
D4
D5
D6
G5
H5
H6
H12
J5
J6
K5
K6
K12
L5
P4
P5
P6
U8
U9

F2
G2
H3
L2
M2

A11
C12
E8
E12
G12
H8
H9
H11
J9
J10
K8
K11
L12
N8
N12
R12
U11

H4
J11

J8

B3
B4

C4
K9
R3

M_B_D0
M_B_D1
M_B_D4
M_B_D3
M_B_D2
M_B_D6
M_B_D5
M_B_D7
M_B_D25
M_B_D29
M_B_D27
M_B_D26
M_B_D24
M_B_D28
M_B_D30
M_B_D31
M_B_D19
M_B_D23
M_B_D21
M_B_D16
M_B_D22
M_B_D18
M_B_D17
M_B_D20
M_B_D13
M_B_D15
M_B_D10
M_B_D11
M_B_D12
M_B_D8
M_B_D9
M_B_D14

V1P8U_2P5U V1P8U_2P5U

V1P2U

V1P2U

V1P2U

R17032 243

ZQ1701

R17034 2431%

ZQ1702

M_B_D[7:0] [11] M_B_D[55:48] [11]

M_B_D[31:24] [11]

M_B_DIM0_CLKP1[11,17]
M_B_DIM0_CLKN 1[11,17]

M_B_D[23:16] [11]

M_B_D[15:8] [11]

V_VREF_CA_DIM M

0402

1%

0402
TBL1601

V_VREF_DQ_DIM M1

M_B_DIM0_CKE2[11,17]
M_B_DIM0_CKE3[11,17]

M_B_DIM0_CS0_N[11,17]
M_B_DIM0_CS1_N[11,17]

M_B_DQSP6[11]
M_B_DQSN6[11]

M_B_DQSP5[11]
M_B_DQSN5[11]

M_B_DQSP4[11]
M_B_DQSN4[11]

M_B_DQSP7[11]
M_B_DQSN7[11]

M_B_CAB0
M_B_CAB1
M_B_CAB2
M_B_CAB3
M_B_CAB4
M_B_CAB5
M_B_CAB6
M_B_CAB7
M_B_CAB8
M_B_CAB9

U17002
H9CCNNN BLTBLAR-NUD

R2

CA0

P2

CA1

N2

CA2

N3

CA3

M3

CA4

F3

CA5

E3

CA6

E2

CA7

D2

CA8

C2

CA9

J3

CK

J2

CK#

K3

CKE0

K4

CKE1

L3

CS#0

L4

CS#1

L8

DM0

G8

DM1

P8

DM2

D8

DM3/NC

A1

DNU1

A2

DNU2

A12

DNU3

A13

DNU4

B1

DNU5

B13

DNU6

T1

DNU7

T13

DNU8

U1

DNU9

U2

DNU10

U12

DNU11

U13

DNU12

L10

DQS0

L11

DQS0#

G10

DQS1

G11

DQS1#

P10

DQS2/NC

P11

DQS2#/NC

D10

DQS3/NC

D11

DQS3#/NC

B2

VSS1

B5

VSS2

C5

VSS3

E4

VSS4

E5

VSS5

F5

VSS6

H2

VSS7

J12

VSS8

K2

VSS9

L6

VSS10

M5

VSS11

N4

VSS12

N5

VSS13

R4

VSS14

R5

VSS15

T2

VSS16

T3

VSS17

T4

VSS18

T5

VSS19

C3

VSSCA1

D3

VSSCA2

F4

VSSCA3

G3

VSSCA4

G4

VSSCA5

J4

VSSCA6

M4

VSSCA7

P3

VSSCA8

B6

VSSQ1

B12

VSSQ2

C6

VSSQ3

D12

VSSQ4

E6

VSSQ5

F6

VSSQ6

F12

VSSQ7

G6

VSSQ8

G9

VSSQ9

H10

VSSQ10

K10

VSSQ11

L9

VSSQ12

M6

VSSQ13

M12

VSSQ14

N6

VSSQ15

P12

VSSQ16

R6

VSSQ17

T6

VSSQ18

T12

VSSQ19

TBL1601

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

DQ16/NC
DQ17/NC
DQ18/NC
DQ19/NC
DQ20/NC
DQ21/NC
DQ22/NC
DQ23/NC
DQ24/NC
DQ25/NC
DQ26/NC
DQ27/NC
DQ28/NC
DQ29/NC
DQ30/NC
DQ31/NC

VDD1_1
VDD1_3
VDD1_5
VDD1_7
VDD1_9
VDD1_2
VDD1_4
VDD1_6
VDD1_8

VDD1_10

VDD2_1
VDD2_2
VDD2_3
VDD2_4
VDD2_5
VDD2_6
VDD2_7
VDD2_8

VDD2_9
VDD2_10
VDD2_11
VDD2_12
VDD2_13
VDD2_14
VDD2_15
VDD2_16
VDD2_17
VDD2_18
VDD2_19
VDD2_20

VDDCA1
VDDCA2
VDDCA3
VDDCA4
VDDCA5

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17

VREFCA

VREFDQ

ODT

ZQ0
ZQ1

NC1
NC2
NC3

P9
N9
N10
N11
M8
M9
M10
M11
F11
F10
F9
F8
E11
E10
E9
D9
T8
T9
T10
T11
R8
R9
R10
R11
C11
C10
C9
C8
B11
B10
B9
B8

A3
A4
A5
A6
A10
U3
U4
U5
U6
U10

A8
A9
D4
D5
D6
G5
H5
H6
H12
J5
J6
K5
K6
K12
L5
P4
P5
P6
U8
U9

F2
G2
H3
L2
M2

A11
C12
E8
E12
G12
H8
H9
H11
J9
J10
K8
K11
L12
N8
N12
R12
U11

H4
J11

J8

B3
B4

C4
K9
R3

ZQ1703
ZQ1704

V1P2U

V1P2U

V1P2U

M_B_DIM0_ODT0 [11,17]M_B_DIM0_ODT0 [11,17]

0402

R17033 2431%
R17035 2431%

0402

TBL1601

M_B_D54
M_B_D53
M_B_D49
M_B_D48
M_B_D55
M_B_D52
M_B_D50
M_B_D51
M_B_D45
M_B_D47
M_B_D42
M_B_D46
M_B_D44
M_B_D43
M_B_D41
M_B_D40
M_B_D33
M_B_D32
M_B_D37
M_B_D36
M_B_D34
M_B_D38
M_B_D39
M_B_D35
M_B_D56
M_B_D59
M_B_D60
M_B_D62
M_B_D57
M_B_D58
M_B_D61
M_B_D63

V_VREF_CA_DIM M

M_B_D[47:40] [11]

M_B_D[39:32] [11]

M_B_D[63:56] [11]

V_VREF_DQ_DIM M1

V_VREF_CA_DIM M V_VREF_DQ_DIM M1

C17001
47000p

0201

6.3V

C17002
47000p

0201

6.3V

C17003
47000p

0201

6.3V

C17004
47000p

0201

6.3V

V0P6DX_LPDDR3

M_B_CAA[9:0][11,17]

M_B_CAB[9:0][11,17]

M_B_DIM0_CLKP0[11,17]
M_B_DIM0_CLKN 0[11,17]
M_B_DIM0_CLKP1[11,17]
M_B_DIM0_CLKN 1[11,17]

M_B_CAA0
M_B_CAA1
M_B_CAA2
M_B_CAA3
M_B_CAA4
M_B_CAA5
M_B_CAA6
M_B_CAA7
M_B_CAA8
M_B_CAA9

M_B_CAB0
M_B_CAB1
M_B_CAB2
M_B_CAB3
M_B_CAB4
M_B_CAB5
M_B_CAB6
M_B_CAB7
M_B_CAB8
M_B_CAB9

M_B_DIM0_ODT0[11,17]
M_B_DIM0_CS0_N[11,17]
M_B_DIM0_CS1_N[11,17]
M_B_DIM0_CKE0[11,17]
M_B_DIM0_CKE1[11,17]
M_B_DIM0_CKE2[11,17]
M_B_DIM0_CKE3[11,17]

R17001 68 5% 0201
R17002 68 5% 0201
R17003 68 5% 0201
R17004 68 5% 0201
R17005 68 5% 0201
R17006 68 5% 0201
R17007 68 5% 0201
R17008 68 5% 0201
R17009 68 5% 0201
R17010 68 5% 0201

R17011 68 5% 0201
R17012 68 5% 0201
R17013 68 5% 0201
R17014 68 5% 0201
R17015 68 5% 0201
R17016 68 5% 0201
R17017 68 5% 0201
R17018 68 5% 0201
R17019 68 5% 0201
R17020 68 5% 0201

R17021 80.6 0201
R17022 80.6 0201
R17023 80.6 0201
R17024 80.6 0201
R17025 80.6 0201
R17026 80.6 0201
R17027 80.6 0201

R17028 37.4 0201
R17029 37.4 0201
R17030 37.4 0201
R17031 37.4 0201

DNP For 4GB System
Memory: R17034, R17035

A A

17. LPDDR3(2)_M EMORY DOW N

17. LPDDR3(2)_M EMORY DOW N

17. LPDDR3(2)_M EMORY DOW N

Title:

Title:

Title:

Surface

Surface

1

Surface

1.0.0.1

1.0.0.1

17 79Thursday, April 26, 2018

17 79Thursday, April 26, 2018

17 79Thursday, April 26, 2018

1.0.0.1

Engineer:

Engineer:

Engineer:

A

A

A

Microsoft Conf idential

Microsoft Conf idential

Microsoft Conf idential

Size Project Name Rev

Size Project Name Rev

Size Project Name Rev

C

C

5

4

3

2

U SPECIFIC

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

5

Vinafix.com

D D

XDP_BPM0[10]
XDP_BPM1[10]

XDP_TP18001SMD RND 22.8mil
XDP_TP18002SMD RND 22.8mil

4

XDP_PRESENT_N[18]

MTP18001 SMD RND 22.8mil

3

V3P3_DSW

R18021

100K

0201
DEBUG_OSG

DEBUG_OSG

U18007

1

NC

2
3 4

VCC

A
GND

74LVC1G06GM

NC

Y

6
5

C18002

DEBUG_OSG

0.010u

0201

R18026

100K

0201
DEBUG_OSG

2

XDP_PRESENT_LOGIC [61]

1

C C

V1P00A

PRIMARY XDP connector

C18003

0.1u6.3V

0201

1.5K
R18025

0201

P18001
TBD

36

GNDPAD

XDP_PRDY_N[24]

CFG18[15]
CFG19[15]
CFG15[15]
CFG14[15]
CFG13[15]
CFG12[15]
CFG11[15]
CFG10[15]
CFG9[15]
CFG8[15]

For the signals only go to XDP, the 0R should be close to XDP connector.
For the signals to both XDP and target circuit, the option resistor locaction should follow the target signal routing.

34

XDP_PRDYn

32

XDP_TCK0

30

XDP_TMS

28

XDP_TRSTn

26

HOOK[6]

24

XDP_PRS_PCH

22

VCCOBS_AB

20

OBS_CLK_2N

18

OBS_CLK_2P

16

OBSDATA_15

14

OBSDATA_14

12

OBSDATA_13

10

OBSDATA_12

8

OBSDATA_11

6

OBSDATA_10

4

OBSDATA_9

2

OBSDATA_8

XDP_TDO

XDP_PREQN

XDP_TCK1

XDP_TDI

HOOK[0]
HOOK[3]

XDP_PRS_CPU

OBS_CLK_1N

OBS_CLK_1P

OBSDATA_7
OBSDATA_6
OBSDATA_5
OBSDATA_4
OBSDATA_3
OBSDATA_2
OBSDATA_1
OBSDATA_0

35
33
31
29
27
25
23
21
19

GND

17
15
13
11
9
7
5
3
1

CMC Merged Adapter Gen1

B B

PROC_TCK[10]
PROC_TMS[10]

PROC_TRST_N[10]

ITP_PMODE[15]

XDP_PRESENT_N[18]

XDP_SPI0_IO2[21]

A A

R18018 1K 0201

V1P00A

DEBUG_OSG

C18004

47uDEBUG_OSG

V1P00A

DNP

0201

PM_RSMRST_PWRGD_XDP

R18019 1.5K

CFG17 [15]
CFG7 [15]
CFG6 [15]
CFG5 [15]
CFG4 [15]

CFG2 [15]
CFG1 [15]
CFG0 [15]

49.9

R18005

0201

CFG16 [15]

CFG3 [15]

PROC_TDO [10]

XDP_PREQ_N [24]

PCH_JTAG_TCK [10]

PROC_TDI [10]

1.5K

R18024

0201

V3P3_DSW

MTP18002 SMD RND 22.8mil

R18015
1K

0201

SAM_PCH_RSMRST_N [22,29,56]

SPI0_MOSI_XDP [21]

C18001

0.1u6.3V

0201

18. XDP

18. XDP

Title:

Title:

Microsoft Confidential

Microsoft Confidential

Microsoft Confidential

Size Project Name Rev

Size Project Name Rev

Size Project Name Rev

B

B

B

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

A

A

A

Title:

Engineer:

Engineer:

Engineer:

18. XDP

Surface

Surface

Surface

1

1.0.0.1

1.0.0.1

1.0.0.1

18 79Thursday, April 26, 2018

18 79Thursday, April 26, 2018

18 79Thursday, April 26, 2018

5

Vinafix.com

4

3

2

1

D D

LPDDR3 Vref

M3: CPU driven VREF path is stuffed by default.
M1: VREF_DQ driven by a Voltage Divider Network during Processor power-off

V1P2U

R19001

8.2K

0402

DIMM0_VREF_DQ[11] DIMM_VREF_CA [11]

C C

R19003 10

C19001

0.022u 16V

0201

24.9

0402

0201

R19005

8.2K

0201

V_VREF_DQ_DIMM0

V_VREF_CA_DIMM

V1P2U

R19006

8.2K

0201R19007

R19002

8.2K

0201

0201

R19004 5.1

C19002

0.022u 16V

0201

DIMM_VREF_CA_CDIMM0_VREF_DQ_C

R19008

24.9

0402

V1P2U

R19010

8.2K

0201

0402

DIMM1_VREF_DQ[11]

B B

N1902

R19011 10

C19003

0.022u 16V

0201

R19012

8.2K

0201

R19013

24.9

0402

V_VREF_DQ_DIMM1

Intel 0203
M3+M1: Default Recommendation

A A

19. LPDDR3(3)_CA/DQ Voltage

19. LPDDR3(3)_CA/DQ Voltage

19. LPDDR3(3)_CA/DQ Voltage

Surface

Surface

Surface

19 79Thursday, April 26, 2018

19 79Thursday, April 26, 2018

1

19 79Thursday, April 26, 2018

1.0.0.1

1.0.0.1

1.0.0.1

Title:

Title:

Microsoft Confidential

Microsoft Confidential

Microsoft Confidential

Size Project Name Rev

Size Project Name Rev

Size Project Name Rev

B

B

B

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

A

A

A

Title:

Engineer:

Engineer:

Engineer:

5

[20,27]

Vinafix.com

4

3

2

1

1P8V_SSD

0201

R20032

10K

D D

SSD_PCIECLK_REQ_N[43]

PCIECLK_SSD_DN[43]
PCIECLK_SSD_DP[43]

C C

SSD2_PCIECLK_REQ_N[44]

PCIECLK_SSD2_DN[44]

PCIECLK_SSD2_DP[44]

PCIE_WIFI_RCLK_DN[50]

PCIE_WIFI_RCLK_DP[50]

PCIE_WIFI_CLKREQ_N[50]

B B

A A

AZ_SYNC_1[40]
AZ_BITCLK_1[40]
AZ_SDATA_OUT_1[40]
AZ_SDATA_IN0[40]

FLASH_PROTECT_N[49]
CAM_F_XO_EN[25,54]

AZ_SDATA_IN0

HDA_RST_N_R

HDA_SDO_R

Need to place as close to
SOC pins as possible

C20011

2p

25V
0201

5

DNP

1P8V_SSD2

10K

0201

DNP

R20033

1

C20012

2p

25V
0201

2

Q20001A
NX3008NBKS

G

DNP

0201

S

SSD

DMIC_CLK[40,54]
DMIC_DATA[40,54]

MTP20001SMD RND 22.8mil

MTP20002SMD RND 22.8mil

MTP20003SMD RND 22.8mil

D

5

Q20001B
NX3008NBKS

G

DNP

0201

C20013

2p

25V
0201

S

R20030 0

SSD

4

R20031 0

6

3

D

3P3V_SSD

R20002

CLKREQ1_N

3P3V_SSD

R20021

CLKREQ4_N

0201
0201

0201

R20014 33
R20011 33
R20012 33

10K

10K

0201

0201

U10001J

D42

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

AR10

GPP_B5/SRCCLKREQ0#

B42

CLKOUT_PCIE_N1

A42

CLKOUT_PCIE_P1

AT7

GPP_B6/SRCCLKREQ1#

D41

CLKOUT_PCIE_N2

C41

CLKOUT_PCIE_P2

AT8

GPP_B7/SRCCLKREQ2#

D40

CLKOUT_PCIE_N3

C40

CLKOUT_PCIE_P3

AT10

GPP_B8/SRCCLKREQ3#

B40

CLKOUT_PCIE_N4

A40

CLKOUT_PCIE_P4

AU8

GPP_B9/SRCCLKREQ4#

E40

CLKOUT_PCIE_N5

E38

CLKOUT_PCIE_P5

AU7

GPP_B10/SRCCLKREQ5#

KBL-R U42

<$LOCATION>
<MATERIAL>
10 OF 20
REV = 1

HDA_SYNC_R
HDA_BCLK_R

INT. PD

HDA_RST_N_R

SAM_UEFI_TOP_SWAP[27]

4

HDA_SDO_R

was HDA_SDI0_R

R20019
100K

0201

KBL_R_U42

CLOCK SIGNALS

BA22
AY22
BB22
BA21
AY21

AW22

AY20

AW20

AK7
AK6
AK9

AK10

AW5

U10001G

AUDIO

HDA_SYNC/I2S0_SFRM
HDA_BLK/I2S0_SCLK
HDA_SDO/I2S0_TXD
HDA_SDI0/I2S0_RXD
HDA_SDI1/I2S1_RXD
HDA_RST#/I2S1_SCLK

J5

GPP_D23/I2S_MCLK
I2S1_SFRM
I2S1_TXD

GPP_F1/I2S2_SFRM
GPP_F0/I2S2_SCLK
GPP_F2/I2S2_TXD
GPP_F3/I2S2_RXD

H5

GPP_D19/DMIC_CLK0

D7

GPP_D20/DMIC_DATA0

D8

GPP_D17/DMIC_CLK1

C8

GPP_D18/DMIC_DATA1

GPP_B14/SPKR

KBL-R U42

<$LOCATION>
<MATERIAL>
7 OF 20
REV = 1

CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

GPD8/SUSCLK

NC_2
NC_1

XCLK_BIASREF

RTCX1
RTCX2

SRTCRST#

RTCRST#

3

Do not place XDP_TP20001 and XDP_TP20002 under SOC heat sync

F43
E43

BA17

E37
E35

E42

AM18
AM20

AN18
AM16

HDA_SDO:

1.Flash descriptor security:
Sampled Low: in effect.
Sampled High: override

2.HDA_SDOwhich sample high on
the rising edge of PWROK
Will also disable Intel ME.

KBL_R_U42

CLK_XDP_DN
CLK_XDP_DP

XCLK_BIASREF

RTC_X1
RTC_X2

SRTC_RST_N [20]
SKL_RTCRST_N [20,27]

SDIO/SDXC

GPP_A17/SD_PWR_EN#/ISH_GP7

U SPECIFIC

XDP_TP20001
XDP_TP20002

R20007 0

C20003
22p 25V 5%

0201

GPP_G0/SD_CMD
GPP_G1/SD_DATA0
GPP_G2/SD_DATA1
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3

GPP_G5/SD_CD#
GPP_G6/SD_CLK

GPP_G7/SD_WP

GPP_A16/SD_1P8_SEL

SD_RCOMP

GPP_F23

2

SMD RND 22.8mil
SMD RND 22.8mil

R20006 10M

0201

CTAL_1

0201

No SD support

AB11
AB13
AB12
W12
W11
W10
W8
W7

BA9
BB9

SD_RCOMP

AB7

AF13

Size Project Name Rev

Size Project Name Rev

Size Project Name Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Microsoft Confidential

Microsoft Confidential

Microsoft Confidential

21

Y20002

32.7 KHz

3.2X1.5X0.9MM

SDRAM_SOC_ID0 [23]
SDRAM_SOC_ID1 [23]
SDRAM_SOC_ID2 [23]
SDRAM_SOC_ID3 [23]
SSD_SOC_ID0 [23]
SSD_SOC_ID1 [23]
CPU_SOC_ID0 [23]
CPU_SOC_ID1 [23]

B

B

B

A

A

A

VCCCLK5_R

R20005 2.7K1%

1

0402

C20005

6.3V

1u

0402

C20006

6.3V

1u

0402

Surface

Surface

Surface

20 79Friday, April 27, 2018

20 79Friday, April 27, 2018

20 79Friday, April 27, 2018

SRTC_RST_N [20]

SKL_RTCRST_N

R20017
200

0201

PDG says to use 2.71K 0.5% resistor.
the power rail connector
to the rail of VCCCLK5. Confirmed with Intel OK
to use 2.71K 1% resistor.

C20004
22p 25V 5%

0201

VCC_RTC

R20009 20K

0201

R20015 20K

0201

PCH_PMI_SLOW [25]

PCH_AUD_1V8_EN [25,62]

20. PCH(1)_SD,HDA,RTC, CLK

20. PCH(1)_SD,HDA,RTC, CLK

Title:

Title:

Title:

Engineer:

Engineer:

Engineer:

20. PCH(1)_SD,HDA,RTC, CLK

1.0.0.1

1.0.0.1

1.0.0.1

5

Vinafix.com

Connected to device.
Default : Clock free run. (PD 10K).

D D

XDP_SPI0_IO2[18]

SPI0_MOSI_XDP[18]

Reserver 10K PU for power saving purpose.

4

3

2

1

R21007

1K

Close to PCH

SPI_CLK[37]
SPI_SO[37]
SPI_SI[37]
SPI_WP_IO2[37]

SPI_HOLD_IO3_N[37]

SPI_CS0_N[37]

C C

TS_SPI_CLK[49]

TS_SPI_MISO[49]

TS_SPI_MOSI[49]

TS_SPI_CS_N[49]

B B

R21011 15 0201
R21012 15 0201
R21013 15 0201
R21009 15 0201
R21010 15 0201
R21023 15 0201

R21014 15
R21015 15
R21016 15

R21019 15

TPM_SERIRQ[38]

SPI_CLK_R
SPI_SO_R
SPI_SI_R
SPI_WP_IO2_R
SPI_HOLD_IO3_R_N

0201
0201
0201

0201

3VSUS_ORG

R21029
10K

1%

0201

Serial Interrupt Request

0201

TS_SPI_CLK_R
TS_SPI_MISO_R
TS_SPI_MOSI_R

TS_SPI_CS_N_R

R21008
1K

0201

AV2

AW3

AV3

AW2

AU4
AU3
AU2
AU1

M2
M3

J4
V1
V2

M1

G3
G2
G1

AW13

AY11

U10001E

SPI - FLASH

SPI0_CLK
SPI0_MISO
SPI0_MOSI
SPI0_IO2
SPI0_IO3
SPI0_CS0#
SPI0_CS1#
SPI0_CS2#

SPI_TOUCH

GPP_D1/SPI1_CLK
GPP_D2/SPI1_MISO
GPP_D3/SPI1_MOSI
GPP_D21/SPI1_IO2
GPP_D22/SPI1_IO3
GPP_D0/SPI1_CS#

C LINK

CL_CLK
CL_DATA
CL_RST#

GPP_A0/RCIN#

GPP_A6/SERIRQ

KBL-R U42

<$LOCATION>
<MATERIAL>
5 OF 20
REV = 1

KBL_R_U42

LPC

SMBUS, SMLINK

1

GPP_B23/SML1ALERT#/PCHHOT#

GPP_A5/LFRAME#/ESPI_CS#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3

GPP_A10/CLKOUT_LPC1

GPP_A8/CLKRUN#

R7
R8

INT. PD

R10

R9
W2

INT. PD

W1

GPP_C5 - LPC boot mode selection - needs to be 0

W3
V3

INT. PD

AM7

AY13
BA13
BB13
AY12
BA12
BA11

AW9
AY9
AW11

0201

was SMB0ALERT#

0201

R21024 49.9

R21027 49.9

0201

0201

R21025 49.9

R21026 49.9

TPM_LPC0 [38]
TPM_LPC1 [38]
TPM_LPC2 [38]
TPM_LPC3 [38]
TPM_LFRAME [38]

CK_24M_EC_R

R21020 22

3VSUS_ORG

R21021

8.2K

0201

TPM_CLKRUN [38]

0201

R21004
10K

1%

0201

GTP21013

R21031
100K

1%
0201

TPM_DEEPSLP_N [38]

TPM_CLK [38]

C21002

50V

10p

0201
DNP

SMD RND 22.8mil

GPP_C2/SMBALERT#

LAD1_SKL_TERM

0 Disable ME crypto TLS

Default

1

Enable ME crypto TLS

Needs to be left open or low for booting

A A

LAD0_SKL_TERM

25V

25V

C21006 56p

C21003 56p

0201

0201

Need into improve LPC signals -

P had in their latest design

0201

U SPECIFIC

5

4

3

LAD2_SKL_TERM

C21004 56p

25V

0201

LAD3_SKL_TERM

25V

C21005 56p

21. PCH(2)_CLK,SMB,LPC, SPI

21. PCH(2)_CLK,SMB,LPC, SPI

Title:

Title:

Title:

Microsoft Confidential

Microsoft Confidential

Microsoft Confidential

Size Project Name Rev

Size Project Name Rev

Size Project Name Rev

B

B

B

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

A

A

A

Engineer:

Engineer:

Engineer:

21. PCH(2)_CLK,SMB,LPC, SPI

Surface

Surface

Surface

21 79Friday, April 27, 2018

21 79Friday, April 27, 2018

1

21 79Friday, April 27, 2018

1.0.0.1

1.0.0.1

1.0.0.1

5

Vinafix.com

D D

3VSUS_ORG

C22001 0.1u

MTTP22014

SMD RND 22.8mil

PLT_RST_BUF_N[27,34,38,43,44,56]

V1P00A

SKL_VCCST_PWRGD[34,59]

C C

PCH_DPWROK

SAM_PCH_RSMRST_N[18,29,56]

SKL_SYS_PWROK[34,59]

SN74AUP1G08DRYR

1
2
3 4

V3P3_DSW

6.3V

0201

R22001

49.9K

0201

R22005 60.4

0402

U22002

A

VCC

B

GND

NC

Y

R22024
10K

R22013 100

0201

U22001
SN74AUP1G08DRYR

6

VCC

5

NC

Y

MTTP22010

SMD RND 22.8mil

R22029 1K

3P3VA

6
5

R22009 49.9

0201

6.3V

DNP

0201

0201 DNP

A
B

GND

0201

0201

C220120.1u

1
2
34

R220200DNP

0201

4

C22002

100p

0201

3VSUS_ORG

MTTP22004

C22003

470p

0201

R22006
10K

0201

SMD RND 22.8mil

SMD RND 22.8mil

MTTP22011

PCH_SYS_RST_N

PM_RSMRST_R

PROCPWRGD

VCCST_PWRG D_R

SYS_PWROK_R

V3P3_VCCDSW

R22011 20K

R22025

49.9K

0201

WAKE_N

0201

V3P3_DSW

R22043
10K

0201
DNP

AN10

AY17

BA20
BB20

AR13
AP11

BB15

AM15

AW17

AT15

3

U10001K

SYSTEM POWER MANAGEMENT

GPP_B13/PLTRST#

B5

SYS_RESET#
RSMRST#

A68

PROCPWRGD

B65

VCCST_PWRGD

B6

SYS_PWROK
PCH_PWROK
DSW_PWROK

GPP_A13/SUSWARN#/SUSPWRDNACK
GPP_A15/SUSACK#

WAKE#
GPD2/LAN_WAKE#
GPD11/LANPHYPC
GPD7/RSVD

KBL-R U42

<$LOCATION>
<MATERIAL>
11 OF 20
REV = 1

KBL_R_U42

SMD RND 22.8mil

GPP_B12/SLP_S0#

GPD9/SLP_WLAN#

GPD3/PWRBTN#

GPD1/ACPRESENT

GPP_B11/EXT_PWR_GATE#

GPP_B2/VRALERT#

MTTP22003

GPD4/SLP_S3#
GPD5/SLP_S4#

GPD10/SLP_S5#

SLP_SUS#

SLP_LAN#

GPD6/SLP_A#

GPD0/BATLOW#

GPP_A11/PME#

INTRUDER#

C22007
180p

25V

0201

AT11
AP15
BA16
AY16

AN15
AW15
BB17
AN16

BA15
AY15
AU13

AU11
AP16

AM10
AM11

2

AC_PRESENT_R
BATLOW_R_N

PME_N
INTRUDER_N

VRALERT_R_N

R22033

0 0201

R22035

22 0201

SMD RND 22.8mil

MTTP22008

V3P3_DSW

C22004

0.01u

10V

0201

R22034

33 0201

R22036

33 0201

R22008 1M

R22012
10K

0201R22014 100K

for VR hot indicator (may not be used)

SKL_SLP_S0_N [27,31,34,38,59,61]
SKL_SLP_S3_N [34,59,61]
SKL_SLP_S4_N [27,34,45,59,61]

SKL_SLP_SUS_N [27,34,58,59]

PCH_PWRBTN_N [34,59]

0201

VCC_RTC

C22005
100p

25V

0201

1

C22006
150p

25V

0201

3VSUS_ORG

0201

R22027
100K

0201

R22004

R22010
10K

0201

V3P3_VCCDSW

10K

PM_PCH_PWROK[22]

V3P3_DSW

R22026 10K

0201 DNP

PCH_DPWROK[27,34,56,59]

V3P3_VCCDSW

B B

R22044 10K

0201

If SUSWARN #/SUS_ACK # handshake

SUSWARN_N

A A

is not used, these signals are tied on the board

R22018 22

0201

V3P3_VCCDSW

R22019
10K

0201

R22022

R22021

56p

25V

SUSACK_N

DNP

100K0201

V3P3_DSW

R22031 100K

PMIC_SAM_ALL_SYS_PWRGD[29,34,59]

0201

R22038

SKL_PCH_PWROK[34,59]

R22040

VRM_PWRGD[66]

R22042

1000201

1000201

C22009
2200p 25V

0201

D22002

1000201

100 0201

C22010
2200p 25V

0201

C22008
2200p 25V

0201

AK

RB520CS3002L

R22041

D22003

AK

RB520CS3002L

C22011

6.3V

0.1u

0201
DNP

V3P3_DSW

R22037
10K

0201

PM_PCH_PWROK [22]

VRM_PWR_EN [29,66]

22. PCH(3)_SYS PWR CONTR

22. PCH(3)_SYS PWR CONTR

Title:

Title:

Title:

Microsoft Confidential

Microsoft Confidential

Microsoft Confidential

Size Project Name Rev

Size Project Name Rev

Size Project Name Rev

A3

A3

U SPECIFIC

5

4

3

2

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

A

A

A

Engineer:

Engineer:

Engineer:

22. PCH(3)_SYS PWR CONTR

Surface

Surface

Surface

22 79Tuesday, May 01, 2018

22 79Tuesday, May 01, 2018

1

22 79Tuesday, May 01, 2018

1.0.0.1

1.0.0.1

1.0.0.1

5

Vinafix.com

4

3

2

1

TBL2301B

LOAD FOR DEBUG, ELSE NO-STUFFR23016, R28013

R23023, R28024

TBL2301A

D D

R23015, R28014 NEW BOARDID SYSTEM, ELSE NO-STUFF

R23022, R28025 OLD BOARDID SYSTEM, ELSE NO-STUFF

LOAD FOR RETAIL, ELSE NO-STUFF

TBL_SSD_2302

TBL2304

C C

TBL1601

TBL2301 PCBA vendor and revision

R23010, R23020, R23024

R23005, R23013, R23017, R28051, R28052, R28053

R23005, R23020, R23024, R28051

R23010, R23013, R23017, R28052, R28053

R23010, R23013, R23024, R28052

R23005, R23020, R23017, R28051, R28053

R23005, R23013, R23024, R28051, R28052

R23010, R23020, R23017, R28053

R23010, R23020, R23017, R28053

R23005, R23013, R23024, R28051, R28052

R23005, R23020, R23017, R28051, R28053

R23010, R23013, R23024, R28052

R23010, R23013, R23017, R28052, R28053

R23005, R23020, R23024, R28051

R23005, R23013, R23017, R28051, R28052, R28053

Revision EV2P5

NO-STUFF FOR REVISION

Revision EV2P51

NO-STUFF FOR REVISION

Revision DV

NO-STUFF FOR REVISION

Revision DV1.01

NO-STUFF FOR REVISION

Revision DV1.1, DV1.2, PV

NO-STUFF FOR REVISION

Lacey EV1

NO-STUFF FOR REVISION

Reserved

NO-STUFF FOR REVISION

Reserved

NO-STUFF FOR REVISIONR23010, R23020, R23024

CPU_SOC_ID1[20]
CPU_SOC_ID2[23]

SDRAM_SOC_ID0[20]
SDRAM_SOC_ID1[20]
SDRAM_SOC_ID2[20]
SDRAM_SOC_ID3[20]

See TBL1601

TBL1001

R23041
10K

0201

TBL1001

R23043
10K

0201

TBL1601

R23051
10K

0201

TBL1601

R23050
10K

0201

TBL1001

R23045
10K

0201

V3P3_DSW

TBL1601

R23053
10K

0201

TBL1601

R23052
10K

0201

SSD_SOC_ID0[20]CPU_SOC_ID0[20]
SSD_SOC_ID1[20]

TBL1601

R23055
10K

0201

TBL1601

R23054
10K

0201

SSD

R23031
10K

0201

TBL1601

R23057
10K

0201

TBL1601

R23056
10K

0201

SSD

R23033
10K

0201

V3P3_DSWV1P8AV3P3_DSW

TBL2304

10K

0201

TBL2304

R23009
10K

0201

TBL1001

R23042
10K

0201

V1P8A

TBL2301

R23005
10K

0201

TBL2301A

R23015
10K

0201

TBL2301A

R23022
10K

0201

TBL2301

R23010
10K

0201

TBL1001

R23040

TBL2304

R23003
10K

0201

TBL2304

R23008
10K

0201

TBL2301B

R23016
10K

0201

TBL2301B

R23023
10K

0201

10K

0201

See TBL1001

C23001

10u

6.3V
0402 R23004

MISC_SOC_ID bits are "RESERVED" in PM

B B

U10001I

CSI-2

A36

CSI2_DN0

B36

CSI2_DP0

C38

CSI2_DN1

D38

CSI2_DP1

C36

CSI2_DN2

D36

CSI2_DP2

A38

CSI2_DN3

B38

CSI2_DP3

CSI2_FCAM4_DN[54]
CSI2_FCAM4_DP[54]

CSI2_IRCAM8_DN[54]
CSI2_IRCAM8_DP[54]

A A

C31
D31
C33
D33

A31
B31
A33
B33

A29

B29
C28
D28

A27

B27
C27
D27

KBL-R U42

<$LOCATION>
<MATERIAL>
9 OF 20
REV = 1

CSI2_DN4
CSI2_DP4
CSI2_DN5
CSI2_DP5
CSI2_DN6
CSI2_DP6
CSI2_DN7
CSI2_DP7

CSI2_DN8
CSI2_DP8
CSI2_DN9
CSI2_DP9
CSI2_DN10
CSI2_DP10
CSI2_DN11
CSI2_DP11

KBL_R_U42

CSI2_CLKN0
CSI2_CLKP0
CSI2_CLKN1
CSI2_CLKP1
CSI2_CLKN2
CSI2_CLKP2
CSI2_CLKN3
CSI2_CLKP3

CSI2_COMP

GPP_D4/FLASHTRIG

EMMC

GPP_F13/EMMC_DATA0
GPP_F14/EMMC_DATA1
GPP_F15/EMMC_DATA2
GPP_F16/EMMC_DATA3
GPP_F17/EMMC_DATA4
GPP_F18/EMMC_DATA5
GPP_F19/EMMC_DATA6
GPP_F20/EMMC_DATA7

GPP_F21/EMMC_RCLK

GPP_F22/EMMC_CLK

GPP_F12/EMMC_CMD

EMMC_RCOMP

C37
D37
C32
D32
C29
D29
B26
A26

E13
B7

AP2
AP1
AP3
AN3
AN1
AN2
AM4
AM1

AM2
AM3
AP4

AT1

CSI2_CLK1_FCAM_DN [54]
CSI2_CLK1_FCAM_DP [54]

CSI2_CLK2_IRCAM_DN [54]
CSI2_CLK2_IRCAM_DP [54]

R23011

CSI2_COMP

MISC_SOC_ID0
PWRMON_ID0
GP_SOC_ID0
GP_SOC_ID1
PCBA_SOC_ID0
PCBA_SOC_ID1 PCBA_SOC_ID1
PCBA_SOC_ID2 PCBA_SOC_ID2
DEBUG_RETAIL_SOC_ID DEBUG_RETAIL_SOC_ID

NEW_SOC_ID NEW_SOC_ID

EMMC_RCOMP_R

100 0201

CPU_SOC_ID2 [23]

R23018
200

0201
1%

PWRMON_ID0 bit is noted in "DEBUG_OSG" in PM

MISC_SOC_ID0
PWRMON_ID0
GP_SOC_ID0
GP_SOC_ID1
PCBA_SOC_ID0

TBL2303

R23001
10K

0201

TBL2301

R23013
10K

0201

TBL2301

R23020
10K

0201

TBL2303

R23006
10K

0201

R23002
10K

0201

DNP

R23007
10K

0201

TBL2301

R23017
10K

0201

TBL2301

R23024
10K

0201

U SPECIFIC

5

4

3

2

TBL1001

R23044
10K

0201

POWER MONITORS

V1P8A

Microsoft Confidential

Microsoft Confidential

Microsoft Confidential

Size Project Name Rev

Size Project Name Rev

Size Project Name Rev

A3

A3

A3

Date: Sheet of

Date: Sheet of

Date: Sheet of

DV HAS NO POWER MONITORS

Title:

Title:

Title:

Engineer:

Engineer:

Engineer:

A

A

A

POWER MONITORS, ELSE NO-STUFFR23007

NO POWER MONITORS, ELSE NO-STUFFR23002

SSD

R23030
10K

0201

23. PCH(4)_CCI, HWID

23. PCH(4)_CCI, HWID

23. PCH(4)_CCI, HWID

1

SSD

R23032
10K

0201

Surface

Surface

Surface

23 79Friday, April 27, 2018

23 79Friday, April 27, 2018

23 79Friday, April 27, 2018

1.0.0.1

1.0.0.1

1.0.0.1