Microsoft Surface 1769 Schematics

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Table of Contents
4
3
2
1
Page
D D
01 Table of Contents 02 CHANGE HISTORY 03 BLOCK DIAGRAM 04 CLOCK DISTRIBUTION 05 SYSTEM POWER STATE DIAGRAM 06 POWER DISTRIBUTION 07 INPUT POWER DIAGRAM 08 POWER SYSTEM/CONTROL DIAG 09 I2C MAP 10 CPU(1)_MISC,JTAG,DDI.EDP
C C
11 CPU(2)_LPDDR3 12 CPU(3)_SKL POWER1
Title
Page
Title
31 Debug mux 32 Debug buttons 33 SW Debug Conn 34 EE Debug Connector 35 SM BUS, DIAGNOSTIC CONN 36 Power Monitor 37 SPI ROM UEFI 38 TPM 39 Temp Sensor/System Fan 40 REALTEK ALC3269 CODEC 41 Audio Jack/Spkr 42 Audio Amplifier
Page
Title
61 Discrete Load Switches 62 1.8VSB & Load SW 63 CHARGER 64 5V Load SW 65 3P3V Load SW 66 VCPU Controller 67 VCORE VCCSA 68 VCVGT 69 SL Power 70 BATT CONN, power input 71 Empty
72 LCD backlight/TB 13 CPU(4)_SKL_POWER2 14 CPU(5)_GND 15 CPU(6)_CFG_RESERVED 16 LPDDR3(1)_MEMORY DOWN 17 LPDDR3(2)_MEMORY DOWN 18 XDP 19 LPDDR3(3)_CA/DQ Voltage 20 PCH(1)_SD,HDA,RTC, CLK
B B
21 PCH(2)_CLK,SMB,LPC, SPI 22 PCH(3)_SYS PWR CONTR 23 PCH(4)_CCI, HWID 24 PCH(5)_PCIE,USB 25 PCH(6)_CPU,GPIO,MISC 26 PCH(7)_POWER
43 SSD page 1 44 SSD Page 2 45 USB3.0, TYPE A 46 SL HDMI MUX/3P3V_HPD 47 SurfLink Connector 48 BLADE 49 G5 touch circuitry 50 Wi-Fi_BT 51 Empty 52 Empty 53 mDP 54 Camera/Sensor Conn. 55 eDP connector 56 3P3VA & Reset
73 Empty
74 Empty
75 Empty
76 TP's and Mech
27 SAM_1, K22 28 SAM_2, K22 29 SAM_3, K22 30 INSTANT_ON
A A
57 VCCEDRAM & VCCEOPIO 58 PMIC 1 59 PMIC 2 60 PMIC 3
CAD Note:
Default component footprint is SMD 0201, X5R, 1% resistors.
01. Table of Contents
01. Table of Contents
Property: BUILD-OPT DNP = Do Not Place
5
Title:
Title:
S or DB = Replace after Debug
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3
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Microsoft Confidential
Microsoft Confidential
Microsoft Confidential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
A
A
A
Title:
Engineer:
Engineer:
Engineer:
01. Table of Contents
Surface
Surface
Surface
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Schematics Change History
Schematics Change is maintained in spreadsheet, and would not fit on this page.
D D
C C
B B
A A
CAD Note:
Default component footprint is SMD 0201, X5R, 1% resistors
Property: BUILD-OPT
DNP = Not Installed Part.
5
4
S = Short after design fixed
3
02. CHANGE HISTORY
02. CHANGE HISTORY
Title:
Title:
Title:
Microsoft Confidential
Microsoft Confidential
Microsoft Confidential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
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Date: Sheet of
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Engineer:
Engineer:
Engineer:
02. CHANGE HISTORY
Surface
Surface
Surface
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Front IR
(OV7251)
Debug UART, external connector
D D
Power Monitor Components
(DEBUG)
MIPI CSIx1
(1Gbps)
I2C
Illuminator
MIPI CSIx1
HD Audio
I2C
Front RGB
(720p – OV9734)
Codec
SSD2 BGA chip
Architectural Diagram I-Core
Analog audio combo jack (3.5mm)
Audio
R
L
AMP
Right
ALC1304
Left
Rev 2.5
128GB, 256GB
512GB, 1TB
UART2
CSI2x2
Memory/
SSD BGA chip
128GB, 256GB
512GB, 1TB
2/4 x PCIe
2/4 x PCIe
ALS
I2C
I2C1
I2C3
PCIe 11/12
PCIe 7/8
LPDDR3 x32
Storage
C C
LPDDR3 x32
LPDDR3 x32
LPDDR3 x32
16,8,4 GB (4x)
16MB
128-bit (32b x 4) – 2 Chl -64 bit each
Quad SPI
SPI ROM
Backlight Controller
LCD
13.5"
TrackPad
KeyBoard
B B
UART
INT
TCON
NTRIG G5
eDP 1.4a
SPI
I2C
INT
UART
SC
Freescale
DDR0x64, DD1x64
SPI0
GPIOs
I2C5
eDP
SPI1
I2C0
UART1
SKL-U
15W
2+2/2+3E
O
I P G
K22
SL UART
MUX
PWM/Tach
Hall Effect
Fan/Fan
Connection
Temp
Power/PMIC
BD9992GW
(sep Block Dia)
I2C
7.4V
Battery
45WH
w/Fuel G
SC Debug
I2C
7.4V
Battery Charger ISL9237
Debug XDP
SC,K22
Greenpak
CSI2x2
XDP
P D X
I2C2
HDA
I2C4
DMIC
DDI1
DDI1_AUX
DDPB_CTRL
USB3p2 USB2p2
DDI2
DDI2_AUX
DDPC_CTRL
USB3p1 USB2p1
PCIe9
USB2p5
LPC
LPC
DDI2_A UX DDPC_CTRL
DDI2_A UX
DDPC_CTRL
1XPCIe
USB2
TPM
Infineon
Nuvaton
NationZ
Surflink
DP1.2
MUX
USB2/USB3.0/DP1.2x4
AUX/DDPC
MUX
Debug
Signals
USB3.0
USB2
Wifi abgn+ac
Marvell 88W8897
BT
IMVP8 PMIC
ISL95857
W/2+3E support
POR CHANGES
2xTPS62134
VCCEDRAM/VCCEOPIO
2 Mic
AUX/DDPC
Debug
MUX
CMC + ESD
CMC + ESD
CMC + ESD
CMC + ESD
3.3V@0.8A OUT
POWER IN/OUT
SurfLink
5V@1.78A OUT
Antennas
mDP
USB3.0 Type-A
LEGEND
External
Connectors
POR CHANGES
Power path updates
Separate Block Diagram
POR CHANGES
Mostly same as P
Changed Feature/Implementation
New Feature/Implementation
A A
5
4
3
SD FLUSH
03. BLOCK DIAGRAM
03. BLOCK DIAGRAM
Title:
Title:
Title:
Microsoft Confidential
Microsoft Confidential
Microsoft Confidential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
B
B
B
Date: Sheet of
Date: Sheet of
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Date: Sheet of
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A
A
Engineer:
Engineer:
Engineer:
03. BLOCK DIAGRAM
Surface
Surface
Surface
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D D
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3
2
1
C C
B B
A A
04. CLOCK DISTRIBUTION
04. CLOCK DISTRIBUTION
Title:
Title:
Title:
Microsoft Confidential
Microsoft Confidential
Microsoft Confidential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
A3
A3
A3
Date: Sheet of
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Engineer:
Engineer:
Engineer:
04. CLOCK DISTRIBUTION
Surface
Surface
Surface
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D D
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C C
B B
A A
05. SIGNAL & RESET MAP
05. SIGNAL & RESET MAP
05. SIGNAL & RESET MAP
Surface
Surface
Surface
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Title:
Title:
Microsoft Conf idential
Microsoft Conf idential
Microsoft Conf idential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
C
C
C
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Engineer:
Engineer:
Engineer:
A
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J47001
SurfLink Connector
PWR_SL1
D D
PWR_SL1_F
VDD_BAT
C C
B B
U56002
TPS62177
3P3VA
Always On
PWR_SL1
3P3VA
Imax = .5A
R56007 100mєÀ
Q63008/Q63009
Back to Back FETS
U56005
NX3P1108
3P3VA_SW_EN
DeepSleep Rail
S4/S5 Rail
Power Monitor Input
S0 Rail
Load switch
Control Signal
DC-DC
Regulator
A A
Linear
Regulator
5
External
Regulator /Load
Switch
U63001 ISL9237
Buck/Boost Charger
R36023
100mєA
R28001
100mєA
R31023
0mє À
VCC_RTC
Imax=100uA
R99999
20mєA
4
PWR_SL1_R
R63001
20mєA
VSYS_R
R63009
10mєA
VDD_BAT
J70001/J70002/J70003
Battery Connector
2S
Battery
7.6V typ
R56031 100mєA
R39016 100mєA
3P3V_PMI_DBG
3P3VA_SAM
3P3V_DEBUG
4
3P3VA_SW Imax = .3A
3P3VA_TEMP
R63042
10mє À
Vsys
R67007
20mє À
R68001
20mє À
R67008
50mє À
R58034
10mє À
R58019
5mєA
R58012
20mє À
R58002
10mє À
R59023
25m㤿
R59003
25mє À
R58023
10mє À
R58032
25mєA
R58004
25mєA
R72001
20mє À
3
VCCGT/GTx
Platform PMIC
V3P3A_PCH
V1P8U_2P5U
L_BKLTEN
3
IMVP8
VCORE
VCCSA
U58001
V3P3_DSW
V6
V5A
V5
V1P8A
V8
V7
V0P85A
V12
V1P00A
V11
V9
V1P2U
V10
V0P6DX_LPDDR3
VCCIO
V4
U72001 RT8555
3P3V_SWPWR
V13
VCORE
VCCGT
VCCSA
V3P3_DSW
R58039
20mєA
V5A
R58024
10mєA
V1P8A
R58016
20mєA
V3P3A_PCH
R58008
50mєA
V0P85A
R59027
10mєA
V1P00A
R59007
10mєA
V1P8U_2P5U
R58026
50mєA
V1P2U
R58037
5mєA
R59032
10mєA
R59035
20mєA
VCCIO
R58009
10mєA
2
R64006
50mєA
2
R26004
10mєA
U65003
TPS22920
3P3V_SSD_EN
U65001
TPS22920
EDP_VDD_EN
R53007
0єÀ
R54005 100mєA
R45003
5mє À
R48022 100mєÀ
R64016
20mє À
R64020
20mєA
U62001
SLG59 M1448V
PCH_AUD_1V8_EN
U62003
NX3 P1108
PCH_TPANEL_PWR_EN
TPS22920
WWAN_ PWREN
U61002
SLG5NT1477
VCCSTG_EN
U61003
SLG5NT1477
SKL_SLP_S4_N +
XDP_PR ESENT _LOGIC
U61001
SLG5NT1477
SOiX_EN
SKL
VCORE
Imax = 20A
VCCGT/GTx
Imax = 20A
VCCSA
Imax = 7A
3VSUS_ORG
R38001 100mєÀ
U43005 TPS62085 1P8V_SSD
U43006 TPS62085 1P2V_SSD
R65002
50mєA
ML_V3P3_PWRU53005
3P3V_SSD
R65010 10mє A
R43017
25mєA
R43016
25mєA
NCP380
mDP_PWR_EN
3P3V_CAM
U45004
5V_USBPWR_A
AP2553
SKL_SLP_S4_N
SLG59M1448V
PCH_TPANEL_ PWR_EN
U64002
SLG59M1448V
PCH_TPANEL_PWR_EN
SLG59M1448V
PCH_AUD_5V_EN
SLG59M1448V
SAM_FAN_PWR_EN
U65004
U48002
U64004
U64006
R64019
10mєA
R26003
10mєA
R62002
20mєA
R40005
20mє À
R62007
20mєA
R65012
40mєA
5V0_OFFBOARD
5V_SWPWR
5V_TS
5V_AUDIO
5V_FAN (i-core only)
1P8VSUS_ORG
1P8V_AUDIO
1P8V_AUDIO_DVDD
1P8V_TS
3P3V_WWAN
V0P85A
V1P00A
1V_MODPHY
R61007 20mє À
VCCSTG
R61003 10 mєÀ
VCCST_CPU
R61006 10 mєÀ
V1P00A_XDP
R18001
0 mєA
V1P8U_2P5U
V1P2U
VCCPLL_OC
R61001
10mєA
V0P6DX_LPDDR3
VCCIO
VCC_EDP_BKLT_OUT
DVi7U7660s16s512x2Retail
DVi7U7660s16s512x2Retail
DVi7U7660s16s512x2Retail
Title:
Title:
Microsoft Confidential
Microsoft Confidential
Microsoft Confidential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Title:
Engineer:
Engineer:
Engineer:
A
A
A
1
3P3V_TPM
1P8V_SSD
1P2V_SSD
3P3V_PANEL
J53001
mDP
Connector
J45001 USB 3.0 A Connector
(keyboard)
06. POWER DISTRIBUTION
06. POWER DISTRIBUTION
06. POWER DISTRIBUTION
Surface
Surface
Surface
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D D
4
3
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1
C C
B B
A A
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07. POW ER SEQUENCE 1
07. POW ER SEQUENCE 1
07. POW ER SEQUENCE 1
Title:
Title:
Microsoft Confidential
Microsoft Confidential
Microsoft Confidential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
D
D
D
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
1
Title:
Engineer:
Engineer:
Engineer:
A
A
A
Surface
Surface
Surface
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C C
B B
A A
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08. POWER SEQUENCE
08. POWER SEQUENCE
08. POWER SEQUENCE
Title:
Title:
Microsoft Confidential
Microsoft Confidential
Microsoft Confidential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
D
D
D
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
1
Title:
Engineer:
Engineer:
Engineer:
A
A
A
Surface
Surface
Surface
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D EB U G : P ow e r M on ito rs
U 36 00 2
PM I1 M A X3 44 07
7 -b it s la v e add re ss e s
Sep te m b e r 2 8 , 201 6
D D
1 0 0 4 5
J 1
0 0 4 5
J
1 0 0 4 5
J
Cam e ra s
EE PRO M G T2 4C 0 8S
0x50 , 0 x 5 1,
0x52, 0 x 5 3
Fro n t R G B O V9 73 4
0x36
IR C am O V0 72 5 1
0x60
1P 8V SU S_ OR G
5 /
S
4 1 0 5 2 R
2k?
I2 C_ S xx_ C AM
S
To E E P ow er D ebu g
Co n ne cto r
S
U 36 00 1
PM I0 M A X3 44 07
0x1E
S
M
0x12
I2C 2
S S
U 36 0 03
PM I2 M AX 34 40 7
0x10
U3 60 04
PM I3 M AX 34 4 0 7
0x18
U 36 00 5 U3 60 07
PM I4 M A X3 44 07
S S S
M
I2 C1
0x1A
Light S e nsor a nd B KLT C o n tro lle r
ALS ISL2 9 033
1 0
C C
B B
0 4 5
J
1
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0 0 2 7
U
0x44
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D isp la y
1
TC O N M LT S15 20 00
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J
0x28
Pow e r M an a g e m e n t
1 0
PM IC B D 999 9 2G W
0 8 5
U
1 0
Ch arge r BQ 24 7 70
0 8 5
U
1
3
Fu el G a uge B Q 40x 5 0
0
0
0
0
0
0
7
7
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J
0x30
0x09
0x0B
S
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I2 C_ Sx x_ B KLT
S
D ispl ay _V DD 18
3P 3V _P AN EL
d
r a o b
f
f O
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S
BA T T_I2C _x xx
S
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2 / 1 1 7
R
4.7 k?
I2 C_ DISP LA Y _ Sxx ( DN P)
3P 3V A_ SW
2 / 1 0 0 9 5
R
3P 3V A_ SW
7 / 6 3 0 7 2
R
1P 8V SU S_ OR G
5 / 4 7 0 5 2
R
To De bu g
Co nn ecto r
To De bu g
Co nn ecto r
2k ?
2.2 k?
I2 C_ RO P_ Sx x
2k?
M
I2C 3
I2C 4
M
K22 P 121M 120SF5
M M
I2 C1
SO C/PC H
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SA M
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I2 C0
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M
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0x1C
PM I_ I2C _S xx
I2 C_ Sxx _ A LS (D NP )
5V A ->
TP _P W R_ EN
I2 C _S xx_ T P
I2 C_ Sx x_ M CU
S
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PM IB A T T IN A 23 1
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1P 8V SU S_ OR G
4 / 3
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b
f
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2 / 1 2 0 6 3
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to I2 C_ RO P_ Sx x
W ifi 88W 88 97
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Tra ck p ad IC S 910 1 B
S
0x20
To De bu g
M ux es
To D eb ug
Co n ne cto r
3 0 0 9 3
U
To E E P ow er D eb ug
Te m p S en so r S TT S7 51
S
S
2.2 k?
To E E P ow er De b ug
Co n ne cto r
1 0 0 8 4
J
Tem p S ensors
Co n ne cto r
0x3B
M
D e b ug C o nn e ctor
EE Po w er D e b ug
Con n ecto r
D e b ug M uxe s
Rem ov e d in R e tail
D EB U G _O SG in Reta il
D N P in N o n-R eta il/R eta il
W ifi/B T
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2
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A A
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DVi7U7660s16s512x2Retail
DVi7U7660s16s512x2Retail
DVi7U7660s16s512x2Retail
Microsoft Confidential
Microsoft Confidential
Microsoft Confidential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
2 0 0 9 3
U
A
A
A
Te m p S en sor S TT S7 5 1
0x4A
09. I2C MAP
09. I2C MAP
Title:
Title:
Title:
Engineer:
Engineer:
Engineer:
09. I2C MAP
1
Surface
Surface
Surface
9 79Thursday, April 26, 2018
9 79Thursday, April 26, 2018
9 79Thursday, April 26, 2018
4 0 0 9 3
U
1.0.0.1
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VCCSTG
R10001 1K
0201
D D
C C
PROCHOT_N[34,60,63,66]
R10004
100
0402
D
SAM_PROCHOT[29]
G
RUM002N02GT2L
0201
R10029 100K
Q10001
S
VCCST_CPU
R10019 1K
0201
XDP_TP10001
TS_IRQ_3V3_N[49]
XDP_TP10002
TRACKPAD_INT_N[27,48]
mDP_PWR_EN[53]
0201
R10011 49.9
R10012 49.9
0201
R10003 499
EE SQ 13.8mil
EE SQ 13.8mil
0201
0201
R10013 49.9
4
VCCST_CPU
SMD RND 22.8mil
0201
R10014 49.9
DNP
R10002
49.9
0201
GTP10006
PM_THERMTRIP_N[10,56]
XDP_BPM0[18] XDP_BPM1[18]
PROC_POPIRCOMP PCH_OPIRCOMP OPCE_RCOMP OPC_RCOMP
R10035 330 0201
TP_CATERR_R_N
H_PROCHOT_R_N
GPP_E3
U10001D
D63
CATERR#
A54
PECI
C65
PROCHOT#
C63
THERMTRIP#
A65
SKTOCC#
C55
BPM#[0]
D55
BPM#[1]
B54
BPM#[2]
C56
BPM#[3]
A6
GPP_E3/CPU_GP0
A7
GPP_E7/CPU_GP1
BA5
GPP_B3/CPU_GP2
AY5
GPP_B4/CPU_GP3
AT16
PROC_POPIRCOMP
AU16
PCH_OPIRCOMP
H66
OPCE_RCOMP
H65
OPC_RCOMP
KBL-R U42
<$LOCATION> <MATERIAL> 4 OF 20 REV = 1
3
CPU MISC
KBL_R_U42
JTAG
PROC_TCK
PROC_TDI PROC_TDO PROC_TMS
PROC_TRST#
PCH_JTAG_TCK
PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS
PCH_TRST#
JTAGX
VCCSTG
R10032 100
B61 D60 A61 C60 B59
B56 D59 A56 C59 C61 A59
0201
2
MTP10001 SMD RND 22.8mil MTP10002 SMD RND 22.8mil MTP10003 SMD RND 22.8mil MTP10004 SMD RND 22.8mil MTP10005 SMD RND 22.8mil
PROC_TCK [10,18] PROC_TDI [10,18]
PROC_TDO [10,18] PROC_TMS [10,18] PROC_TRST_N [10,18]
0201
PLACE TP's on BOTTOM,
1
PLACE TP's on BOTTOM,
R10008 51
0201
0201
R10015 51
R10016 100
0201
R10017 51
VCCSTG
MTP10007 SMD RND 22.8mil MTP10008 SMD RND 22.8mil MTP10009 SMD RND 22.8mil MTP10010 SMD RND 22.8mil MTP10011 SMD RND 22.8mil MTP10012 SMD RND 22.8mil
PCH_JTAG_TCK [18] PROC_TDI [10,18] PROC_TDO [10,18] PROC_TMS [10,18] PROC_TRST_N [10,18] PROC_TCK [10,18]
TBL1002
PM_THERMTRIP_N[10,56]
U10001A
MDP_DDI1_ML0_DN[53] MDP_DDI1_ML0_DP[53] MDP_DDI1_ML1_DN[53] MDP_DDI1_ML1_DP[53] MDP_DDI1_ML2_DN[53] MDP_DDI1_ML2_DP[53] MDP_DDI1_ML3_DN[53] MDP_DDI1_ML3_DP[53]
SL_DDI2_ML0_DN[47] SL_DDI2_ML0_DP[47]
B B
DDPB_CTRL_CLK[53]
VCCIO
R10025
24.9
0201
SAM_PCH_HALL_INT[27]
DDPB_CTRL_DATA[53]
SL_DDI2_ML1_DN[47] SL_DDI2_ML1_DP[47] SL_DDI2_ML2_DN[47] SL_DDI2_ML2_DP[47] SL_DDI2_ML3_DN[47] SL_DDI2_ML3_DP[47]
DDPC_CTRL_CLK[46]
DDPC_CTRL_DATA[46]
EDP_COMP
INT. PD
INT. PD
TBL1001
A A
E55
DDI1_TXN[0]
F55
DDI1_TXP[0]
E58
DDI1_TXN[1]
F58
DDI1_TXP[1]
F53
DDI1_TXN[2]
G53
DDI1_TXP[2]
F56
DDI1_TXN[3]
G56
DDI1_TXP[3]
C50
DDI2_TXN[0]
D50
DDI2_TXP[0]
C52
DDI2_TXN[1]
D52
DDI2_TXP[1]
A50
DDI2_TXN[2]
B50
DDI2_TXP[2]
D51
DDI2_TXN[3]
C51
DDI2_TXP[3]
L13
GPP_E18/DDPB_CTRLCLK
L12
GPP_E19/DDPB_CTRLDATA
N7
GPP_E20/DDPC_CTRLCLK
N8
GPP_E21/DDPC_CTRLDATA
N11
GPP_E22/DDPD_CTRLCLK
N12
GPP_E23/DDPD_CTRLDATA
E52
EDP_RCOMP
KBL-R U42
1 OF 20 REV = 1
KBL_R_U42
DDI
DISPLAY SIDEBANDS
EDP
EDP_TXN[0] EDP_TXP[0] EDP_TXN[1] EDP_TXP[1] EDP_TXN[2] EDP_TXP[2] EDP_TXN[3] EDP_TXP[3]
EDP_AUXN EDP_AUXP
EDP_DISP_UTIL
DDI1_AUXN DDI1_AUXP DDI2_AUXN DDI2_AUXP
RSVD_G46
RSVD_F46
GPP_E13/DDPB_HPD0 GPP_E14/DDPC_HPD1 GPP_E15/DDPD_HPD2 GPP_E16/DDPE_HPD3
GPP_E17/EDP_HPD
EDP_BKLTEN
EDP_BKLTCTL
EDP_VDDEN
C47 C46 D46 C45 A45 B45 A47 B47
E45 F45
B52
G50 F50 E48 F48 G46 F46
L9 L7 L6 N9 L10
R12 R11 U13
EDP_TX0_DN [55] EDP_TX0_DP [55] EDP_TX1_DN [55] EDP_TX1_DP [55] EDP_TX2_DN [55] EDP_TX2_DP [55] EDP_TX3_DN [55] EDP_TX3_DP [55]
EDP_AUX_DN [55] EDP_AUX_DP [55]
eDP x 4
MDP_DDI1_AUX_DN [53] MDP_DDI1_AUX_DP [53] SL_DDI2_AUX_DN [46] SL_DDI2_AUX_DP [46]
SOC_BKLTEN [30]
SOC_BKLT_CTRL_IN [30]
SOC_DISPLAY_VDD_EN [30]
EDP_DISP_UTIL
0201DNP
0201DNP
R10026 100K
R10027 100K
0201
R10028 100K
DNP
R10022 0
0201
0201
R10037 49.9K
V5A
R10033 10K
0201
5
34
Q10002B NX3008NBKS
SOT-363
BL_INST_ON_HNDSHK [29,30]
EDP_HPD [55]
3VSUS_ORG
R10039 49.9K
0201
V5A
2
R10034 10K
0201
61
Q10002A NX3008NBKS
SOT-363
GPP_A 3.3V GPP_B 3.3V GPP_C 3.3V GPP_D 1.8V GPP_E 3.3V GPP_F 1.8V GPP_G 3.3V GDP 3.3V
MDP_SNK1_HPD [53]
SL_SNK0_HPD [47]
SAM_PCH_RSV1 [27]
10. CPU(1)_MISC,JTAG,DDI.EDP
10. CPU(1)_MISC,JTAG,DDI.EDP
Title:
Title:
Title:
Microsoft Confidential
Microsoft Confidential
Microsoft Confidential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
B
B
U SPECIFIC
5
4
3
2
B
Date: Sheet of
Date: Sheet of
Date: Sheet of
A
A
A
Engineer:
Engineer:
Engineer:
10. CPU(1)_MISC,JTAG,DDI.EDP
Surface
Surface
Surface
10 79Friday, April 27, 2018
10 79Friday, April 27, 2018
1
10 79Friday, April 27, 2018
1.0.0.1
1.0.0.1
1.0.0.1
5
Vinafix.com
4
3
2
1
U10001C
U10001B
M_A_D[7:0][16]
D D
C C
M_A_D[15:8][16]
M_A_D[39:32][16]
M_A_D[47:40][16]
M_B_D[7:0][17]
M_B_D[15:8][17]
M_B_D[39:32][17]
M_B_D[47:40][17]
M_A_D0 M_A_D1 M_A_D2 M_A_D3 M_A_D4 M_A_D5 M_A_D6 M_A_D7 M_A_D8 M_A_D9 M_A_D10 M_A_D11 M_A_D12 M_A_D13 M_A_D14 M_A_D15 M_A_D32 M_A_D33 M_A_D34 M_A_D35 M_A_D36 M_A_D37 M_A_D38 M_A_D39 M_A_D40 M_A_D41 M_A_D42 M_A_D43 M_A_D44 M_A_D45 M_A_D46 M_A_D47 M_B_D0 M_B_D1 M_B_D2 M_B_D3 M_B_D4 M_B_D5 M_B_D6 M_B_D7 M_B_D8 M_B_D9 M_B_D10 M_B_D11 M_B_D12 M_B_D13 M_B_D14 M_B_D15 M_B_D32 M_B_D33 M_B_D34 M_B_D35 M_B_D36 M_B_D37 M_B_D38 M_B_D39 M_B_D40 M_B_D41 M_B_D42 M_B_D43 M_B_D44 M_B_D45 M_B_D46 M_B_D47
DDR4(IL)/LP3-DDR4(NIL)
AL71
DDR0_DQ[0]
AL68
DDR0_DQ[1]
AN68
DDR0_DQ[2]
AN69
DDR0_DQ[3]
AL70
DDR0_DQ[4]
AL69
DDR0_DQ[5]
AN70
DDR0_DQ[6]
AN71
DDR0_DQ[7]
AR70
DDR0_DQ[8]
AR68
DDR0_DQ[9]
AU71
DDR0_DQ[10]
AU68
DDR0_DQ[11]
AR71
DDR0_DQ[12]
AR69
DDR0_DQ[13]
AU70
DDR0_DQ[14]
AU69
DDR0_DQ[15]
BB65
DDR0_DQ[16]/DDR0_DQ[32]
AW65
DDR0_DQ[17]/DDR0_DQ[33]
AW63
DDR0_DQ[18]/DDR0_DQ[34]
AY63
DDR0_DQ[19]/DDR0_DQ[35]
BA65
DDR0_DQ[20]/DDR0_DQ[36]
AY65
DDR0_DQ[21]/DDR0_DQ[37]
BA63
DDR0_DQ[22]/DDR0_DQ[38]
BB63
DDR0_DQ[23]/DDR0_DQ[39]
BA61
DDR0_DQ[24]/DDR0_DQ[40]
AW61
DDR0_DQ[25]/DDR0_DQ[41]
BB59
DDR0_DQ[26]/DDR0_DQ[42]
AW59
DDR0_DQ[27]/DDR0_DQ[43]
BB61
DDR0_DQ[28]/DDR0_DQ[44]
AY61
DDR0_DQ[29]/DDR0_DQ[45]
BA59
DDR0_DQ[30]/DDR0_DQ[46]
AY59
DDR0_DQ[31]/DDR0_DQ[47]
AY39
DDR0_DQ[32]/DDR1_DQ[0]
AW39
DDR0_DQ[33]/DDR1_DQ[1]
AY37
DDR0_DQ[34]/DDR1_DQ[2]
AW37
DDR0_DQ[35]/DDR1_DQ[3]
BB39
DDR0_DQ[36]/DDR1_DQ[4]
BA39
DDR0_DQ[37]/DDR1_DQ[5]
BA37
DDR0_DQ[38]/DDR1_DQ[6]
BB37
DDR0_DQ[39]/DDR1_DQ[7]
AY35
DDR0_DQ[40]/DDR1_DQ[8]
AW35
DDR0_DQ[41]/DDR1_DQ[9]
AY33
DDR0_DQ[42]/DDR1_DQ[10]
AW33
DDR0_DQ[43]/DDR1_DQ[11]
BB35
DDR0_DQ[44]/DDR1_DQ[12]
BA35
DDR0_DQ[45]/DDR1_DQ[13]
BA33
DDR0_DQ[46]/DDR1_DQ[14]
BB33
DDR0_DQ[47]/DDR1_DQ[15]
AY31
DDR0_DQ[48]/DDR1_DQ[32]
AW31
DDR0_DQ[49]/DDR1_DQ[33]
AY29
DDR0_DQ[50]/DDR1_DQ[34]
AW29
DDR0_DQ[51]/DDR1_DQ[35]
BB31
DDR0_DQ[52]/DDR1_DQ[36]
BA31
DDR0_DQ[53]/DDR1_DQ[37]
BA29
DDR0_DQ[54]/DDR1_DQ[38]
BB29
DDR0_DQ[55]/DDR1_DQ[39]
AY27
DDR0_DQ[56]/DDR1_DQ[40]
AW27
DDR0_DQ[57]/DDR1_DQ[41]
AY25
DDR0_DQ[58]/DDR1_DQ[42]
AW25
DDR0_DQ[59]/DDR1_DQ[43]
BB27
DDR0_DQ[60]/DDR1_DQ[44]
BA27
DDR0_DQ[61]/DDR1_DQ[45]
BA25
DDR0_DQ[62]/DDR1_DQ[46]
BB25
DDR0_DQ[63]/DDR1_DQ[47]
KBL-R U42
<$LOCATION> <MATERIAL> 2 OF 20 REV = 1
KBL_R_U42
DDR CH - A
LP3/DDR4
DDR0_CKN[0] DDR0_CKP[0] DDR0_CKN[1] DDR0_CKP[1]
LP3/DDR4
DDR0_CKE[0]
DDR0_CKE[1] DDR0_CKE[2]/NC DDR0_CKE[3]/NC
LP3/DDR4
DDR0_CS#[0]
DDR0_CS#[1]
DDR0_ODT[0] NC/DDR0_ODT[1]
LP3/DDR4
DDR0_CAA[0]/DDR0_MA[5] DDR0_CAA[1]/DDR0_MA[9] DDR0_CAA[2]/DDR0_MA[6] DDR0_CAA[3]/DDR0_MA[8] DDR0_CAA[4]/DDR0_MA[7]
DDR0_CAA[5]/DDR0_BG[0] DDR0_CAA[6]/DDR0_MA[12] DDR0_CAA[7]/DDR0_MA[11]
DDR0_CAA[8]/DDR0_ACT# DDR0_CAA[9]/DDR0_BG[1]
DDR0_CAB[0]/DDR0_MA[13] DDR0_CAB[1]/DDR0_MA[15] DDR0_CAB[2]/DDR0_MA[14] DDR0_CAB[3]/DDR0_MA[16]
DDR0_CAB[7]/DDR0_MA[10]
DDR0_DQSN[2]/DDR0_DQSN[4] DDR0_DQSP[2]/DDR0_DQSP[4] DDR0_DQSN[3]/DDR0_DQSN[5] DDR0_DQSP[3]/DDR0_DQSP[5] DDR0_DQSN[4]/DDR1_DQSN[0] DDR0_DQSP[4]/DDR1_DQSP[0] DDR0_DQSN[5]/DDR1_DQSN[1] DDR0_DQSP[5]/DDR1_DQSP[1] DDR0_DQSN[6]/DDR1_DQSN[4] DDR0_DQSP[6]/DDR1_DQSP[4] DDR0_DQSN[7]/DDR1_DQSN[5] DDR0_DQSP[7]/DDR1_DQSP[5]
LP3/DDR4
DDR0_CAB[4]/DDR0_BA[0]
DDR0_CAB[5]/DDR0_MA[2]
DDR0_CAB[6]/DDR0_BA[1]
DDR0_CAB[8]/DDR0_MA[1] DDR0_CAB[9]/DDR0_MA[0]
NC/DDR0_MA[3] NC/DDR0_MA[4]
DDR4(IL)/LP3-DDR4(NIL)
DDR0_DQSN[0] DDR0_DQSP[0] DDR0_DQSN[1] DDR0_DQSP[1]
LP3/DDR4
NC/DDR0_ALERT#
NC/DDR0_PAR
DDR_VREF_CA DDR0_VREF_DQ DDR1_VREF_DQ
DDR_VTT_CNTL
AU53 AT53 AU55 AT55
BA56 BB56 AW56 AY56
AU45 AU43 AT45 AT43
M_A_CAA0
BA51
M_A_CAA1
BB54
M_A_CAA2
BA52
M_A_CAA3
AY52
M_A_CAA4
AW52
M_A_CAA5
AY55
M_A_CAA6
AW54
M_A_CAA7
BA54
M_A_CAA8
BA55
M_A_CAA9
AY54
M_A_CAB0
AU46
M_A_CAB1
AU48
M_A_CAB2
AT46
M_A_CAB3
AU50
M_A_CAB4
AU52
M_A_CAB5
AY51
M_A_CAB6
AT48
M_A_CAB7
AT50
M_A_CAB8
BB50
M_A_CAB9
AY50 BA50 BB52
AM70 AM69 AT69 AT70 BA64 AY64 AY60 BA60 BA38 AY38 AY34 BA34 BA30 AY30 AY26 BA26
AW50 AT52
AY67
DIMM_VREF_C A [19]
AY68
DIMM0_VREF_D Q [19]
BA67
DIMM1_VREF_D Q [19]
AW67
M_A_DIM0_CLKN 0 [16] M_A_DIM0_CLKP0 [16] M_A_DIM0_CLKN 1 [16] M_A_DIM0_CLKP1 [16]
M_A_DIM0_CKE0 [16] M_A_DIM0_CKE1 [16] M_A_DIM0_CKE2 [16] M_A_DIM0_CKE3 [16]
M_A_DIM0_CS0_N [16] M_A_DIM0_CS1_N [16] M_A_DIM0_ODT0 [16]
M_A_CAA[9:0] [16]
M_A_CAB[9:0] [16]
M_A_DQSN0 [16] M_A_DQSP0 [16] M_A_DQSN1 [16] M_A_DQSP1 [16] M_A_DQSN4 [16] M_A_DQSP4 [16] M_A_DQSN5 [16] M_A_DQSP5 [16] M_B_DQSN0 [17]
M_B_DQSN1 [17] M_B_DQSP1 [17] M_B_DQSN4 [17] M_B_DQSP4 [17] M_B_DQSN5 [17] M_B_DQSP5 [17]
DDR_VTT_CTL [34,59]
M_A_D[23:16][16]
M_A_D[31:24][16]
M_A_D[55:48][16]
M_A_D[63:56][16]
M_B_D[23:16][17]
M_B_D[31:24][17]
M_B_D[55:48][17]
M_B_D[63:56][17]
M_A_D16 M_A_D17 M_A_D18 M_A_D19 M_A_D20 M_A_D21 M_A_D22 M_A_D23 M_A_D24 M_A_D25 M_A_D26 M_A_D27 M_A_D28 M_A_D29 M_A_D30 M_A_D31 M_A_D48 M_A_D49 M_A_D50 M_A_D51 M_A_D52 M_A_D53 M_A_D54 M_A_D55 M_A_D56 M_A_D57 M_A_D58 M_A_D59 M_A_D60 M_A_D61 M_A_D62 M_A_D63 M_B_D16 M_B_D17 M_B_D18 M_B_D19 M_B_D20 M_B_D21 M_B_D22 M_B_D23 M_B_D24 M_B_D25 M_B_D26 M_B_D27 M_B_D28 M_B_D29 M_B_D30 M_B_D31 M_B_D48 M_B_D49 M_B_D50 M_B_D51 M_B_D52 M_B_D53 M_B_D54 M_B_D55 M_B_D56 M_B_D57 M_B_D58 M_B_D59 M_B_D60 M_B_D61 M_B_D62 M_B_D63
DDR4(IL)/LP3-DDR4(NIL) LP3/DDR4
AF65
DDR1_DQ[0]/DDR0_DQ[16]
AF64
DDR1_DQ[1]/DDR0_DQ[17]
AK65
DDR1_DQ[2]/DDR0_DQ[18]
AK64
DDR1_DQ[3]/DDR0_DQ[19]
AF66
DDR1_DQ[4]/DDR0_DQ[20]
AF67
DDR1_DQ[5]/DDR0_DQ[21]
AK67
DDR1_DQ[6]/DDR0_DQ[22]
AK66
DDR1_DQ[7]/DDR0_DQ[23]
AF70
DDR1_DQ[8]/DDR0_DQ[24]
AF68
DDR1_DQ[9]/DDR0_DQ[25]
AH71
DDR1_DQ[10]/DDR0_DQ[26]
AH68
DDR1_DQ[11]/DDR0_DQ[27]
AF71
DDR1_DQ[12]/DDR0_DQ[28]
AF69
DDR1_DQ[13]/DDR0_DQ[29]
AH70
DDR1_DQ[14]/DDR0_DQ[30]
AH69
DDR1_DQ[15]/DDR0_DQ[31]
AT66
DDR1_DQ[16]/DDR0_DQ[48]
AU66
DDR1_DQ[17]/DDR0_DQ[49]
AP65
DDR1_DQ[18]/DDR0_DQ[50]
AN65
DDR1_DQ[19]/DDR0_DQ[51]
AN66
DDR1_DQ[20]/DDR0_DQ[52]
AP66
DDR1_DQ[21]/DDR0_DQ[53]
AT65
DDR1_DQ[22]/DDR0_DQ[54]
AU65
DDR1_DQ[23]/DDR0_DQ[55]
AT61
DDR1_DQ[24]/DDR0_DQ[56]
AU61
DDR1_DQ[25]/DDR0_DQ[57]
AP60
DDR1_DQ[26]/DDR0_DQ[58]
AN60
DDR1_DQ[27]/DDR0_DQ[59]
AN61
DDR1_DQ[28]/DDR0_DQ[60]
AP61
DDR1_DQ[29]/DDR0_DQ[61]
AT60
DDR1_DQ[30]/DDR0_DQ[62]
AU60
DDR1_DQ[31]/DDR0_DQ[63]
AU40
DDR1_DQ[32]/DDR1_DQ[16]
AT40
DDR1_DQ[33]/DDR1_DQ[17]
AT37
DDR1_DQ[34]/DDR1_DQ[18]
AU37
DDR1_DQ[35]/DDR1_DQ[19]
AR40
DDR1_DQ[36]/DDR1_DQ[20]
AP40
DDR1_DQ[37]/DDR1_DQ[21]
AP37
DDR1_DQ[38]/DDR1_DQ[22]
AR37
DDR1_DQ[39]/DDR1_DQ[23]
AT33
DDR1_DQ[40]/DDR1_DQ[24]
AU33
DDR1_DQ[41]/DDR1_DQ[25]
AU30
DDR1_DQ[42]/DDR1_DQ[26]
AT30
DDR1_DQ[43]/DDR1_DQ[27]
AR33
DDR1_DQ[44]/DDR1_DQ[28]
AP33
DDR1_DQ[45]/DDR1_DQ[29]
AR30
DDR1_DQ[46]/DDR1_DQ[30]
AP30
DDR1_DQ[47]/DDR1_DQ[31]
AU27
DDR1_DQ[48]
AT27
DDR1_DQ[49]
AT25
DDR1_DQ[50]
AU25
DDR1_DQ[51]
AP27
DDR1_DQ[52]
AN27
DDR1_DQ[53]
AN25
DDR1_DQ[54]
AP25
DDR1_DQ[55]
AT22
DDR1_DQ[56]
AU22
DDR1_DQ[57]
AU21
DDR1_DQ[58]
AT21
DDR1_DQ[59]
AN22
DDR1_DQ[60]
AP22
DDR1_DQ[61]
AP21
DDR1_DQ[62]
AN21
DDR1_DQ[63]
KBL-R U42
<$LOCATION> <MATERIAL> 3 OF 20 REV = 1
KBL_R_U42
DDR CH - B
DDR1_CKN[0] DDR1_CKN[1] DDR1_CKP[0] DDR1_CKP[1]
LP3/DDR4
DDR1_CKE[0]
DDR1_CKE[1] DDR1_CKE[2]/NC DDR1_CKE[3]/NC
LP3/DDR4
DDR1_CS#[0] DDR1_CS#[1]
DDR1_ODT[0] NC/DDR1_ODT[1]
DDR1_CAA[0]/DDR1_MA[5] DDR1_CAA[1]/DDR1_MA[9] DDR1_CAA[2]/DDR1_MA[6] DDR1_CAA[3]/DDR1_MA[8] DDR1_CAA[4]/DDR1_MA[7]
DDR1_CAA[5]/DDR1_BG[0] DDR1_CAA[6]/DDR1_MA[12] DDR1_CAA[7]/DDR1_MA[11]
DDR1_CAA[8]/DDR1_ACT#
DDR1_CAA[9]/DDR1_BG[1]
DDR1_CAB[0]/DDR1_MA[13] DDR1_CAB[1]/DDR1_MA[15] DDR1_CAB[2]/DDR1_MA[14] DDR1_CAB[3]/DDR1_MA[16]
DDR1_CAB[4]/DDR1_BA[0]
DDR1_CAB[5]/DDR1_MA[2]
DDR1_CAB[6]/DDR1_BA[1]
DDR1_CAB[7]/DDR1_MA[10]
DDR1_CAB[8]/DDR1_MA[1]
DDR1_CAB[9]/DDR1_MA[0]
DDR1_DQSN[0]/DDR0_DQSN[2] DDR1_DQSP[0]/DDR0_DQSP[2] DDR1_DQSN[1]/DDR0_DQSN[3] DDR1_DQSP[1]/DDR0_DQSP[3] DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQSP[2]/DDR0_DQSP[6] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQSP[3]/DDR0_DQSP[7] DDR1_DQSN[4]/DDR1_DQSN[2] DDR1_DQSP[4]/DDR1_DQSP[2] DDR1_DQSN[5]/DDR1_DQSN[3] DDR1_DQSP[5]/DDR1_DQSP[3]
LP3/DDR4
LP3/DDR4
NC/DDR1_MA[3] NC/DDR1_MA[4]
DDR4(IL)/LP3-DDR4(NIL)
DDR1_DQSN[6]
DDR1_DQSP[6]
DDR1_DQSN[7]
DDR1_DQSP[7]
LP3/DDR4
NC/DDR1_ALERT#
NC/DDR1_PAR
DRAM_RESET# DDR_RCOMP[0] DDR_RCOMP[1] DDR_RCOMP[2]
AN45 AN46 AP45 AP46
AN56 AP55 AN55 AP53
BB42 AY42 BA42 AW42
AY48 AP50 BA48 BB48 AP48 AP52 AN50 AN48 AN53 AN52
BA43 AY43 AY44 AW44 BB44 AY47 BA44 AW46 AY46 BA46 BB46 BA47
AH66 AH65 AG69 AG70 AR66 AR65 AR61 AR60 AT38 AR38 AT32 AR32 AR25 AR27 AR22 AR21
AN43 AP43 AT13 AR18 AT18 AU18
M_B_CAA0 M_B_CAA1 M_B_CAA2 M_B_CAA3 M_B_CAA4 M_B_CAA5 M_B_CAA6 M_B_CAA7 M_B_CAA8 M_B_CAA9
M_B_CAB0 M_B_CAB1 M_B_CAB2 M_B_CAB3 M_B_CAB4 M_B_CAB5 M_B_CAB6 M_B_CAB7 M_B_CAB8 M_B_CAB9
M_A_DQSN2 [16] M_A_DQSP2 [16] M_A_DQSN3 [16] M_A_DQSP3 [16] M_A_DQSN6 [16] M_A_DQSP6 [16] M_A_DQSN7 [16] M_A_DQSP7 [16] M_B_DQSN2 [17] M_B_DQSP2 [17] M_B_DQSN3 [17]M_B_DQSP0 [17] M_B_DQSP3 [17] M_B_DQSN6 [17] M_B_DQSP6 [17] M_B_DQSN7 [17] M_B_DQSP7 [17]
SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2
M_B_DIM0_CLKN 0 [17] M_B_DIM0_CLKN 1 [17] M_B_DIM0_CLKP0 [17] M_B_DIM0_CLKP1 [17]
M_B_DIM0_CKE0 [17] M_B_DIM0_CKE1 [17] M_B_DIM0_CKE2 [17] M_B_DIM0_CKE3 [17]
M_B_DIM0_CS0_N [17] M_B_DIM0_CS1_N [17] M_B_DIM0_ODT0 [17]
M_B_CAA[9:0] [17]
M_B_CAB[9:0] [17]
R110042001% R1100580.6 R110061621%
0201 0201 0402
B B
A A
11. CPU(2)_LPDDR3
11. CPU(2)_LPDDR3
11. CPU(2)_LPDDR3
Title:
Title:
Microsoft Conf idential
Microsoft Conf idential
Microsoft Conf idential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
C
C
5
4
3
2
U SPECIFIC
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
Title:
Surface
Surface
Surface
Engineer:
Engineer:
Engineer:
1.0.0.1
1.0.0.1
A
A
A
1
11 79Friday, April 27, 2018
11 79Friday, April 27, 2018
11 79Friday, April 27, 2018
1.0.0.1
V1P2U
Vinafix.com
5
4
3
2
1
0402
C12004 10u
4V
0603
C12002 22u
4V
0402
C12005 10u
4V
0402
C12024 10u
0603
C12003 22u
4V
4V
5
6.3V
0402
C12011 10u
4V
DNP
C12025 10u
0402
VCCPLL_OC
VCCST_CPU
from 1VSB, control SLP_S4 (S3 rail)
C12040
6.3V
1u
0402
VCCSTG
0402
C12041 10u
4V
VCCST_CPU
C12049 1u
0402
REMOVED +VCCEDRAM & +VCCEOPIO RAILS
4
6.3V
C12042 1u
0402
VCORE
AU23 AU28 AU35 AU42
BB23 BB32 BB41 BB47 BB51
AM40
A18
A22
AL23
K20 K21
6.3V
A30 A34 A39
A44 AK33 AK35 AK37 AK38 AK40 AL33 AL37 AL40
AM32 AM33 AM35 AM37 AM38
G30
K32
AK32
AB62
P62
V62
H63
G61
AC63
AE63
AE62
AG62
AL63
AJ62
U10001N
VDDQ_AU23 VDDQ_AU28 VDDQ_AU35 VDDQ_AU42 VDDQ_BB23 VDDQ_BB32 VDDQ_BB41 VDDQ_BB47 VDDQ_BB51
VDDQC
VCCST
VCCSTG_A22
VCCPLL_OC
VCCPLL_K20 VCCPLL_K21
KBL-R U42
<$LOCATION> <MATERIAL> 14 OF 20 REV = 1
KBL_R_U42
CPU POWER 3 OF 4
U10001L
VCCCORE_A30 VCCCORE_A34 VCCCORE_A39 VCCCORE_A44 VCCCORE_AK33 VCCCORE_AK35 VCCCORE_AK37 VCCCORE_AK38 VCCCORE_AK40 VCCCORE_AL33 VCCCORE_AL37 VCCCORE_AL40 VCCCORE_AM32 VCCCORE_AM33 VCCCORE_AM35 VCCCORE_AM37 VCCCORE_AM38 VCCCORE_G30
RSVD_K32
RSVD_AK32
VCCOPC_AB62 VCCOPC_P62 VCCOPC_V62
VCC_OPC_1P8_H63
VCC_OPC_1P8_G61
VCCOPC_SENSE VSSOPC_SENSE
VCCEOPIO_AE62 VCCEOPIO_AG62
VCCEOPIO_SENSE VSSEOPIO_SENSE
KBL-R U42
<$LOCATION> <MATERIAL> 12 OF 20 REV = 1
KBL_R_U42
CPU POWER 1 OF 4
VCCIO_AK28 VCCIO_AK30 VCCIO_AL30
VCCIO_AL42 VCCIO_AM28 VCCIO_AM30 VCCIO_AM42
VCCSA_AK23 VCCSA_AK25
VCCSA_G23 VCCSA_G25 VCCSA_G27 VCCSA_G28
VCCSA_J22 VCCSA_J23
VCCSA_J27 VCCSA_K23 VCCSA_K25 VCCSA_K27 VCCSA_K28 VCCSA_K30
VCCIO_SENSE
VSSIO_SENSE
VSSSA_SENSE
VCCSA_SENSE
3
AK28 AK30 AL30 AL42 AM28 AM30 AM42
AK23 AK25 G23 G25 G27 G28 J22 J23 J27 K23 K25 K27 K28 K30
AM23 AM22
H21 H20
VCCCORE_G32 VCCCORE_G33 VCCCORE_G35 VCCCORE_G37 VCCCORE_G38 VCCCORE_G40 VCCCORE_G42
VCCCORE_J30 VCCCORE_J33 VCCCORE_J37
VCCCORE_J40 VCCCORE_K33 VCCCORE_K35 VCCCORE_K37 VCCCORE_K38 VCCCORE_K40 VCCCORE_K42 VCCCORE_K43
VCC_SENSE
VSS_SENSE
VIDALERT#
VIDSCK
VIDSOUT
VCCSTG_G20
C12089 10p 50V
0201
VCCIO_SENSE [58] VSSIO_SENSE [58]
VSSSA_SENSE [66]
VCCSA_SENSE [66]
VCORE
G32 G33 G35 G37 G38 G40 G42 J30 J33 J37 J40 K33 K35 K37 K38 K40 K42 K43
E32 E33
B63 A63 D64
G20
H_CPU_SVIDALERT_N H_CPU_SVIDCLK H_CPU_SVIDDAT
VCCSTG
VCCIO
6.3V
0402
C12020 1u
C12090 10p 50V
0201
VCC_CORE_SENSE [66]
VSS_CORE_SENSE [66]
+VCCSTG is control by SLP_S0, but it can overwrite by XDP, that means it need power for XDP intrafece
6.3V
0402
C12021 1u
C12043 10u 6.3V
0402
6.3V
0402
C12022 1u
R12005 220 0201 R12006 0 0201 R12007 0 0201
6.3V
0402
C12023 1u
C12044 10u 6.3V
0402
C12045 10u 6.3V
0402
U SPECIFIC
2
C12050 22u 6.3V
0603
C12046 10u 6.3V
0402
0201
Microsoft Confidential
Microsoft Confidential
Microsoft Confidential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
B
B
B
Date: Sheet of
Date: Sheet of
Date: Sheet of
C12051 22u 6.3V
0603
C12047 10u 6.3V
0402
VCCST_CPU
R12004 56
R12003 100
A
A
A
0201
Title:
Title:
Title:
Engineer:
Engineer:
Engineer:
VCCSA
C12048 10u 6.3V
0402
SVID_ALERT# [66] VIDSCLK [66] VIDSOUT [66]
C12034 47u 6.3V
0603
VCCSA
C12069 10u 6.3V
0402
12. CPU(3)_SKL POWER1
12. CPU(3)_SKL POWER1
12. CPU(3)_SKL POWER1
Surface
Surface
Surface
12 79Tuesday, May 01, 2018
12 79Tuesday, May 01, 2018
1
12 79Tuesday, May 01, 2018
C12033 47u 6.3V
0603
DNP
C12070 10u 6.3V
0402
1.0.0.1
1.0.0.1
1.0.0.1
4V
0603
C12001 22u
D D
4V
0402
C12010 10u
C C
B B
A A
5
Vinafix.com
KBL_R_U42
A48 A53 A58 A62
A66 AA63 AA64 AA66 AA67 AA69 AA70 AA71
AC64 AC65 AC66 AC67 AC68 AC69 AC70 AC71
J43
J45
J46
J48
J50
J52
J53
J55
J56
J58
J60
K48
K50
K52
K53
K55
K56
K58
K60
L62
L63
L64
L65
L66
L67
L68
L69
L70
L71
M62 N63 N64 N66 N67 N69
J70
J69
U10001M
CPU POWER 2 OF 4
VCCCORE_A48 VCCCORE_A53 VCCGT_A58 VCCGT_A62 VCCGT_A66 VCCGT_AA63 VCCGT_AA64 VCCGT_AA66 VCCGT_AA67 VCCGT_AA69 VCCGT_AA70 VCCGT_AA71 VCCGT_AC64 VCCGT_AC65 VCCGT_AC66 VCCGT_AC67 VCCGT_AC68 VCCGT_AC69 VCCGT_AC70 VCCGT_AC71 VCCCORE_J43 VCCCORE_J45 VCCCORE_J46 VCCCORE_J48 VCCCORE_J50 VCCCORE_J52 VCCGT_J53 VCCGT_J55 VCCGT_J56 VCCGT_J58 VCCGT_J60 VCCCORE_K48 VCCCORE_K50 RSVD_K52 VCCGT_K53 VCCGT_K55 VCCGT_K56 VCCGT_K58 VCCGT_K60 VCCGT_L62 VCCGT_L63 VCCGT_L64 VCCGT_L65 VCCGT_L66 VCCGT_L67 VCCGT_L68 VCCGT_L69 VCCGT_L70 VCCGT_L71 VCCGT_M62 VCCGT_N63 VCCGT_N64 VCCGT_N66 VCCGT_N67 VCCGT_N69
VCCGT_SENSE VSSGT_SENSE
VCCGT_N70 VCCGT_N71 VCCGT_R63 VCCGT_R64 VCCGT_R65 VCCGT_R66 VCCGT_R67 VCCGT_R68 VCCGT_R69 VCCGT_R70 VCCGT_R71
VCCGT_T62 VCCGT_U65 VCCGT_U68 VCCGT_U71
VCCGT_W63 VCCGT_W64 VCCGT_W65 VCCGT_W66 VCCGT_W67 VCCGT_W68 VCCGT_W69 VCCGT_W70 VCCGT_W71
VCCGT_Y62
VCCCORE_AK42 VCCCORE_AK43 VCCCORE_AK45 VCCCORE_AK46 VCCCORE_AK48 VCCCORE_AK50
RSVD_AK52
VCCGTX_AK53 VCCGTX_AK55 VCCGTX_AK56 VCCGTX_AK58 VCCGTX_AK60
VCCGTX_AK70 VCCCORE_AL43 VCCCORE_AL46 VCCCORE_AL50
VCCGTX_AL53
VCCGTX_AL56
VCCGTX_AL60
VCCCORE_AM48 VCCCORE_AM50 VCCCORE_AM52
VCCGTX_AM53 VCCGTX_AM56 VCCGTX_AM58 VCCGTX_AU58 VCCGTX_AU63
VCCGTX_BB57
VCCGTX_BB66
VCCGTX_SENSE
VSSGTX_SENSE
N70 N71 R63 R64 R65 R66 R67 R68 R69 R70 R71 T62 U65 U68 U71 W63 W64 W65 W66 W67 W68 W69 W70 W71 Y62
AK42 AK43 AK45 AK46 AK48 AK50 AK52 AK53 AK55 AK56 AK58 AK60 AK70 AL43 AL46 AL50 AL53 AL56 AL60 AM48 AM50 AM52 AM53 AM56 AM58 AU58 AU63 BB57 BB66
AK62 AL61
VCORE
D D
C C
VCCGT_SENSE[66] VSSGT_SENSE[66]
4
VCCGTVCCGT
VCORE
VCCGT
3
2
1
Place on primary side, beside the package
C13017 10u 6.3V
0402
C13322 10u 6.3V
0402
C13018 10u 6.3V
0402
C13323 10u 6.3V
0402
C13019 10u 6.3V
0402
C13335 10u 6.3V
0402
C13020 10u 6.3V
0402
C13336 10u 6.3V
0402
C13021 10u 6.3V
0402
C13337 10u 6.3V
0402
C13022 10u 6.3V
0402
C13338 10u 6.3V
0402
C13023 10u 6.3V
0402
C13024 10u 6.3V
0402
C13025 10u 6.3V
0402
C13026 10u 6.3V
0402
Place on secondary side under the package
C13027 10u 6.3V
0402
VCCGT
C13028 10u 6.3V
0402
VCORE
KBL-R U42
<$LOCATION> <MATERIAL> 13 OF 20 REV = 1
REMOVED GTX Connections
C13164
1u
6.3V 0201
C13165
1u
6.3V 0201
C13166
1u
6.3V 0201
VCCGT
Place on primary side, beside the package
C13083 10u 6.3V
0402
C13090 10u 6.3V
0402
B B
VCORE
C13190 47u 6.3V
0603
C13197 47u 6.3V
0603
C13084 10u 6.3V
0402
C13091
6.3V
10u
0402
C13191 47u 6.3V
0603
C13198 47u 6.3V
0603
C13330 10u 6.3V
0402
C13085 10u 6.3V
0402
C13097 10u 6.3V
0402
C13192 47u 6.3V
0603
C13199 47u 6.3V
0603
C13332 10u 6.3V
0402
C13086 10u 6.3V
0402
C13098 10u 6.3V
0402
C13193 47u 6.3V
0805
C13200 47u 6.3V
0603 DNP
C13333 10u 6.3V
0402
C13087 10u 6.3V
0402
C13099 10u 6.3V
0402
C13194 47u 6.3V
0805
C13201 47u 6.3V
0603
C13329 10u 6.3V
0402
C13088 10u 6.3V
0402
C13195 47u 6.3V
0603
C13202 47u 6.3V
0603
C13331 10u 6.3V
0402
C13089 10u 6.3V
0402
C13196 47u 6.3V
0603
C13203 47u 6.3V
0603
C13334 10u 6.3V
0402
VCCGT
Place on primary side, beside the package
C13300 22u
0603
C13306 22u
0603 DNP
6.3V
6.3V
C13301 22u
0603
C13307 22u
0603 DNP
6.3V
6.3V
C13302 22u
0603
C13308 22u
0603 DNP
6.3V
6.3V
C13303 22u
0603
C13309 22u
0603 DNP
6.3V
6.3V
C13304 22u
0603
C13310 22u
0603 DNP
6.3V
6.3V
C13311 22u
0603
C13314 22u
0603 DNP
6.3V
6.3V
C13312 22u
0603
C13315 22u
0603 DNP
6.3V
6.3V
C13313 22u
0603 DNP
C13316 22u
0603 DNP
6.3V
6.3V
C13317 22u
0603 DNP
6.3V
C13167
1u
6.3V 0201
C13168
1u
6.3V 0201
C13169
1u
6.3V 0201
DNP
DNP
C13343 10u 6.3V
0402
C13348 10u 6.3V
0402
DNP
DNP
C13341 10u 6.3V
0402
C13346 10u 6.3V
0402
C13340 10u 6.3V
0402
DNP
C13345 10u 6.3V
0402
A A
DNP
VCORE
C13339
6.3V
10u
0402
DNP
C13344
6.3V
10u
0402
DNP
Place on secondary side under the package
C13171
1u
0201
6.3V
5
C13172
1u
0201
6.3V
C13170
1u
0201
6.3V
DNP
DNP
C13342 10u 6.3V
0402
C13347 10u 6.3V
0402
VCORE
Place on secondary side under the package
C13173
1u
0201
6.3V
C13174
1u
0201
6.3V
4
C13175
1u
0201
6.3V
VCCGT
Place on primary side, beside the package
C13122 47u 6.3V
DNP
3
0603
C13123 47u 6.3V
0805
DNP
C13131 47u 6.3V
0805
DNP
C13106 47u 6.3V
0603
C13107 47u 6.3V
0603
C13108 47u 6.3V
2
C13109
47u 6.3V
0603 DNP
DNP 0603
U SPECIFIC
C13305 47u 6.3V
0805
DNP
C13318 47u 6.3V
0603
DNP
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
C13319 47u 6.3V
0805 DNP
Microsoft Conf idential
Microsoft Conf idential
Microsoft Conf idential
C
C
C
C13320 47u 6.3V
0603
DNP
Title:
Title:
Title:
Engineer:
Engineer:
Engineer:
A
A
A
C13321 47u 6.3V
0805
DNP
13. CPU(4)_SKL_POWER2
13. CPU(4)_SKL_POWER2
13. CPU(4)_SKL_POWER2
Surface
Surface
Surface
13 79Tuesday, May 01, 2018
13 79Tuesday, May 01, 2018
1
13 79Tuesday, May 01, 2018
1.0.0.1
1.0.0.1
1.0.0.1
5
Vinafix.com
U10001P
KBL_R_U42
GND 1 OF 3
A5
VSS_A5
A67
VSS_A67
A70
VSS_A70
AA2
D D
C C
AG16 AG17 AG18 AG19 AG20 AG21 AG71
B B
AA4 AA65 AA68 AB15 AB16 AB18 AB21
AB8 AD13 AD16 AD19 AD20 AD21 AD62
AD8 AE64 AE65 AE66 AE67 AE68 AE69
AF1 AF10 AF15 AF17
AF2
AF4 AF63
AH13
AH6 AH63 AH64 AH67
AJ15 AJ18 AJ20
AJ4 AK11 AK16 AK18 AK21 AK22 AK27 AK63 AK68 AK69
AK8
AL2
AL28 AL32 AL35 AL38
AL4
AL45 AL48 AL52 AL55 AL58 AL64
VSS_AA2 VSS_AA4 VSS_AA65 VSS_AA68 VSS_AB15 VSS_AB16 VSS_AB18 VSS_AB21 VSS_AB8 VSS_AD13 VSS_AD16 VSS_AD19 VSS_AD20 VSS_AD21 VSS_AD62 VSS_AD8 VSS_AE64 VSS_AE65 VSS_AE66 VSS_AE67 VSS_AE68 VSS_AE69 VSS_AF1 VSS_AF10 VSS_AF15 VSS_AF17 VSS_AF2 VSS_AF4 VSS_AF63 VSS_AG16 VSS_AG17 VSS_AG18 VSS_AG19 VSS_AG20 VSS_AG21 VSS_AG71 VSS_AH13 VSS_AH6 VSS_AH63 VSS_AH64 VSS_AH67 VSS_AJ15 VSS_AJ18 VSS_AJ20 VSS_AJ4 VSS_AK11 VSS_AK16 VSS_AK18 VSS_AK21 VSS_AK22 VSS_AK27 VSS_AK63 VSS_AK68 VSS_AK69 VSS_AK8 VSS_AL2 VSS_AL28 VSS_AL32 VSS_AL35 VSS_AL38 VSS_AL4 VSS_AL45 VSS_AL48 VSS_AL52 VSS_AL55 VSS_AL58 VSS_AL64
VSS_AL65
VSS_AL66 VSS_AM13 VSS_AM21 VSS_AM25 VSS_AM27 VSS_AM43 VSS_AM45 VSS_AM46 VSS_AM55 VSS_AM60 VSS_AM61 VSS_AM68 VSS_AM71
VSS_AM8 VSS_AN20 VSS_AN23 VSS_AN28 VSS_AN30 VSS_AN32 VSS_AN33 VSS_AN35 VSS_AN37 VSS_AN38 VSS_AN40 VSS_AN42 VSS_AN58 VSS_AN63 VSS_AP10 VSS_AP18 VSS_AP20 VSS_AP23 VSS_AP28 VSS_AP32 VSS_AP35 VSS_AP38 VSS_AP42 VSS_AP58 VSS_AP63 VSS_AP68 VSS_AP70 VSS_AR11 VSS_AR15 VSS_AR16 VSS_AR20 VSS_AR23 VSS_AR28 VSS_AR35 VSS_AR42 VSS_AR43 VSS_AR45 VSS_AR46 VSS_AR48
VSS_AR5 VSS_AR50 VSS_AR52 VSS_AR53 VSS_AR55 VSS_AR58 VSS_AR63
VSS_AR8
VSS_AT2 VSS_AT20 VSS_AT23 VSS_AT28 VSS_AT35
VSS_AT4 VSS_AT42 VSS_AT56 VSS_AT58
AL65 AL66 AM13 AM21 AM25 AM27 AM43 AM45 AM46 AM55 AM60 AM61 AM68 AM71 AM8 AN20 AN23 AN28 AN30 AN32 AN33 AN35 AN37 AN38 AN40 AN42 AN58 AN63 AP10 AP18 AP20 AP23 AP28 AP32 AP35 AP38 AP42 AP58 AP63 AP68 AP70 AR11 AR15 AR16 AR20 AR23 AR28 AR35 AR42 AR43 AR45 AR46 AR48 AR5 AR50 AR52 AR53 AR55 AR58 AR63 AR8 AT2 AT20 AT23 AT28 AT35 AT4 AT42 AT56 AT58
4
AT63 AT68
AT71 AU10 AU15 AU20 AU32 AU38
AV1 AV68 AV69 AV70 AV71
AW10 AW12 AW14 AW16 AW18 AW21 AW23 AW26 AW28 AW30 AW32 AW34 AW36 AW38 AW41 AW43 AW45 AW47 AW49 AW51 AW53 AW55 AW57
AW6 AW60 AW62 AW64 AW66
AW8
AY66
B10 B14 B18 B22 B30 B34 B39 B44 B48 B53 B58 B62 B66 B71
BA1 BA10 BA14 BA18
BA2 BA23 BA28 BA32 BA36
F68
BA45
U10001Q
KBL_R_U42
GND 2 OF 3
VSS_AT63 VSS_AT68 VSS_AT71 VSS_AU10 VSS_AU15 VSS_AU20 VSS_AU32 VSS_AU38 VSS_AV1 VSS_AV68 VSS_AV69 VSS_AV70 VSS_AV71 VSS_AW10 VSS_AW12 VSS_AW14 VSS_AW16 VSS_AW18 VSS_AW21 VSS_AW23 VSS_AW26 VSS_AW28 VSS_AW30 VSS_AW32 VSS_AW34 VSS_AW36 VSS_AW38 VSS_AW41 VSS_AW43 VSS_AW45 VSS_AW47 VSS_AW49 VSS_AW51 VSS_AW53 VSS_AW55 VSS_AW57 VSS_AW6 VSS_AW60 VSS_AW62 VSS_AW64 VSS_AW66 VSS_AW8 VSS_AY66 VSS_B10 VSS_B14 VSS_B18 VSS_B22 VSS_B30 VSS_B34 VSS_B39 VSS_B44 VSS_B48 VSS_B53 VSS_B58 VSS_B62 VSS_B66 VSS_B71 VSS_BA1 VSS_BA10 VSS_BA14 VSS_BA18 VSS_BA2 VSS_BA23 VSS_BA28 VSS_BA32 VSS_BA36 VSS_F68 VSS_BA45
VSS_BA49 VSS_BA53 VSS_BA57
VSS_BA6 VSS_BA62 VSS_BA66 VSS_BA71 VSS_BB18 VSS_BB26 VSS_BB30 VSS_BB34 VSS_BB38 VSS_BB43 VSS_BB55
VSS_BB6 VSS_BB60 VSS_BB64 VSS_BB67 VSS_BB70
VSS_C1
VSS_C25
VSS_C5 VSS_D10 VSS_D11 VSS_D14 VSS_D18 VSS_D22 VSS_D25 VSS_D26 VSS_D30 VSS_D34 VSS_D39 VSS_D44 VSS_D45 VSS_D47 VSS_D48 VSS_D53 VSS_D58
VSS_D6 VSS_D62 VSS_D66 VSS_D69 VSS_E11 VSS_E15 VSS_E18 VSS_E21 VSS_E46 VSS_E50 VSS_E53 VSS_E56
VSS_E6 VSS_E65 VSS_E71
VSS_F1
VSS_F13
VSS_F2 VSS_F22 VSS_F23 VSS_F27 VSS_F28 VSS_F32 VSS_F33 VSS_F35 VSS_F37 VSS_F38
VSS_F4 VSS_F40 VSS_F42
VSS_BA41
BA49 BA53 BA57 BA6 BA62 BA66 BA71 BB18 BB26 BB30 BB34 BB38 BB43 BB55 BB6 BB60 BB64 BB67 BB70 C1 C25 C5 D10 D11 D14 D18 D22 D25 D26 D30 D34 D39 D44 D45 D47 D48 D53 D58 D6 D62 D66 D69 E11 E15 E18 E21 E46 E50 E53 E56 E6 E65 E71 F1 F13 F2 F22 F23 F27 F28 F32 F33 F35 F37 F38 F4 F40 F42 BA41
3
U10001R
KBL_R_U42
GND 3 OF 3
F8 G10 G22 G43 G45 G48
G5 G52 G55 G58
G6 G60 G63 G66 H15 H18 H71
J11 J13 J25 J28 J32 J35 J38 J42
J8 K16 K18 K22 K61 K63 K64 K65 K66 K67 K68 K70 K71
L11 L16 L17
KBL-R U42
<$LOCATION> <MATERIAL> 18 OF 20 REV = 1
VSS_F8 VSS_G10 VSS_G22 VSS_G43 VSS_G45 VSS_G48 VSS_G5 VSS_G52 VSS_G55 VSS_G58 VSS_G6 VSS_G60 VSS_G63 VSS_G66 VSS_H15 VSS_H18 VSS_H71 VSS_J11 VSS_J13 VSS_J25 VSS_J28 VSS_J32 VSS_J35 VSS_J38 VSS_J42 VSS_J8 VSS_K16 VSS_K18 VSS_K22 VSS_K61 VSS_K63 VSS_K64 VSS_K65 VSS_K66 VSS_K67 VSS_K68 VSS_K70 VSS_K71 VSS_L11 VSS_L16 VSS_L17
VSS_L18
VSS_L2
VSS_L20
VSS_L4
VSS_L8 VSS_N10 VSS_N13 VSS_N19 VSS_N21
VSS_N6 VSS_N65 VSS_N68 VSS_P17 VSS_P19 VSS_P20 VSS_P21 VSS_R13
VSS_R6 VSS_T15 VSS_T17 VSS_T18
VSS_T2 VSS_T21
VSS_T4 VSS_U10 VSS_U63 VSS_U64 VSS_U66 VSS_U67 VSS_U69 VSS_U70 VSS_V16 VSS_V17 VSS_V18
VSS_W13
VSS_W6
VSS_W9 VSS_Y17 VSS_Y19 VSS_Y20 VSS_Y21
L18 L2 L20 L4 L8 N10 N13 N19 N21 N6 N65 N68 P17 P19 P20 P21 R13 R6 T15 T17 T18 T2 T21 T4 U10 U63 U64 U66 U67 U69 U70 V16 V17 V18 W13 W6 W9 Y17 Y19 Y20 Y21
2
1
KBL-R U42
A A
<$LOCATION> <MATERIAL> 16 OF 20 REV = 1
5
4
KBL-R U42
<$LOCATION> <MATERIAL> 17 OF 20 REV = 1
14. CPU(5)_GND
14. CPU(5)_GND
Title:
Title:
Title:
Microsoft Confidential
Microsoft Confidential
Microsoft Confidential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
B
B
U SPECIFIC
3
2
B
Date: Sheet of
Date: Sheet of
Date: Sheet of
A
A
A
Engineer:
Engineer:
Engineer:
14. CPU(5)_GND
Surface
Surface
Surface
14 79Friday, April 27, 2018
14 79Friday, April 27, 2018
1
14 79Friday, April 27, 2018
1.0.0.1
1.0.0.1
1.0.0.1
5
Vinafix.com
Vinafix.com
4
3
2
1
KBL_R_U42
RSVD_TP_BB68 RSVD_TP_BB69
RSVD_TP_AK13 RSVD_TP_AK12
RSVD_BB2 RSVD_BA3
TP5 TP6
RSVD_D5 RSVD_D4 RSVD_B2 RSVD_C2
RSVD_B3 RSVD_A3
RSVD_AW1
RSVD_E1 RSVD_E2
RSVD_BA4 RSVD_BB4
RSVD_A4 RSVD_C4
TP4
RSVD_A69 RSVD_B69
RSVD_AY3
RSVD_D71 RSVD_C70
RSVD_C54 RSVD_D54
TP1 TP2
VSS_AY71
ZVM#
RSVD_TP_AW71 RSVD_TP_AW70
MSM#
PROC_SELECT#
BB68 BB69
AK13 AK12
BB2 BA3
AU5 AT5
D5 D4 B2 C2
B3 A3
AW1
E1 E2
BA4 BB4
A4 C4
BB5
A69 B69
AY3
D71 C70
C54 D54
AY4 BB3
AY71 AR56
AW71 AW70
AP56 C64
RSVD_TP_AK13 RSVD_TP_AK12
SMD RND 22.8mil
GTP15002 GTP15003
SMD RND 22.8mil
GTP15004
SMD RND 22.8mil
ZVM# and MSM# may need to control the VCCOPC and VCCEOPIO
E68
B67 D65 D67
E70 C68 D68 C67
F71
G69
F70
G68
H70
G71
H69
G70
E63
F63
E66
F66
E60
E8
AY2 AY1
D1 D3
K46
K45
AL25 AL27
C71
B70
F60
A52
BA70 BA68
J71 J68
F65
G65
F61
E61
U10001S
CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15]
CFG[16] CFG[17]
CFG[18] CFG[19]
CFG_RCOMP
ITP_PMODE
RSVD_AY2 RSVD_AY1
RSVD_D1 RSVD_D3
RSVD_K46 RSVD_K45
RSVD_AL25 RSVD_AL27
RSVD_C71 RSVD_B70
RSVD_F60
RSVD_A52
RSVD_TP_BA70 RSVD_TP_BA68
RSVD_J71 RSVD_J68
VSS_F65 VSS_G65
RSVD_F61 RSVD_E61
KBL-R U42
<$LOCATION> <MATERIAL> 19 OF 20 REV = 1
RESERVED SIGNALS-1
GTP15001
SMD RND 22.8mil
CFG0[18] CFG1[18] CFG2[18] CFG3[18]
D D
CFG4
0 enable eDP
Default
C C
B B
1
Disable eDP
CFG4[18] CFG5[18] CFG6[18] CFG7[18] CFG8[18] CFG9[18] CFG10[18] CFG11[18] CFG12[18] CFG13[18] CFG14[18] CFG15[18]
CFG16[18] CFG17[18]
CFG18[18] CFG19[18]
AW69 AW68
AU56
AW48
U10001T
C7 U12 U11 H11
KBL-R U42
<$LOCATION> <MATERIAL> 20 OF 20 REV = 1
KBL_R_U42
RSVD_AW69 RSVD_AW68 RSVD_AU56 RSVD_AW48 XTAL24_OUT RSVD_U12 RSVD_U11 RSVD_H11
R15001 49.9
R15002 1K
0201
RSVD/XTAL
0201
ITP_PMODE[18]
RSVD_F6 XTAL24_IN RSVD_C11 RSVD_B11 RSVD_A11 RSVD_D12 RSVD_C12
RSVD_F52
F6 E3 C11 B11 A11 D12 C12 F52
XTAL_24M_OUT
CFG_RCOMP
XTAL_24M_IN
R1504 1M
0201S_P28-W35
X150124MHz
R1503 0
0201S_P28-W35
C1503
A A
5
50V
0201S_P33
10p
4
3 1
GND
X948599-001
24
C1502
50V
10p
0201S_P33
15. CPU(6)_CFG_RESERVED
15. CPU(6)_CFG_RESERVED
Title:
Title:
Title:
Microsoft Confidential
Microsoft Confidential
Microsoft Confidential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
B
B
U SPECIFIC
3
2
B
Date: Sheet of
Date: Sheet of
Date: Sheet of
A
A
A
Engineer:
Engineer:
Engineer:
15. CPU(6)_CFG_RESERVED
Surface
Surface
Surface
1.0.0.1
1.0.0.1
1.0.0.1
15 79Friday, April 27, 2018
15 79Friday, April 27, 2018
1
15 79Friday, April 27, 2018
5
Vinafix.com
U16001 H9CCNNN BLTBLAR-NUD
M_A_CAA0 M_A_CAA1 M_A_CAA2 M_A_CAA3 M_A_CAA4 M_A_CAA5 M_A_CAA6 M_A_CAA7 M_A_CAA8 M_A_CAA9
D D
M_A_DIM0_CLKP1[11,16] M_A_DIM0_CLKN 1[11,16]
M_A_DIM0_CKE2[11,16] M_A_DIM0_CKE3[11,16] M_A_DIM0_CKE1[11,16]
M_A_DIM0_CS0_N[11,16] M_A_DIM0_CS1_N[11,16]
M_A_DQSP2[11] M_A_DQSN2[11]
C C
B B
V0P6DX_LPDDR3
A A
M_A_DQSP0[11] M_A_DQSN0[11]
M_A_DQSP3[11] M_A_DQSN3[11]
M_A_DQSP1[11] M_A_DQSN1[11]
C16072 1u
6.3V 0402
distributed along terminations. Shown in blue Figure 4-57 in PDG2.0
C16073 1u
6.3V 0402
C16074 1u
6.3V 0402
R2 P2 N2 N3
M3
F3 E3 E2 D2 C2
J3 J2
K3 K4
L3 L4
L8
G8
P8 D8
A1
A2 A12 A13
B1 B13
T1 T13
U1
U2 U12 U13
L10 L11
G10 G11
P10 P11
D10 D11
B2
B5
C5
E4
E5
F5
H2 J12
K2
L6
M5
N4
N5
R4
R5
T2
T3
T4
T5
C3
D3
F4
G3 G4
J4
M4
P3
B6
B12
C6
D12
E6
F6 F12
G6
G9 H10 K10
L9
M6 M12
N6
P12
R6 T6
T12
C16075 1u
6.3V 0402
CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9
CK CK#
CKE0 CKE1
CS#0 CS#1
DM0 DM1 DM2 DM3/NC
DNU1 DNU2 DNU3 DNU4 DNU5 DNU6 DNU7 DNU8 DNU9 DNU10 DNU11 DNU12
DQS0 DQS0#
DQS1 DQS1#
DQS2/NC DQS2#/NC
DQS3/NC DQS3#/NC
VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19
VSSCA1 VSSCA2 VSSCA3 VSSCA4 VSSCA5 VSSCA6 VSSCA7 VSSCA8
VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9 VSSQ10 VSSQ11 VSSQ12 VSSQ13 VSSQ14 VSSQ15 VSSQ16 VSSQ17 VSSQ18 VSSQ19
TBL1601
C16076 1u
6.3V 0402
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8
DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DQ16/NC DQ17/NC DQ18/NC DQ19/NC DQ20/NC DQ21/NC DQ22/NC DQ23/NC DQ24/NC DQ25/NC DQ26/NC DQ27/NC DQ28/NC DQ29/NC DQ30/NC DQ31/NC
VDD1_1 VDD1_3 VDD1_5 VDD1_7 VDD1_9 VDD1_2 VDD1_4 VDD1_6 VDD1_8
VDD1_10
VDD2_1 VDD2_2 VDD2_3 VDD2_4 VDD2_5 VDD2_6 VDD2_7 VDD2_8
VDD2_9 VDD2_10 VDD2_11 VDD2_12 VDD2_13 VDD2_14 VDD2_15 VDD2_16 VDD2_17 VDD2_18 VDD2_19 VDD2_20
VDDCA1 VDDCA2 VDDCA3 VDDCA4 VDDCA5
VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8
VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17
VREFCA VREFDQ
ODT
ZQ0 ZQ1
NC1 NC2 NC3
C16077 1u
6.3V 0402
P9 N9 N10 N11 M8 M9 M10 M11 F11 F10 F9 F8 E11 E10 E9 D9 T8 T9 T10 T11 R8 R9 R10 R11 C11 C10 C9 C8 B11 B10 B9 B8
A3 A4 A5 A6 A10 U3 U4 U5 U6 U10
A8 A9 D4 D5 D6 G5 H5 H6 H12 J5 J6 K5 K6 K12 L5 P4 P5 P6 U8 U9
F2 G2 H3 L2 M2
A11 C12 E8 E12 G12 H8 H9 H11 J9 J10 K8 K11 L12 N8 N12 R12 U11
H4 J11
J8
B3 B4
C4 K9 R3
ZQ1601 ZQ1602
C16078 1u
6.3V 0402
M_A_D16 M_A_D17 M_A_D23 M_A_D18 M_A_D21 M_A_D20 M_A_D22 M_A_D19 M_A_D7 M_A_D0 M_A_D4 M_A_D1 M_A_D6 M_A_D3 M_A_D5 M_A_D2
M_A_D29 M_A_D28 M_A_D31 M_A_D26 M_A_D25 M_A_D24 M_A_D27 M_A_D30 M_A_D9 M_A_D12 M_A_D15 M_A_D11 M_A_D13 M_A_D8 M_A_D14 M_A_D10
V1P2U
V1P2U
V1P2U
M_A_DIM0_ODT0 [11,16]
R16034 2431% R16035 2431%
C16079 1u
6.3V 0402
0402
0402 TBL1601
DNP For 4GB System Memory: R16035, R16036
M_A_D[23:16] [11]
M_A_D[7:0] [11]
M_A_D[31:24] [11]
M_A_D[15:8] [11]
V1P8U_2P5U
V_VREF_CA_DIM M
C16090 1u
6.3V 0402 DNP
4
M_A_CAB[9:0][11,16]
V_VREF_DQ_DIM M0
C16091 1u
6.3V 0402 DNP
C16092 1u
6.3V 0402 DNP
3
U16002 H9CCNNN BLTBLAR-NUD
M_A_CAB0 M_A_CAB1 M_A_CAB2 M_A_CAB3 M_A_CAB4 M_A_CAB5 M_A_CAB6 M_A_CAB7 M_A_CAB8 M_A_CAB9
M_A_DIM0_CLKP0[11,16] M_A_DIM0_CLKN 0[11,16]
M_A_DIM0_CKE0[11,16]
M_A_DIM0_CS0_N[11,16] M_A_DIM0_CS1_N[11,16]
M_A_DQSP7[11] M_A_DQSN7[11]
M_A_DQSP4[11] M_A_DQSN4[11]
M_A_DQSP6[11] M_A_DQSN6[11]
M_A_DQSP5[11] M_A_DQSN5[11]
C16093 1u
6.3V 0402 DNP
C16094 1u
6.3V 0402 DNP
C16095 1u
6.3V 0402 DNP
R2
CA0
P2
CA1
N2
CA2
N3
CA3
M3
CA4
F3
CA5
E3
CA6
E2
CA7
D2
CA8
C2
CA9
J3
CK
J2
CK#
K3
CKE0
K4
CKE1
L3
CS#0
L4
CS#1
L8
DM0
G8
DM1
P8
DM2
D8
DM3/NC
A1
DNU1
A2
DNU2
A12
DNU3
A13
DNU4
B1
DNU5
B13
DNU6
T1
DNU7
T13
DNU8
U1
DNU9
U2
DNU10
U12
DNU11
U13
DNU12
L10
DQS0
L11
DQS0#
G10
DQS1
G11
DQS1#
P10
DQS2/NC
P11
DQS2#/NC
D10
DQS3/NC
D11
DQS3#/NC
B2
VSS1
B5
VSS2
C5
VSS3
E4
VSS4
E5
VSS5
F5
VSS6
H2
VSS7
J12
VSS8
K2
VSS9
L6
VSS10
M5
VSS11
N4
VSS12
N5
VSS13
R4
VSS14
R5
VSS15
T2
VSS16
T3
VSS17
T4
VSS18
T5
VSS19
C3
VSSCA1
D3
VSSCA2
F4
VSSCA3
G3
VSSCA4
G4
VSSCA5
J4
VSSCA6
M4
VSSCA7
P3
VSSCA8
B6
VSSQ1
B12
VSSQ2
C6
VSSQ3
D12
VSSQ4
E6
VSSQ5
F6
VSSQ6
F12
VSSQ7
G6
VSSQ8
G9
VSSQ9
H10
VSSQ10
K10
VSSQ11
L9
VSSQ12
M6
VSSQ13
M12
VSSQ14
N6
VSSQ15
P12
VSSQ16
R6
VSSQ17
T6
VSSQ18
T12
VSSQ19
TBL1601
C16080
6.3V
22u
0603
Edge of vtt island. Caps shown in green Figure 4-57 in PDG2.0
DQ16/NC DQ17/NC DQ18/NC DQ19/NC DQ20/NC DQ21/NC DQ22/NC DQ23/NC DQ24/NC DQ25/NC DQ26/NC DQ27/NC DQ28/NC DQ29/NC DQ30/NC DQ31/NC
VDD1_1 VDD1_3 VDD1_5 VDD1_7 VDD1_9 VDD1_2 VDD1_4 VDD1_6 VDD1_8
VDD1_10
VDD2_1 VDD2_2 VDD2_3 VDD2_4 VDD2_5 VDD2_6 VDD2_7 VDD2_8
VDD2_9 VDD2_10 VDD2_11 VDD2_12 VDD2_13 VDD2_14 VDD2_15 VDD2_16 VDD2_17 VDD2_18 VDD2_19 VDD2_20
VDDCA1 VDDCA2 VDDCA3 VDDCA4 VDDCA5
VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8
VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17
VREFCA VREFDQ
C16081 22u
0603
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8
DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
ODT
ZQ0
ZQ1
NC1
NC2
NC3
6.3V
M_A_D58
P9
M_A_D61
N9
M_A_D56
N10
M_A_D57
N11
M_A_D60
M8
M_A_D59
M9
M_A_D62
M10
M_A_D63
M11
M_A_D37
F11
M_A_D38
F10
M_A_D32
F9
M_A_D36
F8
M_A_D33
E11
M_A_D39
E10
M_A_D34
E9
M_A_D35
D9
M_A_D52
T8
M_A_D51
T9
M_A_D50
T10
M_A_D48
T11
M_A_D53
R8
M_A_D54
R9
M_A_D55
R10
M_A_D49
R11
M_A_D41
C11
M_A_D45
C10
M_A_D44
C9
M_A_D46
C8
M_A_D40
B11
M_A_D47
B10
M_A_D42
B9
M_A_D43
B8
A3 A4 A5 A6 A10 U3 U4 U5 U6 U10
A8 A9 D4 D5 D6 G5 H5 H6 H12 J5 J6 K5 K6 K12 L5 P4 P5 P6 U8 U9
F2 G2 H3 L2 M2
A11 C12 E8 E12 G12 H8 H9 H11 J9 J10 K8 K11 L12 N8 N12 R12 U11
H4 J11
J8
M_A_DIM0_ODT0 [11,16]
B3
ZQ1603
B4
ZQ1604
C4 K9 R3
V1P2U
V1P2U
R16033 2431% R16036 2431%
M_A_D[63:56] [11]M_A_CAA[9:0][11,16]
V_VREF_CA_DIM M V_VREF_DQ_DIM M0
C16005 10u
6.3V
0402
C16065 1u
6.3V 0402
C16001 47000p
6.3V 0201
V1P8U_2P5U
C16011 1u
6.3V 0402
V1P2U
C16083 10u
6.3V
0402
M_A_D[39:32] [11]
M_A_D[55:48] [11]
M_A_D[47:40] [11]
V1P8U_2P5U
5 distributed. the Figure 4-56 at PDG2.0 the pink circle.
V1P8U_2P5U
C16010 1u
6.3V 0402
5 distributed. Look the Figure 4-56 at PDG2.0 the blue circle.
3 near each DRAM. Look the Figure 4-55 at PDG2.0 the
V1P2U
0402
0402 TBL1601
V1P2U
blue circle.
V_VREF_CA_DIM M
V_VREF_DQ_DIM M0
C16064 1u
6.3V 0402
C16082 10u
6.3V
0402
C16096 10p
50V 0201
C16023 1u
6.3V 0402
V1P2U
C16066 1u
6.3V 0402
C16002 47000p
6.3V 0201
R16021
0
0603
For 1.8V sensing
C16006 10u
6.3V
0402
C16018 10u
6.3V
0402
C16012 1u
6.3V 0402
C16024 1u
6.3V 0402
C16067 1u
6.3V 0402
C16084 10u
6.3V
0402
C16035
0.1u
6.3V 0201
C16043 1u
6.3V 0402
C16051 1u
6.3V 0402
C16061 10u
6.3V
0402
C16007 10u
6.3V
0402
2
C16003 47000p
6.3V 0201
1P8V_DUAL_VR_FB_R [58]
C16008 10u
6.3V
0402
GND
C16013 1u
6.3V 0402
C16014 1u
6.3V 0402
C16019 10u
6.3V
0402
C16025 1u
6.3V 0402
C16036
0.1u
6.3V 0201
C16044 1u
6.3V 0402
C16052 1u
6.3V 0402
C16068 1u
6.3V 0402
C16026 1u
6.3V 0402
C16059 10u
6.3V
0402
C16069 1u
6.3V 0402
3 distributed. Look the Figure 4-56 at PDG2.0 the yellow circle.
C16004 47000p
6.3V 0201
C16037
0.1u
6.3V 0201
C16045 1u
6.3V 0402
C16053 1u
6.3V 0402
C16009 10u
6.3V
0402
C16015 1u
6.3V 0402
C16020 10u
6.3V
0402
C16027 1u
6.3V 0402
C16038
0.1u
6.3V 0201
C16046 1u
6.3V 0402
C16054 1u
6.3V 0402
C16062 10u
6.3V
0402
C16070 1u
6.3V 0402
C16097 2p
25V 0201
M_A_CAB[9:0][11,16]
C16016 1u
6.3V 0402
10u C16021
0402
6.3V
C16028 1u
6.3V 0402
C16039
0.1u
6.3V 0201
C16047 1u
6.3V 0402
C16055 1u
6.3V 0402
C16071 1u
6.3V 0402
C16017 1u
6.3V 0402
C16029 1u
6.3V 0402
C16040
0.1u
6.3V 0201
C16048 1u
6.3V 0402
C16056 1u
6.3V 0402
C16063 10u
6.3V
0402
2 near each DRAM. Look the Figure 4-55 at PDG2.0 the yellow circle.
M_A_CAA[9:0][11,16]
C16022 10u
6.3V
0402
M_A_DIM0_ODT0[11,16] M_A_DIM0_CS0_N[11,16] M_A_DIM0_CS1_N[11,16] M_A_DIM0_CKE0[11,16] M_A_DIM0_CKE1[11,16] M_A_DIM0_CKE2[11,16] M_A_DIM0_CKE3[11,16]
M_A_DIM0_CLKP0[11,16] M_A_DIM0_CLKN 0[11,16] M_A_DIM0_CLKP1[11,16] M_A_DIM0_CLKN 1[11,16]
V1P2U
C16030 1u
6.3V 0402
C16041
0.1u
6.3V 0201
C16049 1u
6.3V 0402
C16057 1u
6.3V 0402
C16060 10u
6.3V
0402
1
M_A_CAA0 M_A_CAA1 M_A_CAA2 M_A_CAA3 M_A_CAA4 M_A_CAA5 M_A_CAA6 M_A_CAA7 M_A_CAA8 M_A_CAA9
M_A_CAB0 M_A_CAB1 M_A_CAB2 M_A_CAB3 M_A_CAB4 M_A_CAB5 M_A_CAB6 M_A_CAB7 M_A_CAB8 M_A_CAB9
2 near each DRAM. Look the Figure 4-55 at PDG2.0 the pink circle.
R16037
0603
C16031 1u
6.3V 0402
C16042
0.1u
6.3V 0201
C16058 1u
6.3V 0402
5 distributed. Look the Figure 4-56 at PDG2.0 the red circle (VDDQ).
R16001 68 5% 0201 R16002 68 5% 0201 R16003 68 5% 0201 R16004 68 5% 0201 R16005 68 5% 0201 R16006 68 5% 0201 R16007 68 5% 0201 R16008 68 5% 0201 R16009 68 5% 0201 R16010 68 5% 0201
R16011 68 5% 0201 R16012 68 5% 0201 R16013 68 5% 0201 R16014 68 5% 0201 R16015 68 5% 0201 R16016 68 5% 0201 R16017 68 5% 0201 R16018 68 5% 0201 R16019 68 5% 0201 R16020 68 5% 0201
R16022 80.6 0201 R16023 80.6 0201 R16024 80.6 0201 R16025 80.6 0201 R16026 80.6 0201 R16027 80.6 0201 R16028 80.6 0201
R16029 37.4 0201 R16030 37.4 0201 R16031 37.4 0201
R16032 37.4 0201
0
V1P2U_VR_FB_R [58]
For 1.2V sensing
C16032 1u
6.3V 0402
2 near each DRAM. Look the Figure 4-55 at PDG2.0 the red circle.
C16050 1u
6.3V 0402
4 near each DRAM. Look the Figure 4-55 at PDG2.0 the red circle (big one).
C16033 1u
6.3V 0402
TBL1601, SEE PAGE 23
V0P6DX_LPDDR3
C16034 1u
6.3V 0402
16. LPDDR3(1)_M EMORY DOW N
16. LPDDR3(1)_M EMORY DOW N
16. LPDDR3(1)_M EMORY DOW N
Title:
Title:
Microsoft Conf idential
Microsoft Conf idential
Microsoft Conf idential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
C
C
5
4
3
2
U SPECIFIC
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
Title:
Surface
Surface
1
Surface
1.0.0.1
1.0.0.1
16 79Thursday, April 26, 2018
16 79Thursday, April 26, 2018
16 79Thursday, April 26, 2018
1.0.0.1
Engineer:
Engineer:
Engineer:
A
A
A
5
Vinafix.com
4
3
2
1
U17001
M_B_CAA[9:0][11,17] M_B_CAB[9:0][11,17]
D D
M_B_DIM0_CLKP0[11,17] M_B_DIM0_CLKN 0[11,17]
M_B_DIM0_CKE0[11,17] M_B_DIM0_CKE1[11,17]
M_B_DIM0_CS0_N[11,17] M_B_DIM0_CS1_N[11,17]
M_B_DQSP0[11]
C C
B B
M_B_DQSN0[11]
M_B_DQSP3[11] M_B_DQSN3[11]
M_B_DQSP2[11] M_B_DQSN2[11]
M_B_DQSP1[11] M_B_DQSN1[11]
M_B_CAA0 M_B_CAA1 M_B_CAA2 M_B_CAA3 M_B_CAA4 M_B_CAA5 M_B_CAA6 M_B_CAA7 M_B_CAA8 M_B_CAA9
H9CCNNN BLTBLAR-NUD
R2
CA0
P2
CA1
N2
CA2
N3
CA3
M3
CA4
F3
CA5
E3
CA6
E2
CA7
D2
CA8
C2
CA9
J3
CK
J2
CK#
K3
CKE0
K4
CKE1
L3
CS#0
L4
CS#1
L8
DM0
G8
DM1
P8
DM2
D8
DM3/NC
A1
DNU1
A2
DNU2
A12
DNU3
A13
DNU4
B1
DNU5
B13
DNU6
T1
DNU7
T13
DNU8
U1
DNU9
U2
DNU10
U12
DNU11
U13
DNU12
L10
DQS0
L11
DQS0#
G10
DQS1
G11
DQS1#
P10
DQS2/NC
P11
DQS2#/NC
D10
DQS3/NC
D11
DQS3#/NC
B2
VSS1
B5
VSS2
C5
VSS3
E4
VSS4
E5
VSS5
F5
VSS6
H2
VSS7
J12
VSS8
K2
VSS9
L6
VSS10
M5
VSS11
N4
VSS12
N5
VSS13
R4
VSS14
R5
VSS15
T2
VSS16
T3
VSS17
T4
VSS18
T5
VSS19
C3
VSSCA1
D3
VSSCA2
F4
VSSCA3
G3
VSSCA4
G4
VSSCA5
J4
VSSCA6
M4
VSSCA7
P3
VSSCA8
B6
VSSQ1
B12
VSSQ2
C6
VSSQ3
D12
VSSQ4
E6
VSSQ5
F6
VSSQ6
F12
VSSQ7
G6
VSSQ8
G9
VSSQ9
H10
VSSQ10
K10
VSSQ11
L9
VSSQ12
M6
VSSQ13
M12
VSSQ14
N6
VSSQ15
P12
VSSQ16
R6
VSSQ17
T6
VSSQ18
T12
VSSQ19
TBL1601
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8
DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DQ16/NC DQ17/NC DQ18/NC DQ19/NC DQ20/NC DQ21/NC DQ22/NC DQ23/NC DQ24/NC DQ25/NC DQ26/NC DQ27/NC DQ28/NC DQ29/NC DQ30/NC DQ31/NC
VDD1_1 VDD1_3 VDD1_5 VDD1_7 VDD1_9 VDD1_2 VDD1_4 VDD1_6 VDD1_8
VDD1_10
VDD2_1 VDD2_2 VDD2_3 VDD2_4 VDD2_5 VDD2_6 VDD2_7 VDD2_8
VDD2_9 VDD2_10 VDD2_11 VDD2_12 VDD2_13 VDD2_14 VDD2_15 VDD2_16 VDD2_17 VDD2_18 VDD2_19 VDD2_20
VDDCA1 VDDCA2 VDDCA3 VDDCA4 VDDCA5
VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8
VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17
VREFCA
VREFDQ
ODT
ZQ0 ZQ1
NC1 NC2 NC3
P9 N9 N10 N11 M8 M9 M10 M11 F11 F10 F9 F8 E11 E10 E9 D9 T8 T9 T10 T11 R8 R9 R10 R11 C11 C10 C9 C8 B11 B10 B9 B8
A3 A4 A5 A6 A10 U3 U4 U5 U6 U10
A8 A9 D4 D5 D6 G5 H5 H6 H12 J5 J6 K5 K6 K12 L5 P4 P5 P6 U8 U9
F2 G2 H3 L2 M2
A11 C12 E8 E12 G12 H8 H9 H11 J9 J10 K8 K11 L12 N8 N12 R12 U11
H4 J11
J8
B3 B4
C4 K9 R3
M_B_D0 M_B_D1 M_B_D4 M_B_D3 M_B_D2 M_B_D6 M_B_D5 M_B_D7 M_B_D25 M_B_D29 M_B_D27 M_B_D26 M_B_D24 M_B_D28 M_B_D30 M_B_D31 M_B_D19 M_B_D23 M_B_D21 M_B_D16 M_B_D22 M_B_D18 M_B_D17 M_B_D20 M_B_D13 M_B_D15 M_B_D10 M_B_D11 M_B_D12 M_B_D8 M_B_D9 M_B_D14
V1P8U_2P5U V1P8U_2P5U
V1P2U
V1P2U
V1P2U
R17032 243
ZQ1701
R17034 2431%
ZQ1702
M_B_D[7:0] [11] M_B_D[55:48] [11]
M_B_D[31:24] [11]
M_B_DIM0_CLKP1[11,17] M_B_DIM0_CLKN 1[11,17]
M_B_D[23:16] [11]
M_B_D[15:8] [11]
V_VREF_CA_DIM M
0402
1%
0402 TBL1601
V_VREF_DQ_DIM M1
M_B_DIM0_CKE2[11,17] M_B_DIM0_CKE3[11,17]
M_B_DIM0_CS0_N[11,17] M_B_DIM0_CS1_N[11,17]
M_B_DQSP6[11] M_B_DQSN6[11]
M_B_DQSP5[11] M_B_DQSN5[11]
M_B_DQSP4[11] M_B_DQSN4[11]
M_B_DQSP7[11] M_B_DQSN7[11]
M_B_CAB0 M_B_CAB1 M_B_CAB2 M_B_CAB3 M_B_CAB4 M_B_CAB5 M_B_CAB6 M_B_CAB7 M_B_CAB8 M_B_CAB9
U17002 H9CCNNN BLTBLAR-NUD
R2
CA0
P2
CA1
N2
CA2
N3
CA3
M3
CA4
F3
CA5
E3
CA6
E2
CA7
D2
CA8
C2
CA9
J3
CK
J2
CK#
K3
CKE0
K4
CKE1
L3
CS#0
L4
CS#1
L8
DM0
G8
DM1
P8
DM2
D8
DM3/NC
A1
DNU1
A2
DNU2
A12
DNU3
A13
DNU4
B1
DNU5
B13
DNU6
T1
DNU7
T13
DNU8
U1
DNU9
U2
DNU10
U12
DNU11
U13
DNU12
L10
DQS0
L11
DQS0#
G10
DQS1
G11
DQS1#
P10
DQS2/NC
P11
DQS2#/NC
D10
DQS3/NC
D11
DQS3#/NC
B2
VSS1
B5
VSS2
C5
VSS3
E4
VSS4
E5
VSS5
F5
VSS6
H2
VSS7
J12
VSS8
K2
VSS9
L6
VSS10
M5
VSS11
N4
VSS12
N5
VSS13
R4
VSS14
R5
VSS15
T2
VSS16
T3
VSS17
T4
VSS18
T5
VSS19
C3
VSSCA1
D3
VSSCA2
F4
VSSCA3
G3
VSSCA4
G4
VSSCA5
J4
VSSCA6
M4
VSSCA7
P3
VSSCA8
B6
VSSQ1
B12
VSSQ2
C6
VSSQ3
D12
VSSQ4
E6
VSSQ5
F6
VSSQ6
F12
VSSQ7
G6
VSSQ8
G9
VSSQ9
H10
VSSQ10
K10
VSSQ11
L9
VSSQ12
M6
VSSQ13
M12
VSSQ14
N6
VSSQ15
P12
VSSQ16
R6
VSSQ17
T6
VSSQ18
T12
VSSQ19
TBL1601
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8
DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DQ16/NC DQ17/NC DQ18/NC DQ19/NC DQ20/NC DQ21/NC DQ22/NC DQ23/NC DQ24/NC DQ25/NC DQ26/NC DQ27/NC DQ28/NC DQ29/NC DQ30/NC DQ31/NC
VDD1_1 VDD1_3 VDD1_5 VDD1_7 VDD1_9 VDD1_2 VDD1_4 VDD1_6 VDD1_8
VDD1_10
VDD2_1 VDD2_2 VDD2_3 VDD2_4 VDD2_5 VDD2_6 VDD2_7 VDD2_8
VDD2_9 VDD2_10 VDD2_11 VDD2_12 VDD2_13 VDD2_14 VDD2_15 VDD2_16 VDD2_17 VDD2_18 VDD2_19 VDD2_20
VDDCA1 VDDCA2 VDDCA3 VDDCA4 VDDCA5
VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8
VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17
VREFCA
VREFDQ
ODT
ZQ0 ZQ1
NC1 NC2 NC3
P9 N9 N10 N11 M8 M9 M10 M11 F11 F10 F9 F8 E11 E10 E9 D9 T8 T9 T10 T11 R8 R9 R10 R11 C11 C10 C9 C8 B11 B10 B9 B8
A3 A4 A5 A6 A10 U3 U4 U5 U6 U10
A8 A9 D4 D5 D6 G5 H5 H6 H12 J5 J6 K5 K6 K12 L5 P4 P5 P6 U8 U9
F2 G2 H3 L2 M2
A11 C12 E8 E12 G12 H8 H9 H11 J9 J10 K8 K11 L12 N8 N12 R12 U11
H4 J11
J8
B3 B4
C4 K9 R3
ZQ1703 ZQ1704
V1P2U
V1P2U
V1P2U
M_B_DIM0_ODT0 [11,17]M_B_DIM0_ODT0 [11,17]
0402
R17033 2431% R17035 2431%
0402
TBL1601
M_B_D54 M_B_D53 M_B_D49 M_B_D48 M_B_D55 M_B_D52 M_B_D50 M_B_D51 M_B_D45 M_B_D47 M_B_D42 M_B_D46 M_B_D44 M_B_D43 M_B_D41 M_B_D40 M_B_D33 M_B_D32 M_B_D37 M_B_D36 M_B_D34 M_B_D38 M_B_D39 M_B_D35 M_B_D56 M_B_D59 M_B_D60 M_B_D62 M_B_D57 M_B_D58 M_B_D61 M_B_D63
V_VREF_CA_DIM M
M_B_D[47:40] [11]
M_B_D[39:32] [11]
M_B_D[63:56] [11]
V_VREF_DQ_DIM M1
V_VREF_CA_DIM M V_VREF_DQ_DIM M1
C17001 47000p
0201
6.3V
C17002 47000p
0201
6.3V
C17003 47000p
0201
6.3V
C17004 47000p
0201
6.3V
V0P6DX_LPDDR3
M_B_CAA[9:0][11,17]
M_B_CAB[9:0][11,17]
M_B_DIM0_CLKP0[11,17] M_B_DIM0_CLKN 0[11,17] M_B_DIM0_CLKP1[11,17] M_B_DIM0_CLKN 1[11,17]
M_B_CAA0 M_B_CAA1 M_B_CAA2 M_B_CAA3 M_B_CAA4 M_B_CAA5 M_B_CAA6 M_B_CAA7 M_B_CAA8 M_B_CAA9
M_B_CAB0 M_B_CAB1 M_B_CAB2 M_B_CAB3 M_B_CAB4 M_B_CAB5 M_B_CAB6 M_B_CAB7 M_B_CAB8 M_B_CAB9
M_B_DIM0_ODT0[11,17] M_B_DIM0_CS0_N[11,17] M_B_DIM0_CS1_N[11,17] M_B_DIM0_CKE0[11,17] M_B_DIM0_CKE1[11,17] M_B_DIM0_CKE2[11,17] M_B_DIM0_CKE3[11,17]
R17001 68 5% 0201 R17002 68 5% 0201 R17003 68 5% 0201 R17004 68 5% 0201 R17005 68 5% 0201 R17006 68 5% 0201 R17007 68 5% 0201 R17008 68 5% 0201 R17009 68 5% 0201 R17010 68 5% 0201
R17011 68 5% 0201 R17012 68 5% 0201 R17013 68 5% 0201 R17014 68 5% 0201 R17015 68 5% 0201 R17016 68 5% 0201 R17017 68 5% 0201 R17018 68 5% 0201 R17019 68 5% 0201 R17020 68 5% 0201
R17021 80.6 0201 R17022 80.6 0201 R17023 80.6 0201 R17024 80.6 0201 R17025 80.6 0201 R17026 80.6 0201 R17027 80.6 0201
R17028 37.4 0201 R17029 37.4 0201 R17030 37.4 0201 R17031 37.4 0201
DNP For 4GB System Memory: R17034, R17035
A A
17. LPDDR3(2)_M EMORY DOW N
17. LPDDR3(2)_M EMORY DOW N
17. LPDDR3(2)_M EMORY DOW N
Title:
Title:
Title:
Surface
Surface
1
Surface
1.0.0.1
1.0.0.1
17 79Thursday, April 26, 2018
17 79Thursday, April 26, 2018
17 79Thursday, April 26, 2018
1.0.0.1
Engineer:
Engineer:
Engineer:
A
A
A
Microsoft Conf idential
Microsoft Conf idential
Microsoft Conf idential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
C
C
5
4
3
2
U SPECIFIC
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
Vinafix.com
D D
XDP_BPM0[10] XDP_BPM1[10]
XDP_TP18001SMD RND 22.8mil XDP_TP18002SMD RND 22.8mil
4
XDP_PRESENT_N[18]
MTP18001 SMD RND 22.8mil
3
V3P3_DSW
R18021
100K
0201 DEBUG_OSG
DEBUG_OSG
U18007
1
NC
2 3 4
VCC
A GND
74LVC1G06GM
NC
Y
6 5
C18002
DEBUG_OSG
0.010u
0201
R18026
100K
0201 DEBUG_OSG
2
XDP_PRESENT_LOGIC [61]
1
C C
V1P00A
PRIMARY XDP connector
C18003
0.1u6.3V
0201
1.5K R18025
0201
P18001 TBD
36
GNDPAD
XDP_PRDY_N[24]
CFG18[15] CFG19[15] CFG15[15] CFG14[15] CFG13[15] CFG12[15] CFG11[15] CFG10[15] CFG9[15] CFG8[15]
For the signals only go to XDP, the 0R should be close to XDP connector. For the signals to both XDP and target circuit, the option resistor locaction should follow the target signal routing.
34
XDP_PRDYn
32
XDP_TCK0
30
XDP_TMS
28
XDP_TRSTn
26
HOOK[6]
24
XDP_PRS_PCH
22
VCCOBS_AB
20
OBS_CLK_2N
18
OBS_CLK_2P
16
OBSDATA_15
14
OBSDATA_14
12
OBSDATA_13
10
OBSDATA_12
8
OBSDATA_11
6
OBSDATA_10
4
OBSDATA_9
2
OBSDATA_8
XDP_TDO
XDP_PREQN
XDP_TCK1
XDP_TDI
HOOK[0] HOOK[3]
XDP_PRS_CPU
OBS_CLK_1N
OBS_CLK_1P
OBSDATA_7 OBSDATA_6 OBSDATA_5 OBSDATA_4 OBSDATA_3 OBSDATA_2 OBSDATA_1 OBSDATA_0
35 33 31 29 27 25 23 21 19
GND
17 15 13 11 9 7 5 3 1
CMC Merged Adapter Gen1
B B
PROC_TCK[10] PROC_TMS[10]
PROC_TRST_N[10]
ITP_PMODE[15]
XDP_PRESENT_N[18]
XDP_SPI0_IO2[21]
A A
R18018 1K 0201
V1P00A
DEBUG_OSG
C18004
47uDEBUG_OSG
V1P00A
DNP
0201
PM_RSMRST_PWRGD_XDP
R18019 1.5K
CFG17 [15] CFG7 [15] CFG6 [15] CFG5 [15] CFG4 [15]
CFG2 [15] CFG1 [15] CFG0 [15]
49.9
R18005
0201
CFG16 [15]
CFG3 [15]
PROC_TDO [10]
XDP_PREQ_N [24]
PCH_JTAG_TCK [10]
PROC_TDI [10]
1.5K
R18024
0201
V3P3_DSW
MTP18002 SMD RND 22.8mil
R18015 1K
0201
SAM_PCH_RSMRST_N [22,29,56]
SPI0_MOSI_XDP [21]
C18001
0.1u6.3V
0201
18. XDP
18. XDP
Title:
Title:
Microsoft Confidential
Microsoft Confidential
Microsoft Confidential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
B
B
B
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
A
A
A
Title:
Engineer:
Engineer:
Engineer:
18. XDP
Surface
Surface
Surface
1
1.0.0.1
1.0.0.1
1.0.0.1
18 79Thursday, April 26, 2018
18 79Thursday, April 26, 2018
18 79Thursday, April 26, 2018
5
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4
3
2
1
D D
LPDDR3 Vref
M3: CPU driven VREF path is stuffed by default. M1: VREF_DQ driven by a Voltage Divider Network during Processor power-off
V1P2U
R19001
8.2K
0402
DIMM0_VREF_DQ[11] DIMM_VREF_CA [11]
C C
R19003 10
C19001
0.022u 16V
0201
24.9
0402
0201
R19005
8.2K
0201
V_VREF_DQ_DIMM0
V_VREF_CA_DIMM
V1P2U
R19006
8.2K
0201R19007
R19002
8.2K
0201
0201
R19004 5.1
C19002
0.022u 16V
0201
DIMM_VREF_CA_CDIMM0_VREF_DQ_C
R19008
24.9
0402
V1P2U
R19010
8.2K
0201
0402
DIMM1_VREF_DQ[11]
B B
N1902
R19011 10
C19003
0.022u 16V
0201
R19012
8.2K
0201
R19013
24.9
0402
V_VREF_DQ_DIMM1
Intel 0203 M3+M1: Default Recommendation
A A
19. LPDDR3(3)_CA/DQ Voltage
19. LPDDR3(3)_CA/DQ Voltage
19. LPDDR3(3)_CA/DQ Voltage
Surface
Surface
Surface
19 79Thursday, April 26, 2018
19 79Thursday, April 26, 2018
1
19 79Thursday, April 26, 2018
1.0.0.1
1.0.0.1
1.0.0.1
Title:
Title:
Microsoft Confidential
Microsoft Confidential
Microsoft Confidential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
B
B
B
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
A
A
A
Title:
Engineer:
Engineer:
Engineer:
5
[20,27]
Vinafix.com
4
3
2
1
1P8V_SSD
0201
R20032
10K
D D
SSD_PCIECLK_REQ_N[43]
PCIECLK_SSD_DN[43] PCIECLK_SSD_DP[43]
C C
SSD2_PCIECLK_REQ_N[44]
PCIECLK_SSD2_DN[44]
PCIECLK_SSD2_DP[44]
PCIE_WIFI_RCLK_DN[50]
PCIE_WIFI_RCLK_DP[50]
PCIE_WIFI_CLKREQ_N[50]
B B
A A
AZ_SYNC_1[40] AZ_BITCLK_1[40] AZ_SDATA_OUT_1[40] AZ_SDATA_IN0[40]
FLASH_PROTECT_N[49] CAM_F_XO_EN[25,54]
AZ_SDATA_IN0
HDA_RST_N_R
HDA_SDO_R
Need to place as close to SOC pins as possible
C20011
2p
25V 0201
5
DNP
1P8V_SSD2
10K
0201
DNP
R20033
1
C20012
2p
25V 0201
2
Q20001A NX3008NBKS
G
DNP
0201
S
SSD
DMIC_CLK[40,54] DMIC_DATA[40,54]
MTP20001SMD RND 22.8mil
MTP20002SMD RND 22.8mil
MTP20003SMD RND 22.8mil
D
5
Q20001B NX3008NBKS
G
DNP
0201
C20013
2p
25V 0201
S
R20030 0
SSD
4
R20031 0
6
3
D
3P3V_SSD
R20002
CLKREQ1_N
3P3V_SSD
R20021
CLKREQ4_N
0201 0201
0201
R20014 33 R20011 33 R20012 33
10K
10K
0201
0201
U10001J
D42
CLKOUT_PCIE_N0
C42
CLKOUT_PCIE_P0
AR10
GPP_B5/SRCCLKREQ0#
B42
CLKOUT_PCIE_N1
A42
CLKOUT_PCIE_P1
AT7
GPP_B6/SRCCLKREQ1#
D41
CLKOUT_PCIE_N2
C41
CLKOUT_PCIE_P2
AT8
GPP_B7/SRCCLKREQ2#
D40
CLKOUT_PCIE_N3
C40
CLKOUT_PCIE_P3
AT10
GPP_B8/SRCCLKREQ3#
B40
CLKOUT_PCIE_N4
A40
CLKOUT_PCIE_P4
AU8
GPP_B9/SRCCLKREQ4#
E40
CLKOUT_PCIE_N5
E38
CLKOUT_PCIE_P5
AU7
GPP_B10/SRCCLKREQ5#
KBL-R U42
<$LOCATION> <MATERIAL> 10 OF 20 REV = 1
HDA_SYNC_R HDA_BCLK_R
INT. PD
HDA_RST_N_R
SAM_UEFI_TOP_SWAP[27]
4
HDA_SDO_R
was HDA_SDI0_R
R20019 100K
0201
KBL_R_U42
CLOCK SIGNALS
BA22 AY22 BB22 BA21 AY21
AW22
AY20
AW20
AK7 AK6 AK9
AK10
AW5
U10001G
AUDIO
HDA_SYNC/I2S0_SFRM HDA_BLK/I2S0_SCLK HDA_SDO/I2S0_TXD HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD HDA_RST#/I2S1_SCLK
J5
GPP_D23/I2S_MCLK I2S1_SFRM I2S1_TXD
GPP_F1/I2S2_SFRM GPP_F0/I2S2_SCLK GPP_F2/I2S2_TXD GPP_F3/I2S2_RXD
H5
GPP_D19/DMIC_CLK0
D7
GPP_D20/DMIC_DATA0
D8
GPP_D17/DMIC_CLK1
C8
GPP_D18/DMIC_DATA1
GPP_B14/SPKR
KBL-R U42
<$LOCATION> <MATERIAL> 7 OF 20 REV = 1
CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P
GPD8/SUSCLK
NC_2 NC_1
XCLK_BIASREF
RTCX1 RTCX2
SRTCRST#
RTCRST#
3
Do not place XDP_TP20001 and XDP_TP20002 under SOC heat sync
F43 E43
BA17
E37 E35
E42
AM18 AM20
AN18 AM16
HDA_SDO:
1.Flash descriptor security: Sampled Low: in effect. Sampled High: override
2.HDA_SDOwhich sample high on the rising edge of PWROK Will also disable Intel ME.
KBL_R_U42
CLK_XDP_DN CLK_XDP_DP
XCLK_BIASREF
RTC_X1 RTC_X2
SRTC_RST_N [20] SKL_RTCRST_N [20,27]
SDIO/SDXC
GPP_A17/SD_PWR_EN#/ISH_GP7
U SPECIFIC
XDP_TP20001 XDP_TP20002
R20007 0
C20003 22p 25V 5%
0201
GPP_G0/SD_CMD GPP_G1/SD_DATA0 GPP_G2/SD_DATA1 GPP_G3/SD_DATA2 GPP_G4/SD_DATA3
GPP_G5/SD_CD# GPP_G6/SD_CLK
GPP_G7/SD_WP
GPP_A16/SD_1P8_SEL
SD_RCOMP
GPP_F23
2
SMD RND 22.8mil SMD RND 22.8mil
R20006 10M
0201
CTAL_1
0201
No SD support
AB11 AB13 AB12 W12 W11 W10 W8 W7
BA9 BB9
SD_RCOMP
AB7
AF13
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Microsoft Confidential
Microsoft Confidential
Microsoft Confidential
21
Y20002
32.7 KHz
3.2X1.5X0.9MM
SDRAM_SOC_ID0 [23] SDRAM_SOC_ID1 [23] SDRAM_SOC_ID2 [23] SDRAM_SOC_ID3 [23] SSD_SOC_ID0 [23] SSD_SOC_ID1 [23] CPU_SOC_ID0 [23] CPU_SOC_ID1 [23]
B
B
B
A
A
A
VCCCLK5_R
R20005 2.7K1%
1
0402
C20005
6.3V
1u
0402
C20006
6.3V
1u
0402
Surface
Surface
Surface
20 79Friday, April 27, 2018
20 79Friday, April 27, 2018
20 79Friday, April 27, 2018
SRTC_RST_N [20]
SKL_RTCRST_N
R20017 200
0201
PDG says to use 2.71K 0.5% resistor. the power rail connector to the rail of VCCCLK5. Confirmed with Intel OK to use 2.71K 1% resistor.
C20004 22p 25V 5%
0201
VCC_RTC
R20009 20K
0201
R20015 20K
0201
PCH_PMI_SLOW [25]
PCH_AUD_1V8_EN [25,62]
20. PCH(1)_SD,HDA,RTC, CLK
20. PCH(1)_SD,HDA,RTC, CLK
Title:
Title:
Title:
Engineer:
Engineer:
Engineer:
20. PCH(1)_SD,HDA,RTC, CLK
1.0.0.1
1.0.0.1
1.0.0.1
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Vinafix.com
Connected to device. Default : Clock free run. (PD 10K).
D D
XDP_SPI0_IO2[18]
SPI0_MOSI_XDP[18]
Reserver 10K PU for power saving purpose.
4
3
2
1
R21007
1K
Close to PCH
SPI_CLK[37] SPI_SO[37] SPI_SI[37] SPI_WP_IO2[37]
SPI_HOLD_IO3_N[37]
SPI_CS0_N[37]
C C
TS_SPI_CLK[49]
TS_SPI_MISO[49]
TS_SPI_MOSI[49]
TS_SPI_CS_N[49]
B B
R21011 15 0201 R21012 15 0201 R21013 15 0201 R21009 15 0201 R21010 15 0201 R21023 15 0201
R21014 15 R21015 15 R21016 15
R21019 15
TPM_SERIRQ[38]
SPI_CLK_R SPI_SO_R SPI_SI_R SPI_WP_IO2_R SPI_HOLD_IO3_R_N
0201 0201 0201
0201
3VSUS_ORG
R21029 10K
1%
0201
Serial Interrupt Request
0201
TS_SPI_CLK_R TS_SPI_MISO_R TS_SPI_MOSI_R
TS_SPI_CS_N_R
R21008 1K
0201
AV2
AW3
AV3
AW2
AU4 AU3 AU2 AU1
M2 M3
J4 V1 V2
M1
G3 G2 G1
AW13
AY11
U10001E
SPI - FLASH
SPI0_CLK SPI0_MISO SPI0_MOSI SPI0_IO2 SPI0_IO3 SPI0_CS0# SPI0_CS1# SPI0_CS2#
SPI_TOUCH
GPP_D1/SPI1_CLK GPP_D2/SPI1_MISO GPP_D3/SPI1_MOSI GPP_D21/SPI1_IO2 GPP_D22/SPI1_IO3 GPP_D0/SPI1_CS#
C LINK
CL_CLK CL_DATA CL_RST#
GPP_A0/RCIN#
GPP_A6/SERIRQ
KBL-R U42
<$LOCATION> <MATERIAL> 5 OF 20 REV = 1
KBL_R_U42
LPC
SMBUS, SMLINK
1
GPP_B23/SML1ALERT#/PCHHOT#
GPP_A5/LFRAME#/ESPI_CS#
GPP_A14/SUS_STAT#/ESPI_RESET#
GPP_A9/CLKOUT_LPC0/ESPI_CLK
GPP_C0/SMBCLK
GPP_C1/SMBDATA
GPP_C2/SMBALERT#
GPP_C3/SML0CLK
GPP_C4/SML0DATA
GPP_C5/SML0ALERT#
GPP_C6/SML1CLK
GPP_C7/SML1DATA
GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3
GPP_A10/CLKOUT_LPC1
GPP_A8/CLKRUN#
R7 R8
INT. PD
R10
R9 W2
INT. PD
W1
GPP_C5 - LPC boot mode selection - needs to be 0
W3 V3
INT. PD
AM7
AY13 BA13 BB13 AY12 BA12 BA11
AW9 AY9 AW11
0201
was SMB0ALERT#
0201
R21024 49.9
R21027 49.9
0201
0201
R21025 49.9
R21026 49.9
TPM_LPC0 [38] TPM_LPC1 [38] TPM_LPC2 [38] TPM_LPC3 [38] TPM_LFRAME [38]
CK_24M_EC_R
R21020 22
3VSUS_ORG
R21021
8.2K
0201
TPM_CLKRUN [38]
0201
R21004 10K
1%
0201
GTP21013
R21031 100K
1% 0201
TPM_DEEPSLP_N [38]
TPM_CLK [38]
C21002
50V
10p
0201 DNP
SMD RND 22.8mil
GPP_C2/SMBALERT#
LAD1_SKL_TERM
0 Disable ME crypto TLS
Default
1
Enable ME crypto TLS
Needs to be left open or low for booting
A A
LAD0_SKL_TERM
25V
25V
C21006 56p
C21003 56p
0201
0201
Need into improve LPC signals -
P had in their latest design
0201
U SPECIFIC
5
4
3
LAD2_SKL_TERM
C21004 56p
25V
0201
LAD3_SKL_TERM
25V
C21005 56p
21. PCH(2)_CLK,SMB,LPC, SPI
21. PCH(2)_CLK,SMB,LPC, SPI
Title:
Title:
Title:
Microsoft Confidential
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Microsoft Confidential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
B
B
B
Date: Sheet of
Date: Sheet of
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Date: Sheet of
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Engineer:
Engineer:
Engineer:
21. PCH(2)_CLK,SMB,LPC, SPI
Surface
Surface
Surface
21 79Friday, April 27, 2018
21 79Friday, April 27, 2018
1
21 79Friday, April 27, 2018
1.0.0.1
1.0.0.1
1.0.0.1
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D D
3VSUS_ORG
C22001 0.1u
MTTP22014
SMD RND 22.8mil
PLT_RST_BUF_N[27,34,38,43,44,56]
V1P00A
SKL_VCCST_PWRGD[34,59]
C C
PCH_DPWROK
SAM_PCH_RSMRST_N[18,29,56]
SKL_SYS_PWROK[34,59]
SN74AUP1G08DRYR
1 2 3 4
V3P3_DSW
6.3V
0201
R22001
49.9K
0201
R22005 60.4
0402
U22002
A
VCC
B
GND
NC
Y
R22024 10K
R22013 100
0201
U22001 SN74AUP1G08DRYR
6
VCC
5
NC
Y
MTTP22010
SMD RND 22.8mil
R22029 1K
3P3VA
6 5
R22009 49.9
0201
6.3V
DNP
0201
0201 DNP
A B
GND
0201
0201
C220120.1u
1 2 34
R220200DNP
0201
4
C22002
100p
0201
3VSUS_ORG
MTTP22004
C22003
470p
0201
R22006 10K
0201
SMD RND 22.8mil
SMD RND 22.8mil
MTTP22011
PCH_SYS_RST_N
PM_RSMRST_R
PROCPWRGD
VCCST_PWRG D_R
SYS_PWROK_R
V3P3_VCCDSW
R22011 20K
R22025
49.9K
0201
WAKE_N
0201
V3P3_DSW
R22043 10K
0201 DNP
AN10
AY17
BA20 BB20
AR13 AP11
BB15
AM15
AW17
AT15
3
U10001K
SYSTEM POWER MANAGEMENT
GPP_B13/PLTRST#
B5
SYS_RESET# RSMRST#
A68
PROCPWRGD
B65
VCCST_PWRGD
B6
SYS_PWROK PCH_PWROK DSW_PWROK
GPP_A13/SUSWARN#/SUSPWRDNACK GPP_A15/SUSACK#
WAKE# GPD2/LAN_WAKE# GPD11/LANPHYPC GPD7/RSVD
KBL-R U42
<$LOCATION> <MATERIAL> 11 OF 20 REV = 1
KBL_R_U42
SMD RND 22.8mil
GPP_B12/SLP_S0#
GPD9/SLP_WLAN#
GPD3/PWRBTN#
GPD1/ACPRESENT
GPP_B11/EXT_PWR_GATE#
GPP_B2/VRALERT#
MTTP22003
GPD4/SLP_S3# GPD5/SLP_S4#
GPD10/SLP_S5#
SLP_SUS#
SLP_LAN#
GPD6/SLP_A#
GPD0/BATLOW#
GPP_A11/PME#
INTRUDER#
C22007 180p
25V
0201
AT11 AP15 BA16 AY16
AN15 AW15 BB17 AN16
BA15 AY15 AU13
AU11 AP16
AM10 AM11
2
AC_PRESENT_R BATLOW_R_N
PME_N INTRUDER_N
VRALERT_R_N
R22033
0 0201
R22035
22 0201
SMD RND 22.8mil
MTTP22008
V3P3_DSW
C22004
0.01u
10V
0201
R22034
33 0201
R22036
33 0201
R22008 1M
R22012 10K
0201R22014 100K
for VR hot indicator (may not be used)
SKL_SLP_S0_N [27,31,34,38,59,61] SKL_SLP_S3_N [34,59,61] SKL_SLP_S4_N [27,34,45,59,61]
SKL_SLP_SUS_N [27,34,58,59]
PCH_PWRBTN_N [34,59]
0201
VCC_RTC
C22005 100p
25V
0201
1
C22006 150p
25V
0201
3VSUS_ORG
0201
R22027 100K
0201
R22004
R22010 10K
0201
V3P3_VCCDSW
10K
PM_PCH_PWROK[22]
V3P3_DSW
R22026 10K
0201 DNP
PCH_DPWROK[27,34,56,59]
V3P3_VCCDSW
B B
R22044 10K
0201
If SUSWARN #/SUS_ACK # handshake
SUSWARN_N
A A
is not used, these signals are tied on the board
R22018 22
0201
V3P3_VCCDSW
R22019 10K
0201
R22022
R22021
56p
25V
SUSACK_N
DNP
100K0201
V3P3_DSW
R22031 100K
PMIC_SAM_ALL_SYS_PWRGD[29,34,59]
0201
R22038
SKL_PCH_PWROK[34,59]
R22040
VRM_PWRGD[66]
R22042
1000201
1000201
C22009 2200p 25V
0201
D22002
1000201
100 0201
C22010 2200p 25V
0201
C22008 2200p 25V
0201
AK
RB520CS3002L
R22041
D22003
AK
RB520CS3002L
C22011
6.3V
0.1u
0201 DNP
V3P3_DSW
R22037 10K
0201
PM_PCH_PWROK [22]
VRM_PWR_EN [29,66]
22. PCH(3)_SYS PWR CONTR
22. PCH(3)_SYS PWR CONTR
Title:
Title:
Title:
Microsoft Confidential
Microsoft Confidential
Microsoft Confidential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
A3
A3
U SPECIFIC
5
4
3
2
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
A
A
A
Engineer:
Engineer:
Engineer:
22. PCH(3)_SYS PWR CONTR
Surface
Surface
Surface
22 79Tuesday, May 01, 2018
22 79Tuesday, May 01, 2018
1
22 79Tuesday, May 01, 2018
1.0.0.1
1.0.0.1
1.0.0.1
5
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4
3
2
1
TBL2301B
LOAD FOR DEBUG, ELSE NO-STUFFR23016, R28013
R23023, R28024
TBL2301A
D D
R23015, R28014 NEW BOARDID SYSTEM, ELSE NO-STUFF
R23022, R28025 OLD BOARDID SYSTEM, ELSE NO-STUFF
LOAD FOR RETAIL, ELSE NO-STUFF
TBL_SSD_2302
TBL2304
C C
TBL1601
TBL2301 PCBA vendor and revision
R23010, R23020, R23024
R23005, R23013, R23017, R28051, R28052, R28053
R23005, R23020, R23024, R28051
R23010, R23013, R23017, R28052, R28053
R23010, R23013, R23024, R28052
R23005, R23020, R23017, R28051, R28053
R23005, R23013, R23024, R28051, R28052
R23010, R23020, R23017, R28053
R23010, R23020, R23017, R28053
R23005, R23013, R23024, R28051, R28052
R23005, R23020, R23017, R28051, R28053
R23010, R23013, R23024, R28052
R23010, R23013, R23017, R28052, R28053
R23005, R23020, R23024, R28051
R23005, R23013, R23017, R28051, R28052, R28053
Revision EV2P5
NO-STUFF FOR REVISION
Revision EV2P51
NO-STUFF FOR REVISION
Revision DV
NO-STUFF FOR REVISION
Revision DV1.01
NO-STUFF FOR REVISION
Revision DV1.1, DV1.2, PV
NO-STUFF FOR REVISION
Lacey EV1
NO-STUFF FOR REVISION
Reserved
NO-STUFF FOR REVISION
Reserved
NO-STUFF FOR REVISIONR23010, R23020, R23024
CPU_SOC_ID1[20] CPU_SOC_ID2[23]
SDRAM_SOC_ID0[20] SDRAM_SOC_ID1[20] SDRAM_SOC_ID2[20] SDRAM_SOC_ID3[20]
See TBL1601
TBL1001
R23041 10K
0201
TBL1001
R23043 10K
0201
TBL1601
R23051 10K
0201
TBL1601
R23050 10K
0201
TBL1001
R23045 10K
0201
V3P3_DSW
TBL1601
R23053 10K
0201
TBL1601
R23052 10K
0201
SSD_SOC_ID0[20]CPU_SOC_ID0[20] SSD_SOC_ID1[20]
TBL1601
R23055 10K
0201
TBL1601
R23054 10K
0201
SSD
R23031 10K
0201
TBL1601
R23057 10K
0201
TBL1601
R23056 10K
0201
SSD
R23033 10K
0201
V3P3_DSWV1P8AV3P3_DSW
TBL2304
10K
0201
TBL2304
R23009 10K
0201
TBL1001
R23042 10K
0201
V1P8A
TBL2301
R23005 10K
0201
TBL2301A
R23015 10K
0201
TBL2301A
R23022 10K
0201
TBL2301
R23010 10K
0201
TBL1001
R23040
TBL2304
R23003 10K
0201
TBL2304
R23008 10K
0201
TBL2301B
R23016 10K
0201
TBL2301B
R23023 10K
0201
10K
0201
See TBL1001
C23001
10u
6.3V 0402 R23004
MISC_SOC_ID bits are "RESERVED" in PM
B B
U10001I
CSI-2
A36
CSI2_DN0
B36
CSI2_DP0
C38
CSI2_DN1
D38
CSI2_DP1
C36
CSI2_DN2
D36
CSI2_DP2
A38
CSI2_DN3
B38
CSI2_DP3
CSI2_FCAM4_DN[54] CSI2_FCAM4_DP[54]
CSI2_IRCAM8_DN[54] CSI2_IRCAM8_DP[54]
A A
C31 D31 C33 D33
A31 B31 A33 B33
A29
B29 C28 D28
A27
B27 C27 D27
KBL-R U42
<$LOCATION> <MATERIAL> 9 OF 20 REV = 1
CSI2_DN4 CSI2_DP4 CSI2_DN5 CSI2_DP5 CSI2_DN6 CSI2_DP6 CSI2_DN7 CSI2_DP7
CSI2_DN8 CSI2_DP8 CSI2_DN9 CSI2_DP9 CSI2_DN10 CSI2_DP10 CSI2_DN11 CSI2_DP11
KBL_R_U42
CSI2_CLKN0 CSI2_CLKP0 CSI2_CLKN1 CSI2_CLKP1 CSI2_CLKN2 CSI2_CLKP2 CSI2_CLKN3 CSI2_CLKP3
CSI2_COMP
GPP_D4/FLASHTRIG
EMMC
GPP_F13/EMMC_DATA0 GPP_F14/EMMC_DATA1 GPP_F15/EMMC_DATA2 GPP_F16/EMMC_DATA3 GPP_F17/EMMC_DATA4 GPP_F18/EMMC_DATA5 GPP_F19/EMMC_DATA6 GPP_F20/EMMC_DATA7
GPP_F21/EMMC_RCLK
GPP_F22/EMMC_CLK
GPP_F12/EMMC_CMD
EMMC_RCOMP
C37 D37 C32 D32 C29 D29 B26 A26
E13 B7
AP2 AP1 AP3 AN3 AN1 AN2 AM4 AM1
AM2 AM3 AP4
AT1
CSI2_CLK1_FCAM_DN [54] CSI2_CLK1_FCAM_DP [54]
CSI2_CLK2_IRCAM_DN [54] CSI2_CLK2_IRCAM_DP [54]
R23011
CSI2_COMP
MISC_SOC_ID0 PWRMON_ID0 GP_SOC_ID0 GP_SOC_ID1 PCBA_SOC_ID0 PCBA_SOC_ID1 PCBA_SOC_ID1 PCBA_SOC_ID2 PCBA_SOC_ID2 DEBUG_RETAIL_SOC_ID DEBUG_RETAIL_SOC_ID
NEW_SOC_ID NEW_SOC_ID
EMMC_RCOMP_R
100 0201
CPU_SOC_ID2 [23]
R23018 200
0201 1%
PWRMON_ID0 bit is noted in "DEBUG_OSG" in PM
MISC_SOC_ID0 PWRMON_ID0 GP_SOC_ID0 GP_SOC_ID1 PCBA_SOC_ID0
TBL2303
R23001 10K
0201
TBL2301
R23013 10K
0201
TBL2301
R23020 10K
0201
TBL2303
R23006 10K
0201
R23002 10K
0201
DNP
R23007 10K
0201
TBL2301
R23017 10K
0201
TBL2301
R23024 10K
0201
U SPECIFIC
5
4
3
2
TBL1001
R23044 10K
0201
POWER MONITORS
V1P8A
Microsoft Confidential
Microsoft Confidential
Microsoft Confidential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
DV HAS NO POWER MONITORS
Title:
Title:
Title:
Engineer:
Engineer:
Engineer:
A
A
A
POWER MONITORS, ELSE NO-STUFFR23007
NO POWER MONITORS, ELSE NO-STUFFR23002
SSD
R23030 10K
0201
23. PCH(4)_CCI, HWID
23. PCH(4)_CCI, HWID
23. PCH(4)_CCI, HWID
1
SSD
R23032 10K
0201
Surface
Surface
Surface
23 79Friday, April 27, 2018
23 79Friday, April 27, 2018
23 79Friday, April 27, 2018
1.0.0.1
1.0.0.1
1.0.0.1
5
Vinafix.com
4
3
2
1
U10001H
D D
C C
PCIE_SSD_RX7_DN[43] PCIE_SSD_RX7_DP[43]
PCIE SSD1
PCIE WIFI
3VSUS_ORG
B B
PCIE SSD2
PCIE_SSD_TX7_DN[43] PCIE_SSD_TX7_DP[43]
PCIE_SSD_RX8_DN[43] PCIE_SSD_RX8_DP[43] PCIE_SSD_TX8_DN[43] PCIE_SSD_TX8_DP[43]
PCIE_WIFI_RX9_DN[50] PCIE_WIFI_RX9_DP[50] PCIE_WIFI_TX9_DN[50] PCIE_WIFI_TX9_DP[50]
R24009 10K
1%
0201
PCIE_SSD2_RX11_DN[44] PCIE_SSD2_RX11_DP[44] PCIE_SSD2_TX11_DN[44] PCIE_SSD2_TX11_DP[44] PCIE_SSD2_RX12_DN[44] PCIE_SSD2_RX12_DP[44] PCIE_SSD2_TX12_DN[44] PCIE_SSD2_TX12_DP[44]
XDP_PRDY_N[18]
XDP_PREQ_N[18]
C24003 0.22u
C24005 0.22u
C24007 0.1u 6.3V 0201
0.22u 0201 6.3V C24020
0.22u 0201 6.3V C24022
6.3V0201SSD
6.3V0201SSD
R24006 100
0201
SSD
0.22u 0201 6.3V
0.22u 0201 6.3V
SSD
C24004
C24006
C24008 0.1u
SSD
SSD
PIRQA_N
SSD
SSD
0.22u
6.3V0201
0.22u
6.3V0201
6.3V0201
PCIE_RCOMPN PCIE_RCOMPP
C24021
C24023
BB11
PCIE/USB3/SATA
H13
PCIE1_RXN/USB3_5_RXN
G13
PCIE1_RXP/USB3_5_RXP
B17
PCIE1_TXN/USB3_5_TXN
A17
PCIE1_TXP/USB3_5_TXP
G11
PCIE2_RXN/USB3_6_RXN
F11
PCIE2_RXP/USB3_6_RXP
D16
PCIE2_TXN/USB3_6_TXN
C16
PCIE2_TXP/USB3_6_TXP
H16
PCIE3_RXN
G16
PCIE3_RXP
D17
PCIE3_TXN
C17
PCIE3_TXP
G15
PCIE4_RXN
F15
PCIE4_RXP
B19
PCIE4_TXN
A19
PCIE4_TXP
F16
PCIE5_RXN
E16
PCIE5_RXP
C19
PCIE5_TXN
D19
PCIE5_TXP
G18
PCIE6_RXN
F18
PCIE6_RXP
D20
PCIE6_TXN
C20
PCIE6_TXP
F20
PCIE7_RXN/SATA0_RXN
E20
PCIE7_RXP/SATA0_RXP
B21
PCIE7_TXN/SATA0_TXN
A21
PCIE7_TXP/SATA0_TXP
G21
PCIE8_RXN/SATA1A_RXN
F21
PCIE8_RXP/SATA1A_RXP
D21
PCIE8_TXN/SATA1A_TXN
C21
PCIE8_TXP/SATA1A_TXP
E22
PCIE9_RXN
E23
PCIE9_RXP
B23
PCIE9_TXN
A23
PCIE9_TXP
F25
PCIE10_RXN
E25
PCIE10_RXP
D23
PCIE10_TXN
C23
PCIE10_TXP
F5
PCIE_RCOMP_N
E5
PCIE_RCOMP_P
D56
PROC_PRDY#
D61
PROC_PREQ# GPP_A7/PIRQA#
E28
PCIE11_RXN/SATA1B_RXN
E27
PCIE11_RXP/SATA1B_RXP
D24
PCIE11_TXN/SATA1B_TXN
C24
PCIE11_TXP/SATA1B_TXP
E30
PCIE12_RXN/SATA2_RXN
F30
PCIE12_RXP/SATA2_RXP
A25
PCIE12_TXN/SATA2_TXN
B25
PCIE12_TXP/SATA2_TXP
KBL_R_U42
SSIC / USB3
USB3_1_RXN USB3_1_RXP USB3_1_TXN USB3_1_TXP
USB3_2_RXN/SSIC_RXN USB3_2_RXP/SSIC_RXP
USB3_2_TXN/SSIC_TXN USB3_2_TXP/SSIC_TXP
USB3_3_RXN USB3_3_RXP USB3_3_TXN USB3_3_TXP
USB3_4_RXN USB3_4_RXP USB3_4_TXN USB3_4_TXP
USB2
USB2_COMP
USB2_VBUSSENSE
GPP_E9/USB2_OC0# GPP_E10/USB2_OC1# GPP_E11/USB2_OC2# GPP_E12/USB2_OC3#
GPP_E4/DEVSLP0 GPP_E5/DEVSLP1 GPP_E6/DEVSLP2
GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2
GPP_E8/SATALED#
USB2N_1 USB2P_1
USB2N_2 USB2P_2
USB2N_3 USB2P_3
USB2N_4 USB2P_4
USB2N_5 USB2P_5
USB2N_6 USB2P_6
USB2N_7 USB2P_7
USB2N_8 USB2P_8
USB2N_9 USB2P_9
USB2N_10
USB2P_10
USB2_ID
H8 G8 C13 D13
J6 H6 B13 A13
J10 H10 B15 A15
E10 F10 C15 D15
AB9 AB10
AD6 AD7
AH3 AJ3
AD9 AD10
AJ1 AJ2
AF6 AF7
AH1 AH2
AF8 AF9
AG1 AG2
AH7 AH8
AB6 AG3 AG4
A9 C9 D9 B9
J1 J2 J3
H2 H3 G4
H1
USB2_COMP
USB3_TYPEA_RX_DN [45] USB3_TYPEA_RX_DP [45] USB3_TYPEA_TX_DN [45] USB3_TYPEA_TX_DP [45]
USB3_SL_RX_DN [47] USB3_SL_RX_DP [47] USB3_SL_TX_DN [47] USB3_SL_TX_DP [47]
C24031 10p
0201
USB2_BT_DN [50] USB2_BT_DP [50]
GND
C24032 10p
0201
R24004 1130201
C24030 10p0201
USB Type A
USB3 SL1
USB2_TYPEA_DN [45] USB2_TYPEA_DP [45]
USB2_SL_DN [47] USB2_SL_DP [47]
BT
R24005 10K
0201
USB Type A
USB2 SL1
3VSUS_ORG
USB_CONN_OC_N [45]
KBL-R U42
<$LOCATION> <MATERIAL> 8 OF 20 REV = 1
SSD2_SATA_PCIE_DET_N [44]
A A
24. PCH(5)_PCIE,USB
24. PCH(5)_PCIE,USB
Title:
Title:
Title:
Microsoft Confidential
Microsoft Confidential
Microsoft Confidential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
A3
A3
U SPECIFIC
5
4
3
2
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
A
A
A
Engineer:
Engineer:
Engineer:
24. PCH(5)_PCIE,USB
Surface
Surface
Surface
24 79Friday, April 27, 2018
24 79Friday, April 27, 2018
1
24 79Friday, April 27, 2018
1.0.0.1
1.0.0.1
1.0.0.1
5
Vinafix.com
SAM_PCH_INT0[25,29]
R25059 100K
0201
No reboot strap Low: Disable (Default) High:Enable
D D
3VSUS_ORG
SAM_PCH_UART_TX[27,31]
SAM_PCH_UART_RX[27,31] BOOT_TO_USB[32] BOOT_TO_UEFI[32]
PCH_SSD_UART2_RXD[43]
PCH_SSD_UART2_TXD[43]
I2C_SDA_TP[31,48]
I2C_SCL_TP[31,48]
C C
B B
I2C_SDA_CAM[54] I2C_SCL_CAM[54]
I2C_SDA_BKLT[72]
I2C_SCL_BKLT[72]
GTP25030
SMD RND 22.8mil
GTP25031
SMD RND 22.8mil
I2C_SDA_ALS[54]
I2C_SCL_ALS[54]
DNP
R25001 1K
0201
R25077 0
Pull up resistors, pg 48
SL_CONN[25,27] 5V_USB_EN[45]
KPTP_FAULT_N[48] SAM_PCH_INT1[25,27]
R25078 0 0201
0201
R25007 49.9 R25008 49.9
R25085 00201 DNP R25086 00201 DNP
SKL_NO_REBOOT
R250830 0201SSD R250840 0201SSD
SAM_PCH_T1_PWRBTN_N[25,27]
DNP
PCH_AUD_5V_EN[25,64]
0201 0201
3P3V_SSD 3P3V_SSD
R25060 100K
0201 DNP
I2C_SDA_CAM_R I2C_SCL_CAM_R
2K
0201
R25014
1P8VSUS_ORG
GTP25033
SMD RND 22.8mil
MTP25002
SMD RND 22.8mil
4
R25050 100K
0201 SSD
0201
R25015
GTP25032
SMD RND 22.8mil
R25051 100K
0201 SSD
INT. PD
INT. PD
2K
1P8VSUS_ORG
GTP25034
SMD RND 22.8mil
GTP25035
SMD RND 22.8mil
R25048 49.9K
R25074 2K 0201
R25055 100K
0201
R25056 100K
0201
R25075 2K 0201
0201
R25046 49.9K
3VSUS_ORG
U10001F
AN8
GPP_B15/GSPI0_CS#
AP7
GPP_B16/GSPI0_CLK
AP8
GPP_B17/GSPI0_MISO
AR7
GPP_B18/GSPI0_MOSI
AM5
GPP_B19/GSPI1_CS#
AN7
GPP_B20/GSPI1_CLK
AP5
GPP_B21/GSPI1_MISO
AN5
GPP_B22/GSPI1_MOSI
AB1
GPP_C8/UART0_RXD
AB2
GPP_C9/UART0_TXD
W4
GPP_C10/UART0_RTS#
AB3
GPP_C11/UART0_CTS#
AD1
GPP_C20/UART2_RXD
AD2
GPP_C21/UART2_TXD
AD3
GPP_C22/UART2_RTS#
AD4
GPP_C23/UART2_CTS#
U7
GPP_C16/I2C0_SDA
U6
GPP_C17/I2C0_SCL
U8
GPP_C18/I2C1_SDA
U9
GPP_C19/I2C1_SCL
AH9
GPP_F4/I2C2_SDA
AH10
GPP_F5/I2C2_SCL
AH11
GPP_F6/I2C3_SDA
AH12
GPP_F7/I2C3_SCL
AF11
GPP_F8/I2C4_SDA
AF12
GPP_F9/I2C4_SCL
KBL-R U42
<$LOCATION> <MATERIAL> 6 OF 20 REV = 1
SAM_PCH_INT1 [25,27]
0201
3
KBL_R_U42
LPSS ISH
GPP_F10/I2C5_SDA/ISH_I2C2_SDA
GPP_F11/I2C5_SCL/ISH_I2C2_SCL
GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA
3VSUS_ORG
PCH_PMI_SLOW [20]
R25090 49.9K
0201
R25068 49.9K
R25069 49.9K
R25062 49.9K
R25061 49.9K
R25019 49.9K
R25020 49.9K
R25024 49.9K
GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL
GPP_D16/ISH_UART0_CTS#/SML0BALERT#
GPP_C12/UART1_RXD/ISH_UART1_RXD
GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_C15/UART1_CTS#/ISH_UART1_CTS#
SAM_PCH_T1_PWRBTN_N [25,27]
0201
0201
0201
0201
0201
0201
0201
GPP_D15/ISH_UART0_RTS#
GPP_A12/BM_BUSY#/ISH_GP6
CAM_F_PWR_DN_N [25,54]
CAM_IR_PWR_DN_N [25,54]
WW AN_PW REN [25,65]
PCH_AUD_1V8_EN [20,62]
PCH_TPANEL_PW R_EN [25,62,64]
2
GPP_D9 GPP_D10 GPP_D11 GPP_D12
GPP_D5/ISH_I2C0_SDA
GPP_D6/ISH_I2C0_SCL
GPP_D7/ISH_I2C1_SDA
GPP_D8/ISH_I2C1_SCL
GPP_A18/ISH_GP0 GPP_A19/ISH_GP1 GPP_A20/ISH_GP2 GPP_A21/ISH_GP3 GPP_A22/ISH_GP4 GPP_A23/ISH_GP5
CAM_F_XO_EN [20,25,54]
CAM_IR_XO_EN [25,54]
P2 P3 P4 P1
M4 N3
N1 N2
AD11 AD12
U1 U2 U3 U4
AC1 AC2 AC3 AB4
AY8 BA8 BB7 BA7 AY7 AW7 AP13
C25001
0201
68p
50V
R25071 0
0201 DNP
CAM_F_PWR_DN_N_R
R25004 330
0201
R25011 33
0201
R25057
49.9K
0201
R25003 330
0201
R25054 1K
0201
R25052 100K
0201
MTP25003
SMD RND 22.8mil
BBS_BIT0,BBS_BIT1 : Boot BIOS Strap
BBS_BIT0
1
0
Sampled on rising edge of PWROK.
1
MTP25001
SMD RND 22.8mil
TPANEL_RST_N [49] PCH_TPANEL_PW R_EN [25,62,64]
CAM_F_XO_EN [20,25,54]
GTP25024
TCON_BRD_REV [25,55] TCON_VENDOR_ID [25,55]
PCIE_WIFI_WAKE_N [50]
ALS_IRQ_N [54]
PCIE_WIFI_DISABLE_N [50]
PCIE_WIFI_PERST_N [50]
CAM_LED_F_EN [25,54]
WW AN_PW REN [25,65] PCIE_SSD_PERST_N [43,44]
R25053 100K
0201
Boot BIOS Strap
Boot BIOS Location
LPC - Not to use
SPI
(PCH)
CAM_F_PWR_DN_N [25,54]
CAM_IR_XO_EN [25,54]
CAM_IR_PWR_DN_N [25,54]
MTP25016
SMD RND 22.8mil
PCH_UART1_RXD [31,33]
PCH_UART1_TXD [31,33]
WLAN_PW D_N [25,50]
MTP25030
SMD RND 22.8mil
3VSUS_ORG
SAM_PCH_INT0 [25,29]
R25035 49.9K
0201
A A
5
1P8VSUS_ORG
4
R25036 49.9K0201 R25037 49.9K0201
TCON_BRD_REV [25,55] TCON_VENDOR_ID [25,55]
3
R25065 49.9K
0201
R25070 49.9K
0201
R25038 49.9K
0201
R25049 49.9K
0201
CAM_LED_F_EN [25,54]
SL_CONN [25,27]
WLAN_PW D_N [25,50]
PCH_AUD_5V_EN [25,64]
Want to ensure BIOS strap is for SPI boot mode - IPD
U SPECIFIC
2
BBS_BIT0 has internal SoC PD resistor
25. PCH(6)_CPU,GPIO,MISC
25. PCH(6)_CPU,GPIO,MISC
Title:
Title:
Title:
Microsoft Confidential
Microsoft Confidential
Microsoft Confidential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
B
B
B
Date: Sheet of
Date: Sheet of
Date: Sheet of
A
A
A
Engineer:
Engineer:
Engineer:
25. PCH(6)_CPU,GPIO,MISC
Surface
Surface
Surface
1.0.0.1
1.0.0.1
1.0.0.1
25 79Friday, April 27, 2018
25 79Friday, April 27, 2018
1
25 79Friday, April 27, 2018
5
Vinafix.com
4
V0P85A
3
2
1
Put this logic at near SOC VCCPRIM.
R26010 0
DNP
C26001
6.3V
1u
22u
6.3V
22u
6.3V
0603
C26025
2.2u 6.3V
0603
C26057
25V
2p
0201
0402
0402
C26018 1u
0402
L26008
75OHM
6.3V
C26019 1u
0402
D D
V1P00A
R26008
0 0603
R26009
0 0603
C26023
0603
C26024
VCCPLL(VCCSFR)=0.12A
V1P00A
C C
C26039
2p
25V 0201
3VSUS_ORG
3VSUS_ORG
B B
V1P00A
C26040
25V
2p
0201
L26003
75OHM
0402
1P8VSUS_ORG
C26041
25V
2p
0201
0 0402
V1P00A
V1P00A
V3P3_VCCDSW
L26004
R26001
R26002
0 0402
2pF caps need to be place as close to
A A
SOC pins as possible
V0P85A
C26007
6.3V
1u
0402
C26010 1u
0402
C26022 2p 25V
0201
75OHM
0402
L26009
1P8VSUS_ORG_L
C26017 1u
0402
C26059 1u
0402
6.3V
V3P3_VCCDSW
6.3V
0402
C26033 22u 6.3V
0603
DNP
75OHM
6.3V
6.3V
2.57A
25V 0201
25V 0201
25V 0201
C26021 2p 25V
0201
C26060 1u
0402
C26061
2p
25V 0201
C26005
6.3V
1u
0402
C26006 1u
0402
C26009
6.3V
1u
0402
C260542p
C260532p
C260552p
C26043 1u
0402
6.3V
V0P85A
C26056
2p
25V 0201
C26044
2p
6.3V
6.3V
3VSUS_ORG
C26030 22u 6.3V
0603
25V 0201
C26045
2p
25V 0201
DCPDSW_1P0
VCCMPHYGT_1P0
VCCAMPHYPLL_1P0
VCCAPLL_1P0
C26042 2p 25V
0201
VCCSRAM_1P0
VCCAPLLEBB
C26046
2p
25V 0201
U10001O
AB19
VCCPRIM_1P0_AB19
AB20
VCCPRIM_1P0_AB20
P18
VCCPRIM_1P0_P18
AF18
VCCPRIM_CORE_AF18
AF19
VCCPRIM_CORE_AF19
V20
VCCPRIM_CORE_V20
V21
VCCPRIM_CORE_V21
AL1
DCPDSW_1P0
K17
VCCMPHYAON_1P0_K17
L1
VCCMPHYAON_1P0_L1
N15
VCCMPHYGT_1P0_N15
N16
VCCMPHYGT_1P0_N16
N17
VCCMPHYGT_1P0_N17
P15
VCCMPHYGT_1P0_P15
P16
VCCMPHYGT_1P0_P16
K15
VCCAMPHYPLL_1P0
L15
VCCAMPHYPLL_1P0
V15
VCCAPLL_1P0
AB17
VCCPRIM_1P0_AB17
Y18
VCCPRIM_1P0_Y18
AD17
VCCDSW_3P3_AD17
AD18
VCCDSW_3P3_AD18
AJ17
VCCDSW_3P3_AJ17
AJ19
VCCHDA
AJ16
VCCSPI
AF20
VCCSRAM_1P0_AF20
AF21
VCCSRAM_1P0_AF21
T19
VCCSRAM_1P0_T19
T20
VCCSRAM_1P0_T20
AJ21
VCCPRIM_3P3_AJ21
AK20
VCCPRIM_1P0_AK20
N18
VCCAPLLEBB
KBL-R U42
<$LOCATION> <MATERIAL> 15 OF 20 REV = 1
V1P8A
C26035
22u
0603
6.3V
C26036
22u
0603
6.3V
KBL_R_U42
CPU POWER 4 OF 4
R26003
0 0603
C26034
10u
6.3V 0402
C26037
22u
0603
6.3V
V1P00A
C26038
22u
0603
6.3V
C26031 22u 6.3V
0603
0201
VCCPGPPA
VCCPGPPB VCCPGPPC VCCPGPPD
VCCPGPPE
VCCPGPPF VCCPGPPG
VCCPRIM_3P3_V19
VCCPRIM_1P0_T1
VCCATS_1P8
VCCRTCPRIM_3P3
VCCRTC_AK19 VCCRTC_BB14
DCPRTC
VCCCLK1
VCCCLK2
VCCCLK3
VCCCLK4
VCCCLK5
VCCCLK6
GPP_B0/CORE_VID0 GPP_B1/CORE_VID1
1P8VSUS_ORG
C26058 1u
0402
6.3V
C26029 22u 6.3V
0603
V0P85A_VR_FB_R [59]
AK15 AG15 Y16 Y15 T16 AF16 AD15
V19
T1
AA1
AK17
AK19 BB14
BB10
A14
K19
L21
N20
L19
A10
AN11 AN13
GTP26005
GTP26006
V3P3_DSW
DCPRTC
VCCCLK2_R
VCCCLK4_R
VCCCLK5_R
R26004
0 0603
for B, C E port
C26002
6.3V
1u
0402
C26047
2p
25V 0201
3VSUS_ORG
C26032 47u 6.3V
0805
DNP
C26003 1u
C26048
2p
25V 0201
C26014
25V
0.1u
0402
C26051 2p 25V
0201
C26050 2p 25V
0201
6.3V
0402
C26012 1u
0402
C26052 2p 25V
0201
VCCCLK5_R
6.3V
DNP
C26004 1u
6.3V
0402
C26008 1u
0402
V1P00A
3VSUS_ORG
C26026 22u 6.3V
0603
C26027 22u 6.3V
C26028 47u
6.3V
C26013
0.1u
0402
0603
6.3V
0603
3VSUS_ORGV1P00A
1P8VSUS_ORG
3VSUS_ORG
25V
C26015
0.1u
0402
L26005
2.2uH MHz
0603
L26006
0
L26007
0
C26049
2p
25V 0201
25V
VCC_RTC
V1P00A
C26016 1u
0402
C26020 1u
0402
6.3V
6.3V
1P8VSUS_ORG
C26011
6.3V
1u
0402
26. PCH(7)_POWER
26. PCH(7)_POWER
Title:
Title:
Title:
Microsoft Confidential
Microsoft Confidential
Microsoft Confidential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
A3
A3
U SPECIFIC
5
4
3
2
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
A
A
A
Engineer:
Engineer:
Engineer:
26. PCH(7)_POWER
Surface
Surface
Surface
26 79Friday, April 27, 2018
26 79Friday, April 27, 2018
1
26 79Friday, April 27, 2018
1.0.0.1
1.0.0.1
1.0.0.1
5
Vinafix.com
4
3
MTP27001
2
1
D D
C C
U27001A
MK22FN512VDC12
MK22FN512VDC12
U27001B
PORT A
PTA4/NMI_b/EZP_CS_b/LLWU_P3/FTM0_CH1
FTM2_CH0/PTA10/FTM2_QD_PHA PTA11/FTM2_CH1/FTM2_QD_PHB
PTA12/FTM1_CH0/I2S0_TXD0/FTM1_QD_PHA
PTA13/LLWU_P4/FTM1_CH1/I2S0_TX_FS/FTM1_QD_PHB
PTA14/SPI0_PCS0/UART0_TX/I2S0_RX_BCLK
PTA15/SPI0_SCK/UART0_RX/I2S0_RXD0
PTA16/SPI0_SOUT/UART0_CTS_b/I2S0_RX_FS
PTA17/ADC1_SE17/SPI0_SIN/UART0_RTS_b/I2S0_MCLK
PORT B
PTB0/I2C0_SCL/ADC0_SE8/ADC1_SE8/LLWU_P5/FTM1_CH0/FTM1_QD_PHA
PTB1/I2C0_SDA/ADC0_SE9/ADC1_SE9/FTM1_CH1/FTM1_QD_PHB
PTB2/ADC0_SE12/I2C0_SCL/UART0_RTS_b/FTM0_FLT3
PTB3/ADC0_SE13/I2C0_SDA/UART0_CTS_b/FTM0_FLT0
PTB6/ADC1_SE12/FB_AD23 PTB7/ADC1_SE13/FB_AD22
PTB8/LPUART0_RTS_b/FB_AD21
PTB9/SPI1_PCS1/LPUART0_CTS_b/FB_AD20
PTB10/ADC1_SE14/SPI1_PCS0/LPUART0_RX/FB_AD19/FTM0_FLT1
PTB11/ADC1_SE15/SPI1_SCK/LPUART0_TX/FB_AD18/FTM0_FLT2
PTB16/SPI1_SOUT/UART0_RX/FTM_CLKIN0/FB_AD17/EWM_IN
PTB17/SPI1_SIN/UART0_TX/FTM_CLKIN1/FB_AD16/EWM_OUT_b
PTB18/FTM2_CH0/I2S0_TX_BCLK/FB_AD15/FTM2_QD_PHA
PTB19/FTM2_CH1/I2S0_TX_FS/FB_OE_b/FTM2_QD_PHB
PTB20/FB_AD31/CMP0_OUT PTB21/FB_AD30/CMP1_OUT
PTB22/FB_AD29
PTB23/SPI0_PCS5/FB_AD28
PTA29/FB_A24
G11 G10 G9 G8 F11 E11 D11 E10 D10 C10
B10 E9 D9 C9 F10 F9 F8 E8
J8 J9 J4 K8 L8 K9 L9 J10 H10 H11
DEBUG_LED1
SAM_TEST_B10 [34] SAM_SSD_FLUSH [43]
SKL_SLP_SUS_N [22,34,58,59]
BATGONE [63,70] SAM_DISPLAY_BKLT_EN [30] SAM_PCH_T1_PWRBTN_N [25] SAM_UEFI_TOP_SWAP [20] SAM_PCH_RSV1 [10]
CPUFAN_TACH [39]
SKL_SLP_S0_N [22,31,34,38,59,61]
PCH_DPWROK [22,34,56,59] SAM_SL_5V_EN [63,69] 3P3V_SSD_EN_R [29]
TRACKPAD_INT_N [10,48]
SAM_GP_DEEPSLP [56] SL_CONN [25]
Use last, NMI
SAM_PCH_UART_TX [25,31]
SAM_PCH_UART_RX [25,31] SKL_SLP_S4_N [22,34,45,59,61] SAM_PCH_HALL_INT [10]
SAM_KBTP_PWR [48]
3P3VA_SW
MASTER_THERMTRIP_N [56]
R27100 499K
CPUFAN_PW M [39] SAM_PANEL_LOGO_EN [30] SAM_SL_5V_PG [63]
DEBUG_LED0 [29]
MTP27003
MTTP27013
MTP27002
MTTP27012
SAM_KIP_RST [31,48]
MK22FN512VDC12
U27001C
PORT C
B B
A A
PTC1/FTM0_CH0/ADC0_SE15/LLWU_P6/SPI0_PCS3/UART1_RTS_b/FB_AD13/I2S0_TXD0/LPUART0_RTS_b
PTC2/ADC0_SE4b/CMP1_IN0/SPI0_PCS2/UART1_CTS_b/FTM0_CH1/FB_AD12/I2S0_TX_FS/LPUART0_CTS_b
PTC3/CMP1_IN1/LLWU_P7/SPI0_PCS1/UART1_RX/FTM0_CH2/CLKOUT/I2S0_TX_BCLK/LPUART0_RX
PTC4/LLWU_P8/SPI0_PCS0/UART1_TX/FTM0_CH3/FB_AD11/CMP1_OUT/LPUART0_TX
PTC5/LLWU_P9/SPI0_SCK/LPTMR0_ALT2/I2S0_RXD0/FB_AD10/CMP0_OUT/FTM0_CH2
PTC6/CMP0_IN0/LLWU_P10/SPI0_SOUT/PDB0_EXTRG/I2S0_RX_BCLK/FB_AD9/I2S0_MCLK
MK22FN512VDC12
PTC0/ADC0_SE14/SPI0_PCS4/PDB0_EXTRG/FB_AD14/USB_SOF_OUT
PTC7/CMP0_IN1/SPI0_SIN/USB_SOF_OUT/I2S0_RX_FS/FB_AD8
PTC8/ADC1_SE4b/CMP0_IN2/FTM3_CH4/I2S0_MCLK/FB_AD7
PTC9/ADC1_SE5b/CMP0_IN3/FTM3_CH5/I2S0_RX_BCLK/FB_AD6/FTM2_FLT0
PTC10/ADC1_SE6b/I2C1_SCL/FTM3_CH6/I2S0_RX_FS/FB_AD5
PTC11,ADC1_SE7b/LLWU_P11/I2C1_SDA/FTM3_CH7/FB_RW_b
PTC12/FB_AD27/FTM3_FLT0
PTC13/FB_AD26 PTC14/FB_AD25 PTC15/FB_AD24
PTC16/LPUART0_RX/FB_CS5_b/FB_TSIZ1/FB_BE23_16_BLS15_8_b
PTC17/LPUART0_TX/FB_CS4_b/FB_TSIZ0/FB_BE31_24_BLS7_0_b
PTC18/LPUART0_RTS_b/FB_TBST_b/FB_CS2_b/FB_BE15_8_BLS23_16_b
PTC19/LPUART0_CTS_b/FB_CS3_b/FB_BE7_0_BLS31_24_b/FB_TA_b
B9 D8 C8 B8 A8 D7 C7 B7 A7 D6 C6 C5 B6 A6 A5 B5 D5 C4 B4 A4
R27046 2K 0402DEBUG_SL
R27047 2K 0402DEBUG_SL
R27036
2.2K
1%
0201
R27037
2.2K
1% 0201
PMIC_EN_R [29] KIP_IO [29,31,48]
PLT_RST_BUF_N [22,34,38,43,44,56] SL_PG [56,69]
DEBUG_MUX_S3 [31]
GP_SAM_COLD_BOOT [56]
RTCRST_CTRL_R [29]
SAM_PCH_RSMRST_N_R [29] VCCRTC_RST [56] DEBUG_MUX_S2 [31]
SB_PWRBTN_SR [29] SAM_PCH_INT1 [25] SL_UART_SEL_N [69] BRDID_ADC_RD_EN [28,29]
SAM_THERM1 [39] SL_ADC_RD_EN [69] SL_3P3V_DIS [46]
SSD_FLUSH_DONE [43,56]
RTCRST_CTRL[29]
I2C_ROP_SCL [31,63,70] I2C_ROP_SDA [31,63,70]
PU Resistors are on PCH side
SKL_RTCRST_N [20]
D
G
R27005 100K
0201
Q27001 RUM002N02GT2L
S
27. SAM_1, K22
27. SAM_1, K22
Title:
Title:
Title:
Microsoft Confidential
Microsoft Confidential
Microsoft Confidential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
B
B
B
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
A
A
A
Engineer:
Engineer:
Engineer:
27. SAM_1, K22
Surface
Surface
Surface
27 79Thursday, April 26, 2018
27 79Thursday, April 26, 2018
1
27 79Thursday, April 26, 2018
1.0.0.1
1.0.0.1
1.0.0.1
5
Vinafix.com
3P3VA_SW
C28005
6.3V
10u
0402
D D
C28002
C28001
6.3V
6.3V
0.1u
0.1u
0201
0201
Place these caps close to VDA
C28011
C28012
6.3V
6.3V
0.1u
0.010u
0201
0201
MTP_BF28001
SMD RND 31.5m il
Place 10u cap close to IC Place 1x0.1uF and 1x0.01uF cap next to each VDD pin
C28004
C28003
6.3V
0.1u
0201
6.3V
0.1u
0201
C28015 1u
6.3V 0201
C28006
6.3V
0.010u
0201
C28016
6.3V
0.010u
0201
C28007
6.3V
0.010u
0201
C28008
6.3V
0.010u
0201
3P3VA
R28039 0 0201
R28040 10K
0201
C28017
0.1u
0201
C28009
6.3V
0.010u
0201
6.3V
4
MTP_BF28005
SMD RND 31.5m il
U27001E
E6
VDD_E6
E7
VDD_E7
E5
VDD_E5
L10
VDD_L10
F5
VDDA
K6
VBAT
G1
VOUT33
G2
VREGIN
G5
VREFH
G6
VREFL
L3
VREF_OUT/CMP1_IN5/CMP0_IN5/ADC1_SE18
F6
VSSA
K10
VSS_K10
G3
VSS_G3
F7
VSS_F7
L6
VSS_L6
G7
VSS_G7
MK22FN512VDC12
XTAL0/PTA19/FTM1_FLT0/FTM_CLKIN1/LPTMR0_ALT1
3P3VA
RESET
EXTAL0/PTA18/FTM0_FLT2/FTM_CLKIN0
EXTAL32
XTAL32
3
C28019
0.1u
0201
6.3V
Place this cap close to RESETN
J11
L11
K11
L5
L4
C28020
2.7p
DNP 25V
C28010
0.010u
0201
1 2
0201
3P3VA_SW
Y28001
32.768KHz
MTP_BF76007
SMD RND 31.5m il
R28002 10K
0201
R28044 0 0201
C28021
2.7p
DNP 25V
0201
2
SAM_RESET_N [31,33]
GTP28012 SMD RND 22.8mil
MTP_BF28002
SMD RND 31.5m il
1
C C
3P3VA_SW
R28093 4.02K0201 TBL1001
R28092 8.06K0201 TBL1001
R28091 16.2K0201 TBL1001
R28082 4.02K0201 SSD
R28081 8.06K0201 SSD
R28072 16.2K0201 TBL2303
R28071 4.02K0201 TBL2303
R28062 8.06K0201 TBL2304
R28061 16.2K0201 TBL2304
R28053 4.02K0201 TBL2301
B B
U27001F
NC_B11 NC_C11 NC_A11
NC_K3 NC_H4
F1 F2
H1 H2 J1 J2 K1 K2 L1 L2 J3 H3
K5 K4
J6 H8 J7 H9 K7
E4 E3 E2 F4 H7
L7 B11 C11 A11 K3 H4
SAM_GP_RST [56]
TP28009
GTP28010
SMD RND 22.8m il
BOARD_ID0 BOARD_ID1 BOARD_ID2 BOARD_ID3 BOARD_ID4 DEBUG_RETAIL_BOAR D_ID NEW_BOA RD_ID
SMD RND 22.8m il
SHOULD BE MTP
3P3VA
R28043 200K
0201
4
SAM_SL_VDET [69] SL_ADC [69]
SAM_CHG_IMO N [63]
MTP_BF28003 SMD RND 31.5mil
SAM_SWD _CLK [31,33]
PMIC_SAM_INT_N [59]
SAM_TRACE_SW O [31,33]
SAM_SWD _DIO [31,33]
SAM_DISPLAY_BKLT_PW M [30]
MTP_BF28004
SMD RND 22.8m il
MTTP28015
PMIC_SAM_RSM RST_N [34,59] SAM_KIP_UART_TX [48]
SHOULD BE MTP
SAM_RTC_W AKEUP [56]
SAM_IC_DEBUG_ TX [33] SAM_IC_DEBUG_ RX [33]
SHOULD BE MTP
USB0_DP
USB0_DM
ADC0_DP1
ADC0_DM1
ADC1_DP1/ADC0_DP2
ADC1_DM1/ADC0_DM2
ADC0_DP0/ADC1_DP3
ADC0_DM0/ADC1_DM3
ADC1_DP0/ADC0_DP3
ADC1_DM0/ADC0_DM3
ADC1_SE16/ADC0_SE22
ADC0_SE16/CMP1_IN2/ADC0_SE21
DAC0_OUT/CMP1_IN3/ADC0_SE23 DAC1_OUT/CMP0_IN4/ADC1_SE23
JTAG_TCLK/PTA0/SWD_CLK/EZP_CLK/UART0_CTS_b/FTM0_CH5
JTAG_TDO/PTA2/TRACE_SWO/EZP_DO/UART0_TX/FTM0_CH7
JTAG_TRST_b/PTA5/USB_CLKIN/FTM0_CH2/I2S0_TX_BCLK
PTE0/CLKOUT32K/I2C1_SDA/ADC1_SE4a/SPI1_PCS1/UART1_TX/RTC_CLKOUT
PTE1/I2C1_SCL/ADC1_SE5a/LLWU_P0/SPI1_SOUT/UART1_RX/SPI1_SIN
A A
MK22FN512VDC12
5
JTAG_TDI/PTA1/EZP_DI/UART0_RX/FTM0_CH6
JTAG_TMS/PTA3/SWD_DIO/UART0_RTS_b/FTM0_CH0
PTE2/ADC1_SE6a/LLWU_P1/SPI1_SCK/UART1_CTS_b
PTE3/ADC1_SE7a/SPI1_SIN/UART1_RTS_b/SPI1_SOUT
PTE4/LLWU_P2/SPI1_PCS0/LPUART0_TX
RTC_WAKEUP
R28052 8.06K0201 TBL2301
R28051 16.2K0201 TBL2301
R28012 10K0201 TBL2303
R28013 10K0201 TBL2301B
R28014 10K0201 TBL2301A
R28019 3.48K0201
R28020 3.48K0201
R28021 3.48K0201
R28022 3.48K0201
R28023 10K0201 TBL2303
R28024 10K0201 TBL2301B
R28025 10K0201 TBL2301A
C28018
0.1u6.3V
0201
R28037 33K
0201
3
SOC type 2
SOC type 1
SOC type 0
SEE TABLE TBL1001 on page 10
SSD vendor 1
SSD vendor 0
RESERVED 1
RESERVED 0
SEE TABLE TBL_SSD_2302 on page 23
Table 2303 bits are "RESERVED" in PM
Greenpack revision 1
Greenpack revision 0
SEE TABLE TBL2301D on page 23
PCBA vendor and revision 2
PCBA vendor and revision 1
PCBA vendor and revision 0
SEE TABLE on page 23
RESERVED 2
SEE TABLE TBL2301B on page 23 SEE TABLE TBL2301A on page 23
BRDID_ADC_R D_EN[27,29]
R28036
100K
0201
VBAT_CHGR [63]
2
R28102 100K
0201
GND
Q28002 RUM002N02GT2L
D
Microsoft Conf idential
Microsoft Conf idential
Microsoft Conf idential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
G
S
Q28003 RUM002N02GT2L
D
G
A
A
A
S
Title:
Title:
Title:
Engineer:
Engineer:
Engineer:
28. SAM_2, K22
28. SAM_2, K22
28. SAM_2, K22
Surface
Surface
Surface
28 79Thursday, April 26, 2018
28 79Thursday, April 26, 2018
1
28 79Thursday, April 26, 2018
1.0.0.1
1.0.0.1
1.0.0.1
5
Vinafix.com
D D
U27001D
PORT - D
PTD0/LLWU_P12/SPI0_PCS0/UART2_RTS_b/FTM3_CH0/FB_ALE/FB_CS1_b/FB_TS_b/LPUART0_RTS_b
PTD6/ADC0_SE7b/LLWU_P15/SPI0_PCS3/UART0_RX/FTM0_CH6/FB_AD0/FTM0_FLT0/SPI1_SOUT
PTD1/ADC0_SE5b/SPI0_SCK/UART2_CTS_b/FTM3_CH1/FB_CS0_b/LPUART0_CTS_b
PTD2/LLWU_P13/SPI0_SOUT/UART2_RX/FTM3_CH2/FB_AD4/I2C0_SCL/LPUART0_RX
PTD3/SPI0_SIN/UART2_TX/FTM3_CH3/FB_AD3/I2C0_SDA/LPUART0_TX
PTD4/LLWU_P14/SPI0_PCS1/UART0_RTS_b/FTM0_CH4/FB_AD2/EWM_IN/SPI1_PCS0
PTD5/ADC0_SE6b/SPI0_PCS2/UART0_CTS_b/FTM0_CH5/FB_AD1/EWM_OUT_b/SPI1_SCK
4
PTD7/UART0_TX/FTM0_CH7/FTM0_FLT1/SPI1_SIN
PTD8/I2C0_SCL/LPUART0_RX/FB_A16 PTD9/I2C0_SDA/LPUART0_TX/FB_A17
PTD10/LPUART0_RTS_b/FB_A18 PTD11/LPUART0_CTS_b/FB_A19
PTD12/FTM3_FLT0/FB_A20
PTD13/FB_A21 PTD14/FB_A22 PTD15/FB_A23
D4 D3 C3 B3 A3 A2 B2 A1 A10 A9 B1 C2 C1 D2 D1 E1
3
R29045 2K 0402DEBUG_SL
R29019 100 0201 R29020 100 0201
R29076499
0201
2
3P3VA_SW
R29061 200K
0201
PSAM_SL_DBG_EN [29]
SAM_CHG_ACOK [63]
SL_UART_RX [69] SL_UART_TX [69] DEBUG_MUX_S0 [31] SAM_CHGR_PSU_ON_R [29]
SAM_PWR_BTN_STATE [34,56]
I2C_SCL_MCU [34,39,59] I2C_SDA_MCU [34,39,59]
KIP_IO [27,31,48]
GP_DBGACC [31,47,56]
SAM_PCH_INT0 [25]
1
SAM_SEN_HALL_INT [41]
BL_INST_ON_HNDSHK [10,30]
SPI1_EXT [37] SAM_PROCHOT_R [29]
C C
MK22FN512VDC12
B B
DEBUG_SL
R29072
BRDID_ADC_RD_EN[27,28]
DEBUG_SL
PSAM_SL_DBG_EN[29]
1000201
DEBUG_SL
R29074 20K
0201
DEBUG_SL
C29022
0.1u 6.3V
0201
PTE6/SPI1_PCS3/LPUART0_CTS_b/I2S0_MCLK/FTM3_CH1/USB_SOF_OUT
00201
DEBUG_SL
R29075 20K
0201
PTE5/SPI1_PCS2/LPUART0_RX/FTM3_CH0
PTE24/ADC0_SE17/I2C0_SCL/EWM_OUT_b
PTE25/ADC0_SE18/I2C0_SDA/EWM_IN
PTE26/CLKOUT32K/RTC_CLKOUT/USB_CLKIN
3P3VA_SW
DEBUG_SL
C29021
0.1u 6.3V
U29020
1
PR
6
D
D
7
CK
2
CLR
NC7SZ74L8X
DEBUG_SL
Pn
VCC
Q
QnCnK
GND
8
3
Q
5
Q
4
0201
PORT - E
G4 F3 H5 J5 H6
SAM_SL_DBG_EN [47]
PMIC_EN_R[27]
3P3V_SSD_EN_R[27]
SAM_PCH_RSMRST_N_R[27]
RTCRST_CTRL_R[27]
SB_PWRBTN_SR[27]
R29046 2K 0402DEBUG_SL
0201
0201
0201
0201
0201
SAM_KIP_UART_RX [48]
DEBUG_MUX_S1 [31]
SAM_PWRBTN_N [56]
DEBUG_LED0 [27]
PMIC_SAM_ALL_SYS_PWRGD [22,34,59]
PMIC_EN [58,59] 3P3V_SSD_EN [65]
RTCRST_CTRL [27] SAM_PMIC_PWRBTN [59] VRM_PWR_EN [22,66] SAM_CHGR_PSU_ON [34,63] SAM_PROCHOT [10]
R29049499
R29050499
R29051499
R29052499
R290530
MTP29001R29073 MTP29002 MTP29003 MTP29004 MTP29005 MTP29006 MTP29007 MTP29008
SAM_PCH_RSMRST_N [18,22,56]
SAM_CHGR_PSU_ON_R[29]
A A
5
DEBUG_SL
C29023
0.1u 6.3V
0201
4
SAM_PROCHOT_R[29]
3
0201
0201
R29055499
R29056499
29. SAM_3, K22
29. SAM_3, K22
Title:
Title:
Title:
Microsoft Confidential
Microsoft Confidential
Microsoft Confidential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
B
B
B
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
A
A
A
Engineer:
Engineer:
Engineer:
29. SAM_3, K22
Surface
Surface
Surface
29 79Thursday, April 26, 2018
29 79Thursday, April 26, 2018
1
29 79Thursday, April 26, 2018
1.0.0.1
1.0.0.1
1.0.0.1
5
Vinafix.com
4
3
When BL_INST_ON_HNDSHK is LOW, SAM controls BKLT.
2
1
When BL_INST_ON_HNDSHK is HIGH, SOC controls BKLT.
D D
SOC_BKLTEN[10]
SAM_DISPLAY_BKLT_EN[27]
BL_INST_ON_HNDSHK[10,29]
SOC_BKLT_CTRL_IN[10]
C C
SAM_DISPLAY_BKLT_PWM[28]
MTP30002
MTP30003
MTP30001
MTP30004
C1
A1
A2
C1
A1
A2
U30001
A
B
C
A
B
C
VCC
GND
SN74AUP1G97YZP
U30002
VCC
GND
SN74AUP1G97YZP
B2
C2
Y
B1
B2
C2
Y
B1
3P3VA_SW
GND
GND
GTP30001
L_BKLTEN [72]
C30001
0.1u 6.3V
0201
GTP30002
L_BKLT_CTRL_IN [72]
C30002
0.1u 6.3V
0201
3P3VA_SW
C30003
0.1u 6.3V
0201
U30003
5
VCC
GND
4
Y
3
GND
2
GND
Microsoft Confidential
Microsoft Confidential
Microsoft Confidential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
B
B
B
Date: Sheet of
Date: Sheet of
Date: Sheet of
DISPLAY_VDD_EN [65]
Title:
Title:
Title:
Engineer:
Engineer:
Engineer:
A
A
A
30. INSTANT_ON
30. INSTANT_ON
30. INSTANT_ON
Surface
Surface
Surface
30 79Thursday, April 26, 2018
30 79Thursday, April 26, 2018
1
30 79Thursday, April 26, 2018
1.0.0.1
1.0.0.1
1.0.0.1
B B
A A
SAM_PANEL_LOGO_EN[27,30]
SOC_DISPLAY_VDD_EN[10]
R30002
49.9K
R30014 100 0201
5
R30001 200K
GND
4
R30004
49.9K
R30005 200K
35kohms-287kohms pulldown at TDM PANEL_LOGO Input is 3.3V tolerant
R30003
49.9K
SAM_PANEL_LOGO_EN[27,30]
R30015 200K
GND
PANEL_LOGO [55]
3
2
A
1
B
74LVC1G32GX
5
Vinafix.com
3P3VA 3P3VA
C31006
0.1u 6.3V
0201
SAM_SWD _DIO[28,33] SPI1_SI_DBG[37] PCH_UART1_TXD[25,33] KIP_SWD_D IO[48]
I2C_ROP_SDA[27,63,70]
SSD_TDI_BUF[31]
TS_TDI_BUF[31]
D D
3P3VA
C C
Mode SD_DEBUG3 SD_DEBUG1 SD_DEBUG4 SD_DEBUG2
B0
B B
A A
B1
SAM JTAG SAM_SWD_CLK SAM_SWD_DIO SAM_RESET_N SAM_TRACE_SWO
B2
UEFI Flashing SPI1_CLK_DBG SPI1_SI_DBG SPI1_SO_DBG SPI1_CS_DBG_N
B3
PCH logging PCH_UART1_RXD PCH_UART1_TXD SAM_PCH_UART_RX SAM_PCH_UART_TX
B4
KIP JTAG KIP_SWD_CLK KIP_SWD_DIO KIP_RST KIP_IO
B5
BATTERY/CHARGER I2C_ROP_SCL I2C_ROP_SDA I2C_SCL_TP_R I2C_SDA_TP_R
B6
SSD JTAG SSD_JTAG_TCK SSD_JTAG_TDI SSD_JTAG_TDO SSD_JTAG_TMS
B7
TS JTAG TS_TCK TS_TDI TS_TDO TS_TMS PWR MON DEBUG_PMI_I2C_SCL DEBUG_PMI_I2C_SDA DEBUG_PMI_SLOW SKL_SLP_S0_N
DEBUG_MUX_S0[29,31] DEBUG_MUX_S1[29,31] DEBUG_MUX_1O EN[31] DEBUG_MUX_2O EN[31]
C31003
0.1u 6.3V
0201 DEBUG_SL
SAM_TRACE_SW O[28,33] SAM_RESET_N[28,33]
SAM_PCH_UAR T_TX[25,27] SAM_PCH_UAR T_RX[25,27]
KIP_IO[27,29,48]
I2C_SDA_TP[25,48]
SSD_TMS_BUF[31]
TS_TMS_BUF[31] SKL_SLP_S0_N[22,27,34,38,59,61]
DEBUG_MUX_S0[29,31] DEBUG_MUX_S1[29,31] DEBUG_MUX_1O EN[31] DEBUG_MUX_2O EN[31]
MTP31001 MTP31002 MTP31003 MTP31004
3P3VA
DEBUG_SL
R31028 100K
R31029 100K
R31030 100K
0402DEBUG_SL
0402DEBUG_SL
0402DEBUG_SL
Motherboard Mux Settings
MTP31015 MTP31016 MTP31017 MTP31018
3P3VA
5
R31040 100K
R31041 100K
R31042 100K
U31001
14
V+
4
1S1
3
1S2
2
1S3
1
1S4
8
2S1
9
2S2
10
2S3
11
2S4
12
IN1
16
IN2
15
1EN
13
2EN
TS3A5017RSVR
DEBUG_SL
U31003
14
V+
4
1S1
3
1S2
2
1S3
1
1S4
8
2S1
9
2S2
10
2S3
11
2S4
12
IN1
16
IN2
15
1EN
13
2EN
TS3A5017RSVR
DEBUG_SL
TS_TCK_BUF [31] TS_TMS_BUF [31] TS_TDO_BUF [31] TS_TDI_BUF [31]
TS_TCK_BUF [31]
TS_TMS_BUF [31]
TS_TDI_BUF [31]
0402DEBUG_SL
0402DEBUG_SL
0402DEBUG_SL
5
1D
7
2D
6
GND
5
1D
7
2D
6
GND
MTP31011 MTP31012 MTP31013 MTP31014
SSD_TCK_BUF [31] SSD_TMS_BUF [31] SSD_TDO_BUF [31] SSD_TDI_BUF [31]
SSD_TCK_BUF [31]
SSD_TMS_BUF [31]
SSD_TDI_BUF [31]
MTP31005
MTP31006
TS_TDO_BUF[31]
TS_TCK_BUF[31]
TS_TMS_BUF[31]
TS_TDI_BUF[31]
SSD_TDO_BUF[31]
SSD_TCK_BUF[31]
SSD_TMS_BUF[31]
SSD_TDI_BUF[31]
4
SD_DEBUG1 [47]
SD_DEBUG2 [47]
4
3P3VA
C31004
0.1u 6.3V
0201 DEBUG_SL
C31011
0.1u 6.3V
0201 DEBUG_SL
C31008
0.1u 6.3V
0201 DEBUG_SL
C31012
0.1u 6.3V
0201 DEBUG_SL
6
4
3
1
2
5
1
2
5
1
2
5
3P3VA
SAM_DEBUG_RX[33]
SAM_DEBUG_TX[33]
U31004
VCCY
VCCA
Y
GND
NC5
74AUP1T34GM
DEBUG_SL
SOT886
U31006
VCCY
VCCA
A
GND
NC5
74AUP1T34GM
DEBUG_SL
SOT886
U31008
VCCY
VCCA
A
GND
NC5
74AUP1T34GM
DEBUG_SL
SOT886
U31010
VCCY
VCCA
A
GND
NC5
74AUP1T34GM
DEBUG_SL
SOT886
U31011
6
VCCY
VCCA
4
Y
3
GND
74AUP1T34GM
SOT886
U31012
1
VCCY
VCCA
2
A
5
GND
NC5
74AUP1T34GM
SOT886
U31013
1
VCCY
VCCA
2
A
5
GND
NC5
74AUP1T34GM
SOT886
U31014
1
VCCY
VCCA
2
A
5
GND
NC5
74AUP1T34GM
SOT886
DEBUG_MUX_S3[27,31]
DEBUG_MUX_S2[27,31]
DEBUG_MUX_S1[29,31]
DEBUG_MUX_S0[29,31]
1
2
A
5
6
4
Y
3
6
4
Y
3
6
4
Y
3
1
2
A
5
NC5
DEBUG_SL
6
4
Y
3
DEBUG_SL
6
4
Y
3
DEBUG_SL
6
4
Y
3
DEBUG_SL
0402 to allow rework
R31022 100K
R31013 100K
R31014 100K
R31015 100K
MTP31009
R31016 22.1
R31018 100K
R31017 22.1
1P8V_TS
C31013
0.1u 6.3V
0201 DEBUG_SL
R31025 22.1
R31026 22.1
R31027 22.1
0201DEBUG_SL
C31007
0.1u 6.3V
0201 DEBUG_SL
0201DEBUG_SL
C31014
0.1u 6.3V
0201 DEBUG_SL
0201DEBUG_SL
3P3V_SSD R31047 FOR INTEL 1P8V_SSD R31046 FOR SAMSUNG TOSHIBA
R31046 0
0201 SSD
0201DEBUG_SL
0201DEBUG_SL
0201DEBUG_SL
3P3V_SSD
1P8V_SSD
C31015
0.1u 6.3V
0201 DEBUG_SL
R31043 22.1
C31009
0.1u 6.3V
0201 DEBUG_SL
R31044 22.1
C31016
0.1u 6.3V
0201 DEBUG_SL
R31045 22.1
0402
0402DNP
0402
MTP31010
TS_TDO_1V8 [49]
TS_TCK_1V8 [49]
TS_TMS_1V8 [49]
TS_TDI_1V8 [49]
R31047 0
0201 SSD
SSD_JTAG_TDO [43]
SSD_JTAG_TCK [43,44]
SSD_JTAG_TMS [43,44]
SSD_JTAG_TDI [43]
3
0402DEBUG_SL
0402DEBUG_SL
0402DEBUG_SL
0402DEBUG_SL
SAM_DEBUG_R_ RX [47]
SAM_DEBUG_R_ TX [47]
3
2
C31002
0.1u 6.3V
0201
DEBUG_GP
DEBUG_SL
C31001
0.1u 6.3V
0201 DEBUG_SL
MTP31019
MTP31020
U31015
1
3
SN74LVC1G19DRYR
DEBUG_SL
A
E
SAM_SWD _CLK[28,33]
SPI1_CLK_DBG[37] PCH_UART1_RXD[25,33] KIP_SWD_C LK[48]
I2C_ROP_SCL[27,63,70] SSD_TCK_BUF[31] TS_TCK_BUF[31]
DEBUG_MUX_S0[29,31] DEBUG_MUX_S1[29,31] DEBUG_MUX_1O EN[31] DEBUG_MUX_2O EN[31]
3P3VA
SPI1_SO_DBG[37]SPI1_CS_DBG_N[37]
SAM_KIP_RST[27,48]
I2C_SCL_TP[25,48]
SSD_TDO_BUF[31]
TS_TDO_BUF[31]
DEBUG_MUX_S0[29,31] DEBUG_MUX_S1[29,31] DEBUG_MUX_1O EN[31] DEBUG_MUX_2O EN[31]
DEBUG_MUX_S3[27,31] DEBUG_MUX_S2[27,31] DEBUG_MUX_S0[29,31] DEBUG_MUX_S1[29,31]
R31048
GP_DBGACC[29,47,56]
0
DEBUG_GP 0201
5
3
Q31002B NX3008NBKS
D
G
S
4
2
6
Q31001A NX3008NBKS
D
G
DEBUG_GP
S
1
GTP31001
SMD RND 22.8m il
R31039 100K
DNP 0402
2
VCC
GND
5
Y0 Y1
U31002
14
V+
4
1S1
3
1S2
2
1S3
1
1S4
8
2S1
9
2S2
10
2S3
11
2S4
12
IN1
16
IN2
15
1EN
13
2EN
TS3A5017RSVR
DEBUG_SL
U31005
14
V+
4
1S1
3
1S2
2
1S3
1
1S4
8
2S1
9
2S2
10
2S3
11
2S4
12
IN1
16
IN2
15
1EN
13
2EN
TS3A5017RSVR
DEBUG_SL
5 6 4 2
G
5
1D
7
2D
6
GND
5
1D
7
2D
6
GND
3P3VA
C31010
0.1u 6.3V
0201 DEBUG_SL
3
Q31001B NX3008NBKS
D
DEBUG_GP
S
4
2
6
Q31002A NX3008NBKS
D
G
DEBUG_GP
S
1
Microsoft Conf idential
Microsoft Conf idential
Microsoft Conf idential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
A
A
A
1
SD_DEBUG3 [47]
MTP31007
SD_DEBUG4 [47]
MTP31008
DEBUG_MUX_1O EN [31]
DEBUG_MUX_2O EN [31]
31. Debug mux
31. Debug mux
1
31. Debug mux
Surface
Surface
Surface
Title:
Title:
Title:
Engineer:
Engineer:
Engineer:
1.0.0.1
1.0.0.1
31 79Thursday, April 26, 2018
31 79Thursday, April 26, 2018
31 79Thursday, April 26, 2018
1.0.0.1
5
Vinafix.com
V3P3_DSW
4
3
2
1
BOOT_TO_USB
D D
R32001
4.99K
BOOT_TO_USB [25]
MTP32002
MTTP_BF32004
SMD RND 31.5mil
MTTP
C C
B B
MTTP_BF32003
SMD RND 31.5mil
MTTP
SMD RND 22.8mil
MTP
V3P3_DSW
MTP32001
SMD RND 22.8mil
MTP
R32002
4.99K
BOOT_TO_UEFI [25]
A A
32. Debug Buttons
32. Debug Buttons
32. Debug Buttons
Surface
Surface
Surface
32 79Thursday, April 26, 2018
32 79Thursday, April 26, 2018
1
32 79Thursday, April 26, 2018
1.0.0.1
1.0.0.1
1.0.0.1
Title:
Title:
Title:
Microsoft Confidential
Microsoft Confidential
Microsoft Confidential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
B
B
B
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
A
A
A
Engineer:
Engineer:
Engineer:
5
Vinafix.com
4
3
2
1
J3302
2
10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64
66 68
4 6 8
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64
MT2 MT4
DBG_D
DEBUG CONN
D D
3P3VA_SW
IMVP_SDA_P[66] IMVP_SCL_P[66]
DBG_D
C3301
0.1u6.3V
0201
C C
4/6/2018
SAM_RESET_N[28,31]
SAM_SWD_CLK[28,31] SAM_SWD_DIO [28,31]
GND
11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63
MT1 MT3
1
1
3
3
5
5
7
7
9
9
11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63
65 67
GND
SAM_TRACE_SWO [28,31]
3P3VA_SW
DBG_D
C3302
0.1u6.3V
0201
Changed H_PROCHOT# to H_PROCHOT_3P3V# for EV2
R3303 10K
0201_p28
DBG_D
DBG_D
C3303
0201
0.1u6.3V
PCH_UART1_RXD [25,31]
V5A
MTP33001
SMD RND 22.8mil
MTP33002
SMD RND 22.8mil
PCH_UART1_TXD [25,31]
B B
SAM_DEBUG_TX [31]
3
Q33002B NX3008NBKS
D
PROT_3V3_SW_G[69]
SAM_IC_DEBUG_TX[28]
A A
5
4
3
SAM_IC_DEBUG_RX[28]
2
5
G
S
4
6
Q33002A NX3008NBKS
D
2
G
S
1
DVi7U7660s16s512x2Retail
DVi7U7660s16s512x2Retail
DVi7U7660s16s512x2Retail
33. SW Debug Conn
33. SW Debug Conn
Title:
Title:
Title:
Microsoft Confidential
Microsoft Confidential
Microsoft Confidential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
B
B
B
Date: Sheet of
Date: Sheet of
Date: Sheet of
A
A
A
Engineer:
Engineer:
Engineer:
33. SW Debug Conn
Surface
Surface
Surface
1
SAM_DEBUG_RX [31]
33 79Thursday, April 26, 2018
33 79Thursday, April 26, 2018
33 79Thursday, April 26, 2018
1.0.0.1
1.0.0.1
1.0.0.1
5
Vinafix.com
D D
4
3
2
1
PCH_PWRBTN_N[22,5 9]
I2C_SCL_MCU[29,39,59]
PCH_DPWROK[22,27,56,59]
I2C_SDA_MCU[2 9,39,59]
SAM_PMIC_PW RBTN_N[59]
DDR_VTT_CTL[11,5 9]
PROCHOT_N[10 ,60,63,66]
NTC_REF[60]
C C
I2C testpoints are shown on page 25
SAM_CHGR_PSU_ON[29, 63]
GTP34032
GTP34002
GTP34003
GTP34004
GTP34005
GTP34008
GTP34009
GTP34011
GTP34012
GTP34030
GTP34029
GTP34041
GTP34040
GTP34016
GTP34017
SKL_SLP_SUS_N [22 ,27,58,59]
V3P3A_PCH
PMIC_SAM_RSM RST_N [28,59]
SKL_SLP_S4_N [22,27,45 ,59,61]
SAM_TEST_B10[27]
GTP34001
GTP34018
GTP34049
PLT_RST_BUF_N[22,27,38,43,4 4,56]
GTP34019
GTP34020
GTP34021
GTP34022
GTP34023
SKL_SLP_S3_N [22,59,61 ]
SKL_VCCST_PWRGD [22,59]
PMIC_SAM_ALL _SYS_PWRGD [22 ,29,59]
SKL_PCH_PWROK [ 22,59]
SKL_SYS_PWROK [22 ,59]
SKL_SLP_S0_N [22,27,31 ,38,59,61]
SAM_PWR_BTN_S TATE[29, 56]
B B
A A
GTP34010
DVi7U7660s16s51 2x2Retail
DVi7U7660s16s51 2x2Retail
DVi7U7660s16s51 2x2Retail
Title
Title
Title
34. EE Debug C onnector
34. EE Debug C onnector
34. EE Debug C onnector
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A <RevCode>
A2
A <RevCode>
A2
A <RevCode>
A2
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
1
34 76Thursday, April 26, 2018
34 76Thursday, April 26, 2018
34 76Thursday, April 26, 2018
5
Vinafix.com
D D
4
3
2
1
C C
B B
A A
35. EMPTY
35. EMPTY
35. EMPTY
Surface
Surface
Surface
1
1.0.0.1
1.0.0.1
1.0.0.1
35 79Thursday, April 26, 2018
35 79Thursday, April 26, 2018
35 79Thursday, April 26, 2018
Title:
Title:
Microsoft Confidential
Microsoft Confidential
Microsoft Confidential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
B
B
B
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
A
A
A
Title:
Engineer:
Engineer:
Engineer:
5
Vinafix.com
4
3
2
1
D D
C C
MTP3600 3
SMD RND 2 2.8mil
SMD RND 2 2.8mil
MTP3600 1
MTP3600 2
SMD RND 2 2.8mil
No Power Monitors in this SKU
B B
Resistor Address for MAX3440
20.5K => 0x3C/0x3D
11.0K => 0x38/0x39
5.90K => 0x34/0x35
A A
5
4
3
2
3.16K => 0x30/0x31
1.74K => 0x2C/0x2D 931K => 2x28/2x29 499 => 2x24/2x25 GND => 2x20/2x21
36. Power Monitor
36. Power Monitor
36. Power Monitor
Title:
Title:
Microsoft Confidential
Microsoft Confidential
Microsoft Confidential
Size Project Name R ev
Size Project Name R ev
Size Project Name R ev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Title:
Surface
Surface
Surface
Engineer:
Engineer:
Engineer:
A
A
A
1
36 79Thursday, April 26, 2018
36 79Thursday, April 26, 2018
36 79Thursday, April 26, 2018
1.0.0.1
1.0.0.1
1.0.0.1
5
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4
3
2
1
D D
C C
B B
SPI1_CLK SPI1_SI SPI1_SO SPI1_WP_N SPI1_HOLD_N
SPI1_CS0_N
3VSUS_ORG
0201
R37001 1K
SPI1_WP_N
SPI_CLK = 20/33/50Mhz
SPI_CLK[21] SPI_SI[21] SPI_SO[21] SPI1_SO_DBG [31] SPI_WP_IO2[21]
SPI_HOLD_IO3_N[21]
SPI_CS0_N[21]
R37006 0 NDEBUG_SL 0201 R37007 0 NDEBUG_SL 0201 R37008 0 NDEBUG_SL 0201 R37009 0 NDEBUG_SL 0201 R37010 0 NDEBUG_SL 0201 R37011 0 NDEBUG_SL 0201
SPI1_CS0_N SPI1_SO
(128Mb=16MB @104MHz)
Needs to >= 66MHz
U37001 W25Q128JVPIQ
1
CS#
2
DO(IO1)
3
WP#(IO2)
4
GND1
9
GND2
SPI1_CLK SPI1_SI SPI1_SO SPI1_WP_N SPI1_HOLD_N SPI1_CS0_N
HOLD#(IO3)
DI(IO0)
SPI_CLK SPI_SI SPI_SO SPI_WP_IO2 SPI_HOLD_IO3_N SPI_CS0_N
8
VCC
7 6
CLK
5
DEBUG_SL
U37002 TS3A27518EZQSR
A1
COM1
B1
COM2
C1
COM3
D1
COM4
E1
COM5
D2
COM6
A3
N.C.
B3
NC1
A2
NC2
A4
NC3
B5
NC4
C5
NC5
A5
NC6
BGA24
UEFI SPI ROM
3VSUS_ORG
SPI1_HOLD_N SPI1_CLK SPI1_SI
3VSUS_ORG
C37002
C2
V+
C4
EN#
B4
IN1
D3
IN2
C3
GND
E2
NO1
E3
NO2
E4
NO3
D5
NO4
D4
NO5
E5
NO6
MTTP37002 SMD RND 22.8mil MTTP37003 SMD RND 22.8mil MTTP37004 SMD RND 22.8mil MTTP37005 SMD RND 22.8mil MTTP37006 SMD RND 22.8mil MTTP37007 SMD RND 22.8mil
0.1u 6.3V
0201 DEBUG_SL
SPI1_WP_DBG_N SPI1_HOLD_DBG_N
MTTP37001
SMD RND 22.8mil
C37001
0.1u 6.3V
0201
DEBUG_SL
R37005 100K
0201
0201
DEBUG_SL
3VSUS_ORG
R37003 1K
R37004 1K
0201 DEBUG_SL
SPI1_EXT [29]
SPI1_CLK_DBG [31] SPI1_SI_DBG [31]
SPI1_CS_DBG_N [31]
IN1/IN2 = L => COM to NC IN1/IN2 = H => NC to COM
A A
37. SPI ROM UEFI
37. SPI ROM UEFI
Title:
Title:
Title:
Microsoft Confidential
Microsoft Confidential
Microsoft Confidential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
B
B
B
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
A
A
A
Engineer:
Engineer:
Engineer:
37. SPI ROM UEFI
Surface
Surface
Surface
37 79Tuesday, May 01, 2018
37 79Tuesday, May 01, 2018
1
37 79Tuesday, May 01, 2018
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Trusted Platform Module
D D
V3P3_DSW
V3P3_DSW
V3P3_DSW
C38001
0.1u 6.3V
R38003
4.99K
0201 TBL3801
C C
R38004
4.99K
0201 TBL3801
SKL_SLP_S0_N[22,27,31,34,59,61]
0201
R38015 0
R38017 0
R38019 0
C38008
0.1u 6.3V
0201
TBL38010201
TBL38010201
TBL38010201
R38016
10K
TPM_PP
0201TBL3801
U38001
1
NC/SDA/GPIO0
2
NC/SCL/GPIO1
3
NC_3
4
GND_4
5
VDD/VSB/NC
6
GPIO/GPX/GPIO2/NC
7
PP
8
NC/TEST
9
LRESET1#/NC/BADD/GPIO3
10
VDD/3V
11
GND_11
12
NC_12
13
NC_13
14
NC/RESERVED
NPCT650SBCW X
TBL3801
LRESET2#/LRESET/SPI_RST/SRESET/LRESET#
NC/LPCPD/LPCPD#
SERIRQ/SIRQ
LAD0/MISO
GND_25
VDD/VHIO/3V_24
LAD1/MOSI
LFRAME#
LCLK/SCLK
LAD2/SPI_RST/RESET
VDD/VHIO/3V_19
GND_18
LAD3
NC/CLK/RUN/SINT/GPIO4/CLKRUN#
TPM_NC6
28 27 26 25 24 23 22 21 20 19 18 17 16 15
V3P3_DSW V3P3_DSW
R38002 100K
X813010-001 0201 TBL3801
TPM_NC9
R38006 0
0201 TBL3801
R38009
8.2K
0201
TBL38010201
R38018 0
TPM_SERIRQ [21]
TPM_LPC0 [21]
TBL3801
R38005 0
0201
TPM_DEEPSLP_N [21]
V3P3_DSW
C38002
0.1u 6.3V
0201
TPM_LPC1 [21]
TPM_LFRAME [21]
TPM_LPC2 [21]
TPM_LPC3 [21]
TPM_CLKRUN [21]
C38007
0.1u 6.3V
0201
DNP
C38004
50V
10p
0201
C38006
4.7u
6.3V 0402
V3P3_DSW
DNP
C38005 22p
0201
R38007 100K
0201
PLT_RST_BUF_N [22,27,34,43,44,56]
25V
MTP38001
TPM_CLK [21]
B B
TBL3801
Lancelot RefDes Nuvuton NationZ
U38001 M1006791-002 X930840-002 R38002 NO STUFF X813010-001 R38003 NO STUFF NO STUFF R38004 X813007-001 NO STUFF R38005 X811786-001 NO STUFF R38006 NO STUFF X811786-001 R38015 X811786-001 NO STUFF
A A
5
R38016 NO STUFF NO STUFF R38017 X811786-001 X811786-001 R38018 X811786-001 NO STUFF R38019 X811786-001 NO STUFF
4
38. TPM
38. TPM
Title:
Title:
Title:
Microsoft Confidential
Microsoft Confidential
Microsoft Confidential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
B
B
B
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
A
A
A
Engineer:
Engineer:
Engineer:
38. TPM
Surface
Surface
Surface
1
1.0.0.1
1.0.0.1
1.0.0.1
38 79Thursday, April 26, 2018
38 79Thursday, April 26, 2018
38 79Thursday, April 26, 2018
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V5A
D D
C C
C39001 22u 6.3V
0603
MTP39002
SMD RND 22.8mil
CFAN_PWM_R_1
5 1 2 3 4 6
J39001
MT7 NC1 1 2 3 4 NC2
MT8
7
8
SMD RND 22.8mil
CPUFAN_TACH [27]
R39005 4.99K
0201
FAN Connector
MTP39001
R39004 100
0603
V3P3_DSW
R39021
close to J39001
100K
0201
V5A
SMD RND 22.8mil
SMD RND 22.8mil
CPUFAN_PW M [27]
MTP39003
MTP39004
0201
3P3VA_SW
33K
0201
R39008
U39003
1
SCL
6
SDA
4
ADD0
SN1608035
V+
ALERT
GND
3P3VA
5
3
2
C39006
0.1u 6.3V
0201
3P3VA
33K
R39019
B B
I2C_SCL_MCU[29,34,59]
I2C_SDA_MCU[29,34,59]
GP_TSYS[56]
R39017 0 0201
SAM_THERM1[27]
7-bit I2C Address = 0x48
A1
A A
A2
D39003
BAT54CW
K
R39026 0 0201
MTTP39001
SMD RND 22.8mil
SHOULD BE MTTP?
39. Temp Sensor/System Fan
39. Temp Sensor/System Fan
Title:
Title:
Title:
Microsoft Confidential
Microsoft Confidential
Microsoft Confidential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
B
B
U SPECIFIC
5
4
3
2
B
Date: Sheet of
Date: Sheet of
Date: Sheet of
A
A
A
Engineer:
Engineer:
Engineer:
39. Temp Sensor/System Fan
Surface
Surface
Surface
39 79Tuesday, May 01, 2018
39 79Tuesday, May 01, 2018
1
39 79Tuesday, May 01, 2018
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5V_AUDIO
D D
C40009 and C40010 can be deleted and L40001 converted to a 0 ohm jumper if smart amp remains.
1P8V_AUDIO
C C
C40014
10u
6.3V
0402
B B
C40015
0.1u
6.3V 0201
R40017 0
Place close to J41001
R40018 0
Place under U40001
R40002
10
0402
C40016
10u
0402
0201
0201
L40001
0805
C40017
1P8V_AUDIO
6.3V
0.1u
6.3V 0201
GNDGND
AGND
AUDIO_VREF1
C40003 10u 6.3V
0402
AGND AGND
C40034
6.3V
22u
0603
AGND
2A
600 OHM
C40009 10u
10V 0603
GND GND
C40010 10u
6.3V 0402
GND GND
C40031 10u
6.3V 0402
C40004
0.1u 6.3V
0201
AGND
C40020 10u
6.3V 0402
AGND AGND
C40021
0.1u
6.3V 0201
TP40003
SMD RND 22.8mil
close to audio
C40008
0.1u
6.3V 0201
C40011
0.1u
6.3V 0201
C40032
AGND
C40019
2.2u
6.3V 0402
0.1u
6.3V 0201
AGND
C40005
6.3V
22u
0603
0.1u 6.3V
0402
AGND
C40018
2.2u
6.3V 0402
AUDIO_VREF
6.3V
6.3V
5V_AUDIO_AVDD
C40006
0.1u 6.3V
0201
AGND
0402
ALC298_MIC1_CAP
C40022 10u
6.3V 0402
AGND
C40001
2.2u
0402
C40025 10u
C40002
0.1u 6.3V
0201
AGNDAGND
C40033
0201
6.3V
0402
C40024 10u
GND
C40028 2.2u 6.3V
C40029 2.2u 6.3V
6.3V
AGND
AGND
0201
0402
0402
CODEC_LDO1
0201
C40027 10u
AGND
CODEC_LDO2
CODEC_LDO3
6.3V
C40023 0.1u
GND
CPVPP
CPVEE
AGND
6.3V
C40026 0.1u
AGND
GND
GND
AGND
GND
AGND
CODEC_CBP1_R
CODEC_CBN1_R
CODEC_CBP2_R
CODEC_CBN2_R
ALC298_VD22STB
U40008
J5
VD33STB
C9
AVDD1
B9
LDO1-AMP_B9
B8
LDO1-AMP_B8
C7
MIC1-CAP
D7
VREF
A9
AVSS1
H9
PVDD1
D9
PVDD2
E8
PVSS_E8
F9
PVSS_F9
J6
DVDD
G1
DVDD-IO
J2
DVSS-IO_J2
J4
DVSS-IO_J4
J9
DVSS-IO_J9
C1
AVDD2
E1
VBG
D1
LDO2-CAP
D2
VRP-ADDA
H1
LDO3-IN
J1
LDO3-CAP
F1
AVSS2_F1
A3
CPVDD
A2
CPGND
B4
CPVPP_B4
C4
CPVPP_C4
C3
CPVEE
C5
CPVEE-CLN
A4
CPVREF
D5
AVSS2_D5
B3
CBP1
A1
CBN1
B2
CBP2
B1
CBN2
C2
DUMMY_C2
D3
DUMMY_D3
D4
DUMMY_D4
E2
DUMMY_E2
F2
DUMMY_F2
G4
BOND0
G5
BOND1
J7
DFTEN
ALC3269C-GRT
R40015 10K
0201 DNP
V5A
GND
R40020 10K
0201
R40034 324K
SPKR Trace Width
1. Maximum trace resistance for each channel less than 0.5 ohms.
2. Each of 4 traces, measured from CODEC to speaker connector, less than 0.25 ohms
MTTP40001SMD RND 22.8mil MTTP40002SMD RND 22.8mil
E4
BCLK
SYNC
IRQ GPIO1 GPIO2
GPIO4
EAPD
HP-L
HP-R
MIC-L MIC-R
H2
SDATA_IN_R
E3 G2
F3
H3 H4
H7 J8 F4 F7 G3 G6 F5 H8 G7 E5 J3 G8
E6 F6
H6 H5
B5
HPOUT_L [41]
A5
HPOUT_R [41]
A8
B6 A6 C8
B7
MIC1_L [41]
A7
MIC1_R [41]
C6
MIC1_VREFO_L [41]
D6
E7
D8 E9
G9 F8
R40006 33
R40013100K
0201
COMBO_JACK [41]
1P8V_AUDIO
MTTP_BF40001 SMD RND 31.5mil MTTP_BF40002 SMD RND 31.5mil
MTTP_BF40004 SMD RND 31.5mil MTTP_BF40003 SMD RND 31.5mil
MTTP_BF40006 SMD RND 31.5mil MTTP_BF40005 SMD RND 31.5mil
0201
AGND
HPOUT_JD_R
CODEC_AMP_OUTL [42] CODEC_AMP_OUTR [42]
RESETO
SDATA-IN
SDATA-OUT
I2C-SCL
I2C-SDA
DC_DET
I2S-DIN
I2S-DOUT
I2S-BCLK
SPDIF-IN
I2S-LRCK
GPIO10
DMIC-CLK1
DMIC-DATA1
GPI-JD1 GPI-JD2
AVSS-SW
LINE1-L
LINE1-R
LINE1-VREFO
MIC1-VREFO-L
MIC1-VREF-O-R
PCBEEP
SPK-OUT-LP
SPK-OUT-LN
SPK-OUT-RP SPK-OUT-RN
DNP
C40012 22p
25V
0201
GND
MTP40001
SMD RND 22.8mil
CODEC_PD_N
DMIC_CLK [20,54]
DMIC_DATA [20,54]
GND
AZ_BITCLK_1 [20]
AZ_SDATA_IN0 [20]
AZ_SDATA_OUT_1 [20]
AZ_SYNC_1 [20]
CODEC_PD_N [42]
R40031 1K
0201
0201
R40001 100K
R40003 200K
1P8V_AUDIO
0201
MTTP40004
SMD RND 22.8mil
HPOUT_JD [41]
GND
A A
GND
5
AGND
40. REALTEK ALC3269 CODEC
40. REALTEK ALC3269 CODEC
Title:
Title:
Title:
Microsoft Confidential
Microsoft Confidential
Microsoft Confidential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
4
3
2
Date: Sheet of
A
A
A
Engineer:
Engineer:
Engineer:
40. REALTEK ALC3269 CODEC
Surface
Surface
Surface
40 79Thursday, April 26, 2018
40 79Thursday, April 26, 2018
1
40 79Thursday, April 26, 2018
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V3P3_DSW
R41015
D D
J41005
PINS MIRRORED
2
2
4
4
6
6
8
8
10
MTG2
R41001
MIC1_VREFO_L[40]
C41001
4.7uF
6.3V
MIC1_R[40]
C C
MIC1_L[40]
0402
C41015
4.7uF
6.3V 0402
2.2K 020 1
R41002 1K
0201
L41001 place close to J41004
R41003 22K
0201
L41001
0603
BLM18SG121TN1D
120 OHM,100MHZ
C41002
100p25V
0201
12
502426-0810
MTG4
MTG1 MTG3
1
1
3
3
5
5
7
7
9 11
C41016
6.3V
0.1u
PCB trace width of MIC1-R/Mic1-L (Sleeve/Ring2) are
AGND
AGND
required at least 40 mil for HP crosstalk consideration and
499K
0201
Audio Jack/MIC1 Combo Jack
SMD RND 22.8m il
MTP41011
SAM_SEN_HALL_INT [29]
its length should be as short as possible
SMD RND 22.8m il
MTP41001
MIC1_R_CR_F _C
COMBO_JACK[40]
HPOUT_L[40]
HPOUT_R[40]
B B
AMP_SPK_RP[42]
C41008 1000p25V
AMP_SPK_RN[42]
0201
C41007 1000p 25V
0201
GND
C41004 10u 6.3V
0402
AGND
0603
R41005 51.1
R41006 51.1
0603
R41004 22K
0201
HPOUT_L_F
HPOUT_R_F
R41007 10K
0201
AGND AGND
BLM18SG121TN1D
L41002
0603
0603
BLM18SG121TN1D
120 OHM,100MHZ
R41008 10K
0201
A1 A2
120 OHM,100MHZ
L41003
C41005 100p
25V 0201
SPKR
D41005 V14MLA0603NH
GNDGND
C41006 100p
25V 0201
D41006 V14MLA0603NH
A1 A2
D41002 V5.5MLA0402NR
A1 A2
SMD RND 22.8m il
MTP41006
MTP41007
SMD RND 22.8m il
GND
A1 A2
GNDGND
1
2
3 4
HPOUT_L_F_C
D41003 V5.5MLA0402NR
J41002 78171-0002
1
2
MTG1 MTG2
HPOUT_R_F_C
X872411-001
MTP41004
SMD RND 22.8m il
MTP41005
SMD RND 22.8m il
MTP41002
SMD RND 22.8m il
D41004 V5.5MLA0402NR
A1 A2
GND
CDS2C05GTA
HPOUT_JD [40]
D41001 V5.5MLA0402NR
A1 A2
GND
MIC1_R_CR_F _C
AGND
1
3
4
5
2
AGND
DNP
J41004
MIC
RIGHT
DET
LEFT
GND
MTP41003
SMD RND 22.8m il
GNDGND
J41003
GND
3
78171-0002
1
2
3 4
SMD RND 22.8m il
A A
AMP_SPK_LP[42]
C41009 1000p 25V
0201
C41010 1000p25V
AMP_SPK_LN[42]
5
0201
GND
4
D41007 V14MLA0603NH
A1 A2
GND GND
A1 A2
MTP41008
D41008 V14MLA0603NH
MTP41009
SMD RND 22.8m il
1
2
MTG1 MTG2
X872411-001
41. Audio Jack/Spkr
41. Audio Jack/Spkr
41. Audio Jack/Spkr
Title:
Title:
Microsoft Conf idential
Microsoft Conf idential
Microsoft Conf idential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
C
C
C
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
A
A
A
Title:
Engineer:
Engineer:
Engineer:
1
Surface
Surface
Surface
1.0.0.1
1.0.0.1
41 79Thursday, April 26, 2018
41 79Thursday, April 26, 2018
41 79Thursday, April 26, 2018
1.0.0.1
5
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SPKR Trace Width
1. Maximum trace resistance for each
Stereo Input(S.E.)
channel less than 0.5 ohms.
2. Each of 4 traces, measured from
Stereo Output-BTL
D D
OUTPR OUTNR OUTNL OUTPL
CODEC to speaker connector, less than 0.25 ohms
AMP_SPK_RP [41] AMP_SPK_LN [41] AMP_SPK_RN [41]
AMP_SPK_LP [41]
24
OUTPR
BSPR
PVCC
PVCC
SDZ
FAULTZ
INPR
INNR
EPAD
0 0201
R42015 0
0201 DNP
C42013
330p
0201 25V
GND
Plimit
1
R42016
R42002
0201
10
Close IC Close IC
C42001
0.22u
0402 25V
23
22
OUTNR
GVDD
2
GVDD
C42005 1u
0402 10V
21
BSNR
ALC1304
Gain/SLV3GND4INNL
20
GND
GND
U42001
5
0402
Close IC
0201
R42003
0201
10
19
6
C42010
1u
10V
R42017 0
3
0.22u
0402 25V
BSNL
INPL
C42011
1u
0402 10V
C42019
330p
0201 25V
C42003
18
OUTNL
MUTE7PBTL/BTL
8
17
GND
OUTPL
BSPL
PVCC
PVCC
AVCC
Sync
AM0
AM1
16
15
14
13
12
11
10
9
GAIN / SLV
R42001
10
0201
Close IC
C C
B B
A A
VSYS VSYS
C42017 10u
0603 16V
1P8V_AUDIO
R42022 10K
0201
1
CODEC_PD_N[40]
Q42001 MMBT3904WT1G
SOT-323
CODEC_AMP_OUTR[40]
5
Close IC
5V_AUDIO
32
C42007
0.1u
0201 16V
R42023 100K
0201
C42006 1000p
0201
25V
Hi : Normal Low: shut-down
AMP_PD_N
C42012
330p
0201 25V
C42002
C42008 1u
0402 10V
0.22u
0402 25V
0402 10V
0201
4
25
26
27
28
29
30
31
32
33
C42009 1u
R42014 0
C42018
330p
0201 25V
C42004
0.22u
0402 25V
CODEC_AMP_OUTL [40]
R42004
10
0201
Close IC
GVDD
BTL/PBTL Setting
Gain/SLV Setting
R42021 0
0201 DNP
R42008 0
0201
2
C42014 1000p
0201
25V
C42015
0.1u
0201 16V
C42016 10u
0603
16V
Close ICShut-down Control
AM Avoidance Setting
R42013 10K
0201 DNP
R42011 10K
0201
R42020 10K
0201 DNP
R42010 10K
0201
Title:
Title:
Microsoft Confidential
Microsoft Confidential
Microsoft Confidential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
B
B
B
Date: Sheet of
Date: Sheet of
Date: Sheet of
A
A
A
Title:
Engineer:
Engineer:
Engineer:
DNP
R42012 10K
0201
42. Audio Amplifier
42. Audio Amplifier
42. Audio Amplifier
Surface
Surface
Surface
1
R42009 10K
0201
1.0.0.1
1.0.0.1
1.0.0.1
42 79Thursday, April 26, 2018
42 79Thursday, April 26, 2018
42 79Thursday, April 26, 2018
5
Vinafix.com
For common BGA SSDs
0201
SSD
10p
SSD_JTAG_TCK[31,43 ,44]
SSD_JTAG_TMS[31,43,44]
SSD_JTAG_TDI[ 31,43]
SSD1_JTAG_TDO[43,44]
GTP43014
VCC
NC
C43003
SSD
6.3V
GND
Y
C43098
0201 25V DNP
6 5
SSD_PCIECLK_REQ_N[20]
R43011 0 0402 R43012 0 0402
SSD
0.22u 0201 6.3V SSD
0.22u 0201 6.3V C43002
SSD
0.22u 0201 6.3V SSD
0.22u 0201 6.3V C43005
1P8V_SSD
SSD_PERST_N [44]
SMD RND 22.8mil
MTP43024
SSD
R43003 100K
1%
0201
GND
GTP43003
SMD RND 22.8mil
SSD_XTAL_OUT
SSD_XTAL_IN
SSD_DIAG1[43]
SSD_DIAG0[43,44]
SMD RND 22.8mil
SSD_DIAG1
SSD_DIAG0
SSD_JTAG_TCK
SSD_JTAG_TMS
SSD_JTAG_TDI
SSD1_JTAG_TDO
GTP43013
C43004
PCIECLK_SSD_DP[20] PCIECLK_SSD_DN[20]
PCIE_SSD_TX7_DP[24] PCIE_SSD_TX7_DN[2 4]
PCIE_SSD_RX7_DP[24] PCIE_SSD_RX7_DN[24]
PCIE_SSD_TX8_DP[24] PCIE_SSD_TX8_DN[2 4]
PCIE_SSD_RX8_DP[24]
PLT_RST_BUF_N[22,27,34,38,44,56]
DNP
C43099
10p
PCIE_SSD_RX8_DN[24]
GND
R43098 1M
0402
2 4
U43002
1
A
2
B
3 4
GND
SN74AUP1G08DRYR
XRCGB25M000F2P00R0
Y43001
31
DNP
SMD RND 22.8mil
0.1u
DNP
D D
PCIE_SSD_PERST_N[25,44]
0201
25V
C C
C43001
U43001A
D4
REFCLK_P
D5
REFCLK_N
F4
SATAmAp/PERp0
F5
SATAmAm/PERn0
H4
SATAmBp/PETp0
H5
SATAmBm/PETn0
K4
PER_P1
K5
PER_N1
M4
PET_P1
M5
PET_N1
P4
PERp2/NC_P4
P5
PERn2/NC_P5
T4
PETp2/NC_T4
T5
PETn2/NC_T5
V4
PERp3/NC_V4
V5
PERn3/NC_V5
Y4
PETp3/NC_Y4
Y5
PETn3/NC_Y5
D7
PERST#
F14
PEDET
D8
CLKREQ#
D14
SUSCLK/NC_D14
E8
DEVSLP/NC_E8
E12
PEWAKE#/NC_E12
W7
LED1#/ DAS
B6
CAL_P/NC_B6
C7
XTAL_ OUT/NC_C7
C8
XTAL_IN/NC_C8
C10
RZQ_1/NC_C10
D13
DIAG1/I2C_DATA
E13
DIAG0/I2C_CLK
L18
JTAG_TRST#/NC_L18
N17
JTAG_ TCK
N18
JTAG_ TMS
R17
JTAG_ TDI
R18
JTAG_ TDO
U17
SMB_ CLK/NC_U17
U18
SMB_ DATA/NC_U18
W18
ALERT#/NC_W18
AA10
RZQ_2/NC_AA10
HFB1M8MO331A0MR
Load R43100 and DNP R43101 for U43001 loaded and U44007 DNP (Single SSD)
DNP R43100 and Load R43101 for both U43001 and U44007 loade d (Dual SSD)
SSD2_JTAG_TDO[44]
SSD1_JTAG_TDO[43,44]
B B
R43100 0
0402 SSD
R43101 0
0402 SSD
4
1P2V_SSD
1P8V_SSD
3P3V_SSD
SSD_JTAG_TDO [31]
U43001C
C1
GND_C1
C2
GND_C2
C3
GND_C3
C4
GND_C4
C5
GND_C5
C15
GND_C15
D6
GND_D6
D11
GND_D11
E1
GND_E1
E2
GND_E2
E3
GND_E3
E4
GND_E4
E5
GND_E5
E6
GND_E6
E7
GND_E7
E11
GND_E11
E14
GND_E14
E15
GND_E15
F6
GND_F6
G1
GND_G1
G2
GND_G2
G3
GND_G3
G4
GND_G4
G5
GND_G5
G9
GND_G9
G10
GND_G10
G14
GND_G14
G15
GND_G15
H9
GND_H9
H10
GND_H10
J1
GND_J1
J2
GND_J2
J3
GND_J3
J4
GND_J4
J5
GND_J5
J9
GND_J9
J10
GND_J10
J14
GND_J14
J15
GND_J15
K7
GND_K7
K8
GND_K8
K9
GND_K9
K10
GND_K10
K11
GND_K11
K12
GND_K12
L1
GND_L1
L2
GND_L2
L3
GND_L3
L4
GND_L4
L5
GND_L5
L14
GND_L14
L15
GND_L15
M9
GND_M9
HFB1M8MO331A0MR
SSD_JTAG_TMS[31,43,44] SSD_JTAG_TCK[31,43 ,44] SSD_JTAG_TDI[ 31,43]
GND_M10
GND_N1 GND_N2 GND_N3 GND_N4
GND_N5 GND_N14 GND_N15
GND_P7
GND_P8
GND_P9 GND_P10 GND_P11 GND_P12
GND_R1
GND_R2
GND_R3
GND_R4
GND_R5
GND_R9 GND_R10 GND_R14 GND_R15
GND_T9 GND_T10
GND_U1
GND_U2
GND_U3
GND_U4
GND_U5
GND_U9 GND_U10 GND_U14 GND_U15
GND_W1 GND_W2 GND_W3 GND_W4 GND_W5
GND_W6 GND_W11 GND_W14 GND_W15
GND_Y6 GND_Y11 GND_Y13 GND_AA1 GND_AA2 GND_AA3 GND_AA4 GND_AA5
GND_AA14 GND_AA15
SSD_JTAG_TMS SSD_JTAG_TCK SSD_JTAG_TDI SSD_JTAG_TDO
M10 N1 N2 N3 N4 N5 N14 N15 P7 P8 P9 P10 P11 P12 R1 R2 R3 R4 R5 R9 R10 R14 R15 T9 T10 U1 U2 U3 U4 U5 U9 U10 U14 U15 W1 W2 W3 W4 W5 W6 W11 W14 W15 Y6 Y11 Y13 AA1 AA2 AA3 AA4 AA5 AA14 AA15
GTP43012
SMD RND 22.8mil
U43001B
G7
1p2v/1p1v/0p9v/RFU_G7
G8
1p2v/1p1v/0p9v/RFU_G8
G11
1p2v/1p1v/0p9v/RFU_G11
G12
1p2v/1p1v/0p9v/RFU_G12
H7
1p2v/1p1v/0p9v/RFU_H7
H8
1p2v/1p1v/0p9v/RFU_H8
H11
1p2v/1p1v/0p9v/RFU_H11
H12
1p2v/1p1v/0p9v/RFU_H12
J7
1p2v/1p1v/0p9v/RFU_J7
J8
1p2v/1p1v/0p9v/RFU_J8
J11
1p2v/1p1v/0p9v/RFU_J11
J12
1p2v/1p1v/0p9v/RFU_J12
R7
V1P8_R7
R8
V1P8_R8
R11
V1P8_R11
R12
V1P8_R12
T7
V1P8_T7
T8
V1P8_T8
T11
V1P8_T11
T12
V1P8_T12
U7
V1P8_U7
U8
V1P8_U8
U11
V1P8_U11
U12
V1P8_U12
D9
V3P3_D9
D10
V3P3_D10
E9
V3P3_E9
E10
V3P3_E10
W9
V3P3_W9
W10
V3P3_W10
Y9
V3P3_Y9
Y10
V3P3_Y10
HFB1M8MO331A0MR
C13 C14 D15 F15 H14 H15 K14 K15
L10 L11 L12
M7
M8 M11 M12 M14 M15
N7
N8
N9
N10 N11 N12 P14 P15 T14 T15 V14 V15
W8 W12 W13
MTP43020
SMD RND 22.8mil
MTP43021
SMD RND 22.8mil
MTP43022
SMD RND 22.8mil
MTP43023
SMD RND 22.8mil
U43001D
RFU_C13 RFU_C14 RFU_D15 RFU_F15 RFU_H14 RFU_H15 RFU_K14 RFU_K15
L7
RFU_L7
L8
RFU_L8
L9
RFU_L9 RFU_L10 RFU_L11 RFU_L12 RFU_M7 RFU_M8 RFU_M11 RFU_M12 RFU_M14 RFU_M15 RFU_N7 RFU_N8 RFU_N9 RFU_N10 RFU_N11 RFU_N12 RFU_P14 RFU_P15 RFU_T14 RFU_T15 RFU_V14 RFU_V15 RFU_W8 V_SEL0/RFU_W12 V_SEL1/RFU_W13
HFB1M8MO331A0MR
3
DNU_A1 DNU_A2 DNU_A4 DNU_A6
DNU_A8 DNU_A11 DNU_A13 DNU_A15 DNU_A17 DNU_A18
DNU_B1
DNU_B2
DNU_B4
DNU_B8 DNU_B11 DNU_B13 DNU_B15 DNU_B17 DNU_B18
DNU_C6
DNU_C9 DNU_C11 DNU_C12
DNU/DDR_VDDQ
DNU_C17 DNU_C18 DNU_D12 DNU_E16 DNU_E17 DNU_E18 DNU_G16 DNU_G17 DNU_G18
DNU_J16 DNU_J17 DNU_J18 DNU_L16
DNU/JTAG_TRST#
DNU_N16 DNU_R16 DNU_U16
DNU_W16 DNU_W17
DNU/SSD_FLUSH
DNU/SSD_FLUSH_FB
DNU_Y12 DNU_Y14 DNU_Y15 DNU_AA6 DNU_AA7 DNU_AA8 DNU_AA9
DNU_AA11
DNU_AA12
DNU_AA13 DNU_AA16
DNU/UART_RX
DNU/UART_TX
DNU_AB1 DNU_AB2 DNU_AB4 DNU_AB6 DNU_AB8
DNU_AB11 DNU_AB13 DNU/VCCF DNU_AB17 DNU_AB18
DNU_AC1 DNU_AC2 DNU_AC4 DNU_AC6
DNU_AC8 DNU_AC11 DNU_AC13 DNU_AC15
DNU/VCCFQ
DNU_AC18
A1 A2 A4 A6 A8 A11 A13 A15 A17 A18 B1 B2 B4 B8 B11 B13 B15 B17 B18 C6 C9 C11 C12 C16 C17 C18 D12 E16 E17 E18 G16 G17 G18 J16 J17 J18 L16 L17 N16 R16 U16 W16 W17 Y7 Y8 Y12 Y14 Y15 AA6 AA7 AA8 AA9 AA11 AA12 AA13 AA16 AA17 AA18 AB1 AB2 AB4 AB6 AB8 AB11 AB13 AB15 AB17 AB18 AC1 AC2 AC4 AC6 AC8 AC11 AC13 AC15 AC17 AC18
GTP43028SMD RND 22.8mil
GTP43020SMD RND 22.8mil
GTP43021SMD RND 22.8mil GTP43022SMD RND 22.8mil
GTP43029SMD RND 22.8mil
GTP43027SMD RND 22.8mil
GTP43026SMD RND 22.8mil GTP43023SMD RND 22.8mil
SMD RND 22.8mil
GTP43016
3P3V_SSD
PCH_SSD_UART2_TXD [25]
PCH_SSD_UART2_RXD [25]
GTP43024SMD RND 22.8mil GTP43025SMD RND 22.8mil
SMD RND 22.8mil
GTP43015
3P3V_SSD
R43019 100K
1% 0201
R43134 100K
0201
GND
GTP43017
SMD RND 22.8mil
GTP43018
SMD RND 22.8mil
2
PCIE[12:1]_TXN/P : Gen1 and Gen2 = 75 to 200 nF; where 100 nF is nominal value, Gen3 = 176 to 265 nF; where 220 nF is nominal value
PCIE[12:1]_RXN/P : Gen1 and Gen2 = 75 to 200 nF; where 100 nF is nominal value, Gen3 = 176 to 265 nF; where 220 nF is nominal value
Difference between USB3 and PCIe: 1. No Choke, 2. Add cap on PER (p832 at DG v1.2) RXN/RXP cap value must be different between Gen2 and Gen3 TX (from SOC) caps are at SOC side
Always ON logic, as like Intel RVP5.
C43101 4.7u
6.3V 0201 SSD
V3P3_DSW
VOS
SW
FB
PG
6
4
3
2
L43001
0.47uH
2.5X2.0X1.2
L43002
0.47uH
2.5X2.0X1.2
R43025
82.5K
1% 0201 DNP
X950133-001
R43007
82.5K
1% 0201
R43008 33K
1% 0201
R43024 33K
1% 0201
R43026 215K
1% 0201 DNP
V3P3_DSW
R43018
100K
1% 0201
SSD_DIAG1
SSD_DIAG0
3P3V_SSD
R43023 0 0201
SSD_DIAG1 [43]
SSD_DIAG0 [43,44]
C43029 10u
6.3V
0402
C43034 10u
6.3V
0402
0201
GND
0201
C43080
0.1u 6.3V
GND
7
1
5
C43039
0.1u 6.3V
QFN-7
U43006
7
VIN
1
EN
5
GND
TPS62085RLTR
QFN-7
U43005
VIN
EN
VOS
GND
TPS62085RLTR
6
SW
4
3
FB
2
PG
1
SMD RND 22.8mil
MTP43026
X950133-001
DNP
C43036
C43035 22u
R43009
C43041
82.5K
1%
100p
0201
25V
SSD
0201 DNP
R43010 is 215K for Samsung, 1P2V_SSD = 1.06V-1.15V + 100mV P-P ripple
R43010 165K
1% 0201 SSD
C43040
100p
25V 0201 DNP
4V 20% 0603
R43010 is 165K for Toshiba, 1P2V_SSD = 1.2V +/- 5% R43010 is 150K for Intel Pleasant Star, 1P2V_SSD = 1.24V+/- 4% R43010 is 165K and R43009 is 24.9K for Hynix, 1P2V_SSD = 0.92V +/- 0.06V
C43031
C43030
22u
22u
4V
4V
20%
20%
0603
0603
22u
4V 20% 0603
SMD RND 22.8mil
MTP43027
C43032 22u
4V 20% 0603
C43037 22u
4V 20% 0603
1P8V_SSD
C43033 22u
4V 20% 0603
C43038 22u
4V 20% 0603
1P2V_SSD
R43150 10K
0201
3P3V_SSD
U43007
VCC
Y
A B
GND
74AUP1G32GX
DNP
1P8V_SSD
R43124 100K
0201 DNP
1P8V_SSD
5 4
3
R43121 100K
0201 DNP
3P3V_SSD1P8V_SSD2
R43125
4.7K
0201 DNP
R43122
4.7K
0201 DNP
DNP
C43100
0.1u 6.3V
0201
Q43001A
2
DNP
GTP43019
SMD RND 22.8mil
61
Q43001B
3
DNP
3P3VA_SW
R43107 200K
0201
34
5
SSD
SSD
C43006
6.3V
1u
0402
1P8V_SSD
SSD
C43013
6.3V
1u
SSD
C43020
6.3V
1u
0402
0402
SSD
C43021
0.1u
6.3V 0201
1P2V_SSD
SSD
C43019
A A
6.3V
1u
0402
C43007
6.3V
1u
0402
SSD
C43014
6.3V
1u
0402
SSD
C43022
0.1u
6.3V 0201
5
SSD
C43008
0.1u
6.3V 0201
SSD
C43015
0.1u
6.3V 0201
SSD
C43023
0.1u
6.3V 0201
SSD
C43009
0.1u
6.3V 0201
SSD
C43016
0.1u
6.3V 0201
SSD
C43024
0.1u
6.3V 0201
SSD
C43010
6.3V
22u
0603
SSD
C43017
6.3V
22u
0603
DNP
C43025
6.3V
22u
0603
SSD
C43011
6.3V
22u
0603
SSD
C43018
6.3V
22u
0603
SSD
C43026
6.3V
22u
0603
GP_SSD_FLUSH[56]
SAM_SSD_FLUSH[27]
SSD_DIAG1[43]
SSD2_DIAG1[44]
4
0201 DNP
MTP43025
SMD RND 22.8mil
R43113499
R43108 200K
0201 DNP
R43106 200K
0201 DNP
R43109 200K
0201 DNP
R43110 200K
0201 DNP
2 1
R43120
4.7K
0201 DNP
R43123
4.7K
0201 DNP
SSD_DIAG0 [43,44]
SSD_FLUSH_DONE [ 27,56]
43. SSD page 1
43. SSD page 1
Title:
Title:
Microsoft Confidential
Microsoft Confidential
Microsoft Confidential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
Custom
Custom
2
U SPECIFIC
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Title:
Engineer:
Engineer:
Engineer:
A
A
A
1
43. SSD page 1
Surface
Surface
Surface
43 79Thursday, April 26, 2018
43 79Thursday, April 26, 2018
43 79Thursday, April 26, 2018
1.0.0.1
1.0.0.1
1.0.0.1
5
Vinafix.com
For common BGA SSDs
SSD_PERST_N[43]
1P8V_SSD
C44118
6.3V
GND
6
VCC
5
NC
Y
SSD2_PCIECLK_REQ_N[20]
C44122
10p25V 0201 DNP
SSD_JTAG_TCK[31,43]
SSD_JTAG_TMS[31,43]
SSD1_JTAG_TDO[43]
SSD2_JTAG_TDO[43]
GTP44004
SMD RND 22.8mil
R44012 0 0402SSD R44013 0 0402SSD
0.22u 0201 6.3V
0.22u 0201 6.3V C44001
SSD
0.22u 0201 6.3V
0.22u 0201 6.3V C44003
SSD
R44126
DNP
R44010 100K
0201_p28mm
1%
GND
SMD RND 22.8mil
SSD2_DIAG1
SSD_DIAG0
SSD_JTAG_TCK
SSD_JTAG_TMS
SSD2_JTAG_TDO
GTP44003
SMD RND 22.8mil
SSD2_SATA_PCIE_DET_N [24 ]
SSD
SSD
0
0201
GTP44001
SSD2_XTAL_OUT
SSD2_XTAL_IN
PCIECLK_SSD2_DP[20] PCIECLK_SSD2_DN[20]
PCIE_SSD2_TX11_DP[24] PCIE_SSD2_TX11_DN[24]
PCIE_SSD2_RX11_DP[24] PCIE_SSD2_RX11_DN[24 ]
PCIE_SSD2_TX12_DP[24] PCIE_SSD2_TX12_DN[24]
PCIE_SSD2_RX12_DP[24]
D D
PCIE_SSD_PERST_N[25,43]
25V
C C
B B
PCIE_SSD2_RX12_DN[24 ]
0201
0.1u
DNP
U44002
1
PLT_RST_BUF_N[22,27,34,38,43,56]
DNP
C44120
10p
0201
SSD2_DIAG1[43]
SSD_DIAG0[43]
3VSUS_ORG
A
2
B
3 4
GND
GND
SN74AUP1G08DRYR
DNP
DNP
R44016 1M
0402
XRCGB25M000F2P00R0
Y44001
31
2 4
DNP
R44125 4 9.9K0201
SSD
R44017 0
0402 SSD
R44125 is loaded for non-RAID case R44017 is loaded for the RAID case
C44121
C44002
U44007A
D4
REFCLK_P
D5
REFCLK_N
F4
SATAmAp/PERp0
F5
SATAmAm/PERn0
H4
SATAmBp/PETp0
H5
SATAmBm/PETn0
K4
PER_P1
K5
PER_N1
M4
PET_P1
M5
PET_N1
P4
PERp2/NC_P4
P5
PERn2/NC_P5
T4
PETp2/NC_T4
T5
PETn2/NC_T5
V4
PERp3/NC_V4
V5
PERn3/NC_V5
Y4
PETp3/NC_Y4
Y5
PETn3/NC_Y5
D7
PERST#
F14
PEDET
D8
CLKREQ#
D14
SUSCLK/NC_D14
E8
DEVSLP/NC_E8
E12
PEWAKE#/NC_E12
W7
LED1#/ DAS
B6
CAL_P/NC_B6
C7
XTAL_ OUT/NC_C7
C8
XTAL_IN/NC_C8
C10
RZQ_1/NC_C10
D13
DIAG1/I2C_DATA
E13
DIAG0/I2C_CLK
L18
JTAG_TRST#/NC_L18
N17
JTAG_ TCK
N18
JTAG_ TMS
R17
JTAG_ TDI
R18
JTAG_ TDO
U17
SMB_ CLK/NC_U17
U18
SMB_ DATA/NC_U18
W18
ALERT#/NC_W18
AA10
RZQ_2/NC_AA10
HFB1M8MO331A0MR
1P2V_SSD2
1P8V_SSD2
3P3V_SSD
4
U44007C
C1
GND_C1
C2
GND_C2
C3
GND_C3
C4
GND_C4
C5
GND_C5
C15
GND_C15
D6
GND_D6
D11
GND_D11
E1
GND_E1
E2
GND_E2
E3
GND_E3
E4
GND_E4
E5
GND_E5
E6
GND_E6
E7
GND_E7
E11
GND_E11
E14
GND_E14
E15
GND_E15
F6
GND_F6
G1
GND_G1
G2
GND_G2
G3
GND_G3
G4
GND_G4
G5
GND_G5
G9
GND_G9
G10
GND_G10
G14
GND_G14
G15
GND_G15
H9
GND_H9
H10
GND_H10
J1
GND_J1
J2
GND_J2
J3
GND_J3
J4
GND_J4
J5
GND_J5
J9
GND_J9
J10
GND_J10
J14
GND_J14
J15
GND_J15
K7
GND_K7
K8
GND_K8
K9
GND_K9
K10
GND_K10
K11
GND_K11
K12
GND_K12
L1
GND_L1
L2
GND_L2
L3
GND_L3
L4
GND_L4
L5
GND_L5
L14
GND_L14
L15
GND_L15
M9
GND_M9
HFB1M8MO331A0MR
GND_M10
GND_N1 GND_N2 GND_N3 GND_N4
GND_N5 GND_N14 GND_N15
GND_P7
GND_P8
GND_P9 GND_P10 GND_P11 GND_P12
GND_R1
GND_R2
GND_R3
GND_R4
GND_R5
GND_R9 GND_R10 GND_R14 GND_R15
GND_T9 GND_T10
GND_U1
GND_U2
GND_U3
GND_U4
GND_U5
GND_U9 GND_U10 GND_U14 GND_U15
GND_W1 GND_W2 GND_W3 GND_W4 GND_W5
GND_W6 GND_W11 GND_W14 GND_W15
GND_Y6 GND_Y11 GND_Y13 GND_AA1 GND_AA2 GND_AA3 GND_AA4 GND_AA5
GND_AA14 GND_AA15
M10 N1 N2 N3 N4 N5 N14 N15 P7 P8 P9 P10 P11 P12 R1 R2 R3 R4 R5 R9 R10 R14 R15 T9 T10 U1 U2 U3 U4 U5 U9 U10 U14 U15 W1 W2 W3 W4 W5 W6 W11 W14 W15 Y6 Y11 Y13 AA1 AA2 AA3 AA4 AA5 AA14 AA15
GTP44002
SMD RND 22.8mil
U44007B
G7
1p2v/1p1v/0p9v/RFU_G7
G8
1p2v/1p1v/0p9v/RFU_G8
G11
1p2v/1p1v/0p9v/RFU_G11
G12
1p2v/1p1v/0p9v/RFU_G12
H7
1p2v/1p1v/0p9v/RFU_H7
H8
1p2v/1p1v/0p9v/RFU_H8
H11
1p2v/1p1v/0p9v/RFU_H11
H12
1p2v/1p1v/0p9v/RFU_H12
J7
1p2v/1p1v/0p9v/RFU_J7
J8
1p2v/1p1v/0p9v/RFU_J8
J11
1p2v/1p1v/0p9v/RFU_J11
J12
1p2v/1p1v/0p9v/RFU_J12
R7
V1P8_R7
R8
V1P8_R8
R11
V1P8_R11
R12
V1P8_R12
T7
V1P8_T7
T8
V1P8_T8
T11
V1P8_T11
T12
V1P8_T12
U7
V1P8_U7
U8
V1P8_U8
U11
V1P8_U11
U12
V1P8_U12
D9
V3P3_D9
D10
V3P3_D10
E9
V3P3_E9
E10
V3P3_E10
W9
V3P3_W9
W10
V3P3_W10
Y9
V3P3_Y9
Y10
V3P3_Y10
HFB1M8MO331A0MR
U44007D
C13
RFU_C13
C14
RFU_C14
D15
RFU_D15
F15
RFU_F15
H14
RFU_H14
H15
RFU_H15
K14
RFU_K14
K15
RFU_K15
L7
RFU_L7
L8
RFU_L8
L9
RFU_L9
L10
RFU_L10
L11
RFU_L11
L12
RFU_L12
M7
RFU_M7
M8
RFU_M8
M11
RFU_M11
M12
RFU_M12
M14
RFU_M14
M15
RFU_M15
N7
RFU_N7
N8
RFU_N8
N9
RFU_N9
N10
RFU_N10
N11
RFU_N11
N12
RFU_N12
P14
RFU_P14
P15
RFU_P15
T14
RFU_T14
T15
RFU_T15
V14
RFU_V14
V15
RFU_V15
W8
RFU_W8
W12
V_SEL0/RFU_W12
W13
V_SEL1/RFU_W13
HFB1M8MO331A0MR
3
DNU_A1 DNU_A2 DNU_A4 DNU_A6
DNU_A8 DNU_A11 DNU_A13 DNU_A15 DNU_A17 DNU_A18
DNU_B1
DNU_B2
DNU_B4
DNU_B8 DNU_B11 DNU_B13 DNU_B15 DNU_B17 DNU_B18
DNU_C6
DNU_C9 DNU_C11 DNU_C12
DNU/DDR_VDDQ
DNU_C17 DNU_C18 DNU_D12 DNU_E16 DNU_E17 DNU_E18 DNU_G16 DNU_G17 DNU_G18
DNU_J16 DNU_J17 DNU_J18 DNU_L16
DNU/JTAG_TRST#
DNU_N16 DNU_R16 DNU_U16
DNU_W16 DNU_W17
DNU/SSD_FLUSH
DNU/SSD_FLUSH_FB
DNU_Y12 DNU_Y14
DNU_Y15 DNU_AA6 DNU_AA7 DNU_AA8 DNU_AA9
DNU_AA11 DNU_AA12 DNU_AA13
DNU_AA16 DNU/UART_RX DNU/UART_TX
DNU_AB1 DNU_AB2 DNU_AB4 DNU_AB6
DNU_AB8 DNU_AB11 DNU_AB13 DNU/VCCF DNU_AB17 DNU_AB18
DNU_AC1
DNU_AC2
DNU_AC4
DNU_AC6
DNU_AC8 DNU_AC11 DNU_AC13 DNU_AC15
DNU/VCCFQ
DNU_AC18
A1 A2 A4 A6 A8 A11 A13 A15 A17 A18 B1 B2 B4 B8 B11 B13 B15 B17 B18 C6 C9 C11 C12 C16 C17 C18 D12 E16 E17 E18 G16 G17 G18 J16 J17 J18 L16 L17 N16 R16 U16 W16 W17 Y7 Y8 Y12 Y14 Y15 AA6 AA7 AA8 AA9 AA11 AA12 AA13 AA16 AA17 AA18 AB1 AB2 AB4 AB6 AB8 AB11 AB13 AB15 AB17 AB18 AC1 AC2 AC4 AC6 AC8 AC11 AC13 AC15 AC17 AC18
GTP44020SMD RND 2 2.8mil
GTP44021SMD RND 2 2.8mil GTP44022SMD RND 2 2.8mil
GTP44024SMD RND 2 2.8mil GTP44025SMD RND 2 2.8mil
GTP44027SMD RND 2 2.8mil
SMD RND 22.8mil
GTP44015
GTP44026SMD RND 2 2.8mil GTP44023SMD RND 2 2.8mil
3P3V_SSD
R44119 100K
1% 0201
GND
V3P3_DSW
V3P3_DSW
R44134 100K
0201
C44190 4.7u
6.3V 0201 DNP
R44118
100K
1% 0201
2
PCIE[12:1]_TXN/P : Gen1 and Gen2 = 75 to 200 nF; where 100 nF is nominal value, Gen3 = 176 to 265 nF; where 220 nF is nominal value
PCIE[12:1]_RXN/P : Gen1 and Gen2 = 75 to 200 nF; where 100 nF is nominal value, Gen3 = 176 to 265 nF; where 220 nF is nominal value
Difference between USB3 and PCIe: 1. No Choke, 2. Add cap on PER (p832 at DG v1.2) RXN/RXP cap value must be different between Gen2 and Gen3 TX (from SOC) caps are at SOC side
Always ON logic, as like Intel RVP5.
SMD RND 22.8mil
TP44007
C44035 22u
4V 20% 0603
R44110 is 165K for Toshiba, 1P2V_SSD = 1.2V +/- 5%
only support Hynix 1TB
SMD RND 22.8mil
TP44006
C44130 22u
4V 20% 0603
3P3V_SSD
R44123 0 0201
C44129 10u
6.3V 0402
C44134 10u
6.3V
0402
0201
GND
0201
C44180
0.1u 6.3V
GND
7
1
5
C44139
0.1u 6.3V
QFN-7
U44006
7
VIN
1
EN
5
GND
QFN-7
U44005
VIN
EN
VOS
GND
TPS62085RLTR
SW
VOS
FB
PG
TPS62085RLTR
6
SW
4
3
FB
2
PG
6
4
3
2
L44101
0.47uH
2.5X2.0X1.2
L44102
0.47uH
2.5X2.0X1.2
R44018
82.5K
1% 0201 DNP
X950133-001
R44107
82.5K
1% 0201
R44108 33K
1% 0201
R44124 33K
1% 0201
X950133-001
R44019 215K
1% 0201 DNP
R44109
C44141
24.9K
1%
100p
0201
25V
SSD
0201 DNP
R44110 is 215K for Samsung, 1P2V_SSD = 1.06V-1.15V + 100mV P-P ripple
R44110 165K
1% 0201 SSD
C44140
100p
25V 0201 DNP
1
C44131 22u
4V 20% 0603
DNP
C44136 22u
4V 20% 0603
SMD RND 22.8mil
MTP44027
C44132 22u
4V 20% 0603
SMD RND 22.8mil
MTP44026
C44137 22u
4V 20% 0603
1P8V_SSD2
C44133 22u
4V 20% 0603
C44138 22u
4V 20% 0603
1P2V_SSD2
R44150 10K
0201 SSD
3P3V_SSD
SSD
SSD
C44107
C44104
6.3V
6.3V
1u
1u
0402
0402
1P8V_SSD2
SSD
SSD
C44028
C44038
6.3V
6.3V
1u
1u
0402
SSD
C44103
6.3V
1u
0402
0402
SSD
C44024
0.1u
6.3V 0201
5
SSD
C44106
0.1u
6.3V 0201
1P2V_SSD2
SSD
C44025
A A
6.3V
1u
0402
SSD
C44105
0.1u
6.3V 0201
SSD
C44115
0.1u
6.3V 0201
SSD
C44113
0.1u
6.3V 0201
SSD
C44026
0.1u
6.3V 0201
SSD
C44109
0.1u
6.3V 0201
SSD
C44112
0.1u
6.3V 0201
SSD
C44108
6.3V
22u
0603
SSD
C44031
6.3V
22u
0603
DNP
C44114
6.3V
22u
0603
SSD
C44030
6.3V
22u
0603
SSD
C44033
6.3V
22u
0603
SSD
C44111
6.3V
22u
0603
44. SSD Page 2
44. SSD Page 2
Title:
Title:
Microsoft Confidential
Microsoft Confidential
Microsoft Confidential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
Custom
Custom
4
3
2
U SPECIFIC
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Title:
Engineer:
Engineer:
Engineer:
A
A
A
1
44. SSD Page 2
Surface
Surface
Surface
44 79Thursday, April 26, 2018
44 79Thursday, April 26, 2018
44 79Thursday, April 26, 2018
1.0.0.1
1.0.0.1
1.0.0.1
5
Vinafix.com
D D
USB3_TYPEA_RX_DN[24]
USB3_TYPEA_RX_DP[24]
USB3_TYPEA_TX_DN[24]
VSYS
USB3_TYPEA_TX_DP[24]
C45015 0.1u 16V
0201
C C
C45016 0.1u 16V
0201
NOTE: power plane split bypass
4
C45001 0.1u 6.3V
0201
C45002 0.1u 6.3V
0201
USB3_CONN_TX_C_DN
USB3_CONN_TX_C_DP
USB2_TYPEA_DP[24] USB2_TYPEA_DN[24]
C2 C1
C2 C1
WLCSP-5
PCMF1USB3S
OUT_1m OUT_1p
WLCSP-5
PCMF1USB3S
OUT_1m OUT_1p
3
GND
IN_1m
IN_1p
U45001
GND
IN_1m
IN_1p
U45002
U45003 IP3319CX6
DP_OA1
B1
DM_O
B1
A2 A1
B1
A2 A1
WLCSP6
USB3_TA_CONN_RX_DN USB3_TA_CONN_RX_DP
USB3_TA_CONN_TX_DN USB3_TA_CONN_TX_DP
DP_I A2 DM_I B2
C2
ID
C1
GND
2
MTTP_BF45002
USB2_TA_CONN_DN USB2_TA_CONN_DP
SMD RND 31.5mil
MTTP_BF45003
SMD RND 31.5mil
MTP_BF45002
SMD RND 31.5mil
MTP_BF45003
SMD RND 31.5mil
5V_USBPWR_A
PESD5V0S1UA D45001
A K
J45001
1
VBUS
2
Dm
3
Dp
4
GND
5
StdA_SSRXm
6
StdA_SSRXp
7
GND_DRAIN
8
StdA_SSTXm
9
StdA_SSTXp
M1015489-001
USERPORTS
1
MTG12 MTG11 MTG10
MTG9 MTG8 MTG7 MTG6 MTG5 MTG4 MTG3 MTG2 MTG1
21 20 19 18 17 16 15 14 13 12 11 10
C45020 is located outside shield
C45013
C45017 10u
6.3V
B B
V5A
C45003 1u6.3V
0201
A A
USB_CONN_OC_N[24]
R45010
49.9K
0201
SKL_SLP_S4_N[22,27,34,59,61]
5V_USB_EN[25]
5
DNP
R45007 10K
0201
R45009 499
0201
4
0402
0.01u
10V 0201
U45004
6
IN
3
FAULT
4
EN
5
GND
7
GNDPAD
AP2553FDC-7R
+
C45020
150uF
1210
OUT
ILIM
6V
1
ALL
C45014
2
14.7K R45008 200K
0201
R45005
0201
14.7K Sets:
MTP_BF45004
0.1u
10V 0201
SMD RND 31.5mil
MTTP_BF45004
5V_USBPWR_A
MTP_BF45001
SMD RND 31.5mil
MTTP_BF45001
SMD RND 31.5mil
Min: 1.64A Typ: 1.8A Max: 1.9A
3
SMD RND 31.5mil
MTP_BF45005
SMD RND 31.5mil
2
45. USB3.0, TYPE A
45. USB3.0, TYPE A
Title:
Title:
Microsoft Confidential
Microsoft Confidential
Microsoft Confidential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
B
B
B
Date: Sheet of
Date: Sheet of
Date: Sheet of
A
A
A
Title:
Engineer:
Engineer:
Engineer:
45. USB3.0, TYPE A
Surface
Surface
Surface
45 79Tuesday, May 01, 2018
45 79Tuesday, May 01, 2018
1
45 79Tuesday, May 01, 2018
1.0.0.1
1.0.0.1
1.0.0.1
5
Vinafix.com
4
3
2
1
SL1 DP mux to HDMI/DVI Dongle control
MTP46008
D D
V3P3_DSW V3P3_DSW
R46003
2.2K
0201
DDPC_CTRL_DATA[10]
R46006
2.2K
0201
PI3USB102GZLEX
EN
C C
L L H
S
L H
X
Connection
AUX for DP [D1 to D] DDC for HDMI [D2 to D]
HI-Z
MTP46007
SP_TP_SMDp58mm
MTP46006
SP_TP_SMDp58mm
SL_DDI2_AUX_DN[10]
SL_DDI2_AUX_DP[10]
SL_CONFIG1[47]
C46004 0.1u 6.3V
0201
C46001 0.1u 6.3V
0201
C46003
0.1u
25V 0201
GND GND
SLMUX_AUX_DN
SLMUX_AUX_DP
SP_TP_SMDp58mm
MTP46005
SP_TP_SMDp58mm
MTP46004
SP_TP_SMDp58mm
U46001
5
M+
7
D+
4
M-
6
D-
10
SEL
8
OE
PI3USB102GZLEX
VDD
Y+
GND
V3P3_DSW
V3P3_DSW
9
1
2
Y-
3
GND
C46002
0.1u 6.3V
0201
GND
R46001 100K
0201
R46002 100K
0201
MTP46003
SP_TP_SMDp58mm
MTP46009
SP_TP_SMDp58mm
SL_DDC_AUX_DN [47]
SL_DDC_AUX_DP [47]DDPC_CTRL_CLK[10]
GND
3P3VA_SW
R46007 100K
MTP46002
SMD RND 22.8mil
B B
SL_3P3V_DIS[27]
R46010 100K
0201
G
0201
3P3V_HDP_EN
D
Q46001 RUM002N02GT2L
SOT-VMT3_1p2xp8xp5_p4mm
S
GNDGND
3P3VA_SW
GND
SL1 3P3V HPD power rail
3P3V_HPD
C46006 10u 6.3V
0402
GND
R46008 20K
0201
U46002
A1
VIN_A1
B1
VIN_B1
C3
ON
C2
ISET
FPF2495UCX
VOUT_A3 VOUT_B3
OCFLAGB
GND_A2 GND_B2
3P3V_HPD
A3 B3
C1
A2 B2
GND
GND
C46005 1u 25V
0603
GND
R46012 200K
0201
R46011
100
0201
MTP46001
SP_TP_SMDp58mm
SL_HPD2 [47]
D46001 PESD24VS1UL
DIO-ESD,SM,PESD24VS1UL,24 V,50 pF,1X.6X.5
A K
A A
46. SL HDMI MUX/3P3V_HPD
46. SL HDMI MUX/3P3V_HPD
Title:
Title:
Title:
Engineer:
Engineer:
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
B
B
B
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
A
A
A
Engineer:
46. SL HDMI MUX/3P3V_HPD
Surface
Surface
Surface
1.00
1.00
1.00
46 76Thursday, April 26, 2018
46 76Thursday, April 26, 2018
1
46 76Thursday, April 26, 2018
5
Vinafix.com
MTP47004
SMD RND 22.8m il
SL_DDC_AUX_D P[46] SL_DDC_AUX_D N[46]
SD_DEBUG1[31] SD_DEBUG3[31]
SAM_SL_DBG_EN[29]
D D
R47008 100K
GND
GP_DBGACC[29,31,56]
USB3_SL_RX_DN[24]
USB3_SL_RX_DP[24]
USB3_SL_TX_DN[24]
USB3_SL_TX_DP[24]
SL_DDI2_ML3_DN[10]
SL_DDI2_ML3_DP[10]
C C
SL_DDI2_ML2_DN[10]
SL_DDI2_ML2_DP[10]
SL_DDI2_ML1_DN[10]
SL_DDI2_ML1_DP[10]
B B
SL_DDI2_ML0_DN[10]
SL_DDI2_ML0_DP[10]
R47020 499
NDEBUG_GP
U47013
VCC
2 1
Y
A B
GND
74LVC1G32GX
DEBUG_GP
C47005 0.1u 6.3V
C47002 0.1u 6.3V
3P3VA
5 4
3
GND
GND
USB3_SL_TX_C_DN
USB3_SL_TX_C_DP
S=0 => D1 <-> D S=1 => D2 <-> D
U47008
5
M+
7
D+
4
M-
6
D-
10
SEL
8
OE
PI3USB102GZLEX
X936286-001 10-WFQF N DEBUG_SL
SL_DBG_EN [47]
MTP47005
SMD RND 22.8m il
M71L47002
100mA
DLP11TB800UL2L
ex-ind4_1P25X1XP35_1p2xp55mm
M71L47003
100mA
DLP11TB800UL2L
ex-ind4_1P25X1XP35_1p2xp55mm
RN47001
1
4
DLP11TB800UL2L
DLP11TB800UL2L
4
1
RN47002
DLP11TB800UL2L
4
1
RN47003
DLP11TB800UL2L
4
1
RN47004
VDD
GND
3
2
3
2
2
3
3
2
3
2
3P3VA
9
1
Y+
2
Y-
3
GND
SL_LANE3_R_DN
SL_LANE3_R_DP
SL_LANE2_R_DN
3
SL_LANE2_R_DP
2
SL_LANE1_R_DN
SL_LANE1_R_DP
SL_LANE0_R_DN
SL_LANE0_R_DP
4
C47004
0.1u 6.3V
DEBUG_SL
GND
USB3_SL_RX_R_DN
4
USB3_SL_RX_R_DP
1
USB3_SL_TX_R_DN
4
USB3_SL_TX_R_DP
1
R47009 0
R47010 0
0201NDEBU G_SL
0201NDEBU G_SL
U47003 IP3319CX6
SL_DBG3_AUX_DN SL_DBG1_AUX_DP SL_DBG1_AUX_R_DP
MTP47006
SMD RND 22.8m il
MTP47007
SMD RND 22.8m il
GND GND
bga6_2x3ns_p95x1p34xp6_p4mm
DP_OA1
B1
DM_O
2
GND
DF5G7M2NU47007
IO11IO23IO34IO5
dfn5_1p3xp8xp4_p45mm
5
GND GND
2
GND
DF5G7M2NU47006
IO11IO23IO34IO5
dfn5_1p3xp8xp4_p45mm
5
DP_I A2 DM_I B2
C2
ID
C1
GND
2
GND
IO11IO23IO34IO5
3
SL_DBG3_AUX_R_DN
GND
2
GND
DF5G7M2NU47009
IO11IO23IO34IO5
DF5G7M2NU47004
dfn5_1p3xp8xp4_p45mm
5
dfn5_1p3xp8xp4_p45mm
5
SMD RND 22.8m il
SMD RND 22.8m il
SL_LANE2_R_DN SL_LANE2_R_DP
SL_LANE1_R_DN SL_LANE1_R_DP
SL_LANE0_R_DN SL_LANE0_R_DP
SMD RND 22.8m il
MTP_BF47007
SMD RND 31.5m il
MTP_BF47008
SMD RND 31.5m il
MTP_BF47009
SMD RND 31.5m il
MTP_BF47010
SMD RND 31.5m il
MTP_BF47011
SMD RND 31.5m il
MTP_BF47012
SMD RND 31.5m il
MTP47001
SL_HPD1A[69]
SL_DBG2_DP_HPD_C ON SAM_DEBUG_RX D_CON
SL_HPD2[46,47]
MTP47002
SL_HPD2[46,47]
SL_HPD1B[69]
SL_DBG3_AUX_R_DN SL_DBG1_AUX_R_DP
SAM_DEBUG_TXD_ CON
SL_DBG4_CONFIG 1_CON
MTP47003
2
PWR_SL
MTP_BF47001
SMD RND 31.5m il
MTP_BF47002
SMD RND 31.5m il
MTP_BF47003
SMD RND 31.5m il
MTP_BF47004
SMD RND 31.5m il
MTP_BF47005
SMD RND 31.5m il
MTP_BF47006
SMD RND 31.5m il
GND
USB3_SL_RX_R_DP USB3_SL_RX_R_DN
USB3_SL_TX_R_DP USB3_SL_TX_R_DN
SL_LANE3_R_DP SL_LANE3_R_DN
USB2_SL_DP_R USB2_SL_DN_R
MTTP_BF47006
SMD RND 31.5m il
MTTP_BF47001
SMD RND 31.5m il
MTTP_BF47002
SMD RND 31.5m il
MTTP_BF47003
SMD RND 31.5m il
MTTP_BF47004
SMD RND 31.5m il
MTTP_BF47005
SMD RND 31.5m il
J47001 20525-040E-02
conn_fpc-r_40_12mtg_21p2x4p15x1p1_p4mm
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
MTG1
42
MTG2
43
MTG3
44
MTG4
45
MTG5
46
MTG6
47
MTG7
48
MTG8
49
MTG9
50
MTG10
51
MTG11
52
MTG12
X908351-001
1
GND
MTTP_BF47012
SMD RND 31.5m il
MTTP_BF47008
SMD RND 31.5m il
MTTP_BF47009
SMD RND 31.5m il
MTTP_BF47007
SMD RND 31.5m il
MTTP_BF47010
SMD RND 31.5m il
MTTP_BF47011
SMD RND 31.5m il
3P3VA
C47001
0.1u6.3V
DEBUG_SL
SL_SNK0_HPD[10]
SL_CONFIG1[46]
A A
5
R47007 100K
0201
R47006 1M
0201
SD_DEBUG2[31]
SD_DEBUG4[31]
SL_DBG_EN[47]
R47004 499K
DEBUG_SL
GND
Mode SD_DEBUG3 SD_DEBUG1 SD_DEBUG4 SD_DEBUG2 PCH logging PCH_UART0_RXD PCH_UART0_TXD SAM_PCH_UART_RX SAM_PCH_UART_TX
B3
4
U47011
QFN10_1P4X1P8XP55_P4MM
5 2 4
7
10
8
1
6
GND
BF 2 board compatability Motherboard Mux Settings
S1A S1B SEL1
S2A S2B SEL2
VCC
GND
TS3A5223
X873777-001 DEBUG_SL
R47011 0
R47012 0
SAM_DEBUG_R_RX[31] SAM_DEBUG_R_TX[31]
OUT1
OUT2
SL_DBG4_CONFIG1_CON
SAM_DEBUG_RXD_CON
SL_DBG2_DP_HPD_CON
U47001 IP4252CZ8-4
dfn9_1p7x1p35xp55_p4mm
1
I1
I
2
3
SL_DBG2_DP_HPD SL_DBG4_CONFIG 1
I2
3
I3
4
I4
GND PAD
9
MTP47008
SMD RND 22.8m il
MTP47009
SMD RND 22.8m il
0201NDEBUG _SL
0201NDEBUG _SL
3
O
GND
8
O1
7
O2
6
O3
5
O4
9
GND
USB2_SL_DN[24] USB2_SL_DP[24]
SAM_DEBUG_TXD_CON
U47010 IP3319CX6
bga6_2x3ns_p95x1p34xp6_p4mm
DM_O
B1
DP_OA1
GND
GND
ID
DM_I B2 DP_I A2
C1
C2
USB2_SL_DN_R USB2_SL_DP_R
2
DVi7U7660s16s512x2Retai l
DVi7U7660s16s512x2Retai l
DVi7U7660s16s512x2Retai l
47. SurfLink Connector
47. SurfLink Connector
Title:
Title:
Title:
Microsoft Conf idential
Microsoft Conf idential
Microsoft Conf idential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
Engineer:
Engineer:
Engineer:
A
A
A
47. SurfLink Connector
47 XXThursday, April 26, 2018
47 XXThursday, April 26, 2018
1
47 XXThursday, April 26, 2018
1.0.0.1
1.0.0.1
1.0.0.1
5
Vinafix.com
MTP48008
MTP48009
MTP48010
KBTP CONNECTOR
4
MTP48011
MTP48012
3
2
1
Pin1 Top Left
J48001
PINS REVERSED
I2C_SCL_TP[25,31,48]
D D
TRACKPAD_INT_N_R2[48]
SAM_KIP_RST[27,3 1]
SAM_KIP_UART_TX[28]
PWR_SW_N[56]
D48004PESD3V3U1UL315
A K
D48009PESD3V3U1UL315
A K
DNP
DNP
D48011P ESD3V3U1UL315
A K
DNP
D48010P ESD3V3U1UL315
DNP
D48008P ESD3V3U1UL315
A K
A K
DNP
2
2
4
4
6
6
8
8
10
10
12
12
14
MTG2
16
MTG4
WP6-S012VA2
X930301-001
MTG1 MTG3
1
1
3
3
5
5
7
7
9
9
11
11
13 15
D48012PESD3V3U1UL315
DNP
D48002PESD3V3U1UL315
D48005
DNP
D48003
A K
A K
PESD3V3U1UL315
DNP
PESD3V3U1UL315
A K
A K
DNP
I2C_SDA_TP [25,31,48]
KIP_SWD_CLK [31]
KIP_SWD_DIO [3 1]
KIP_IO [27 ,29,31]
SAM_KIP_UART_RX [29]
MTP48002
TP48002
D48006
PESD5V0F1USF31 5
5v0_OFFBOARD
MTP48006
I2C_SDA_TP [25,31,48]
A K
MTP48007
I2C_SCL_TP [25,31,48]
R48003
C C
TRACKPAD_INT_N_R2[48]
0 0 201
C48004 100p
0201 25V
PLACE CLOSE TO K22 (U1) Cap for filtering crosstalk. Tune in EV2B to find proper value Current reco.: 100pF
TRACKPAD_INT_N [1 0,27]
OEM Trackpad = 010 0000 + R/W bit
(7-bit address + R/W bit) Write = 0, Read = 1
3VSUS_ORG
100K
R48031
0201
C48011
6.3V
10u
0402
KPTP_FAULT_N [25]
V5A
49.9K R48030
0201
5v0_OFFBOARD
U48002
6
B B
SAM_KBTP_PWR[27]
C48014 1u 6.3V
0201
100K
0201
R48028
IN
3
FAULT
4
EN
5
GND
7
GNDPAD
AP2553FDC-7R
OUT
ILIM
1
2
A A
48. Blade
48. Blade
Title:
Title:
Microsoft Co nfidential
Microsoft Co nfidential
Microsoft Co nfidential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
4
3
2
Title:
Engineer:
Engineer:
Engineer:
A
A
A
48. Blade
Surface
Surface
Surface
1.0.0.1
1.0.0.1
48 79Thursday, April 26, 2018
48 79Thursday, April 26, 2018
48 79Thursday, April 26, 2018
1
1.0.0.1
5
Vinafix.com
TPANEL_RST_N[25,49]
D D
3VSUS_ORG
R49029
100K
3
D
Q49007
NX3008NBKMB315
C C
R49024
200K
DNP
MTP49042 MTP49014 C49078 100p020 1
MTP49027 MTP49008
MTP49016 MTP49022 MTP49023 MTP49017
MTP49024 MTP49025 MTP49018 MTP49019
B B
MTP49015
TS_TCK_1V8[31,49] TS_TDI_1V8[31,49]
TS_TDO_1V8[31,49]
TS_TMS_1V8[31,49]
1P8V_TS
G
1
s
2
FLASH_PROTECT_N
TPANEL_RST_N
FLASH_PROTECT_N
TS_TCK_1V8 TS_TMS_1V8 TS_TDO_1V8 TS_TDI_1V8
TS_SPI_CLK TS_SPI_MISO TS_SPI_MOSI TS_SPI_CS_N
FLASH_PROTECT_N[20,49]
R49030 10K
XTAL-XTAL,SM,48 MHZ,15 PPM,7 PF,2X1.6X0.155MM
5V_TS
TS_SPI_CLK[21,49]
TS_SPI_MOSI[21,49]
TS_SPI_MISO[21,49]TS_IRQ_3V3_N[10] TS_SPI_CS_N[21,49]
FLASH_PROTECT_N
GPIO signals may toggle during boot (see errata document). Please make sure to implement the workaround
TS_TCK_1V8 TS_TDI_1V8 TS_TDO_1V8 TS_TMS_1V8
1P8V_TS
described in the errata
TS_HOST_CLK
R49019 200K
The crystal and capacitors should be placed as close as possible to the D5, with short and symmetrical traces to the XI and XO pins
FLASH_PROTECT_N [20,49]
TPANEL_RST_N [25,49] FLASH_PROTECT_N [20,49]
TS_TCK_1V8 [31,49] TS_TMS_1V8 [31,49] TS_TDO_1V8 [31,49] TS_TDI_1V8 [31,49]
TS_SPI_CLK [21,4 9] TS_SPI_MISO [21,49] TS_SPI_MOSI [21,49] TS_SPI_CS_N [21,49]
TS_SPI_CLK
TS_SPI_MOSI
TS_SPI_MISO TS_SPI_CS_N
R49014 22.1
R49016 1K
R49017 22.1
0201
(If Availible)
123
C49016
12p25V2%
MTP49049
MTP49051
Not to be used for DEBUG build Use MTP points on pg 31 instead
GTP49003MTP49048
4
R49015
0201
Y49001
TS_DLITE_XO
48MHz
C49017
12p25V2%
TS_JTAG_TS_TDO_R
0
TPANEL_RST_N
C49006 2.2u
C49063 0.1u
C49064 100p
TS_SPI_CLK
TS_SPI_MOSI
TS_TOUCH_SPI_DO_R
TS_GPIO0
TS_IRQ_1V8
TS_FLASH_PROTECTn_GPIO_R
TS_DLITE_XI
TS_DLITE_XO_R
TS_FLASH_CSn
TS_FLASH_SCK
TS_FLASH_MISO
TS_FLASH_MOSI
C49004 2.2u
C49059 0.1u
C49060 100p
TS_V1P0_TCH_SSI
6.3V
U49001
F2
SPI_CLK/I2C_SCL
F4
SPI_DI / I2C_SDA
F3
GPIO7 / SPI_DO
G1
GPIO6 / SPI_CS
D4
GPIO0
D3
GPIO1 / INT
D2
GPIO2 / IF_SEL
C1
GPIO3
C2
GPIO4
B1
GPIO5
H2
GPIO9
H1
GPIO10
G2
GPIO11
H5
TCK
H6
TDI
G6
TDO
F6
TMS
J3
CLK_IN
H11
XI
J11
XO
F10
CLK_SLCT
G5
FSCK
H3
FSDI
G4
FSDIO
H4
FSCS
DS-D5000-B064
MTP49040 MTP49041 MTP49044 MTP49045 MTP49046
TS_V1P0_TCH_DIG
U49003
son9_4x4xp6_p8mm
1
CS
6
CK
5
SI/0
2
Q/1
3
WP/2
7
HLRS/3
MX25U1635FZUI
50 pin Drive Connector
J49002
1
TS_AY1_ANT_HV1
H1 H2
TS_AY1_ANT_HV3
H3
TS_AY1_ANT_HV5
H5
TS_AY1_ANT_HV7
H7 H9 H11
TS_AY1_ANT_HV13
H13
TS_AY1_ANT_HV15
H15
TS_AY1_ANT_HV17
H17
TS_AY1_ANT_HV19
H19
TS_AY1_ANT_HV21
H21
TS_AY1_ANT_HV23
H23
TS_AY2_ANT_HV1
H25
TS_AY2_ANT_HV3
H27
TS_AY2_ANT_HV5
H29
TS_AY2_ANT_HV7
H31
TS_AY2_ANT_HV9
H33
TS_AY2_ANT_HV11
H35
TS_AY2_ANT_HV13
H37
TS_AY2_ANT_HV15
H39
TS_AY2_ANT_HV17
H41
TS_AY2_ANT_HV19
H43
TS_AY2_ANT_HV21
H45
TS_AY2_ANT_HV23
H47
A A
V48
1
3
3
5
5
7
7
9
9 111112 131314 151516 171718 191920 212122 232324 252526 272728 292930 313132 333334 353536 373738 393940 414142 434344 454546 474748 494950
51
MTG1
53
MTG3
5024265010
MTG2 MTG4
2 4 6 8
10
TS_AY1_ANT_HV0
2
TS_AY1_ANT_HV2
4
TS_AY1_ANT_HV4
6
TS_AY1_ANT_HV6
8
TS_AY1_ANT_HV8
10
TS_AY1_ANT_HV10TS_AY1_ANT_HV9
12
TS_AY1_ANT_HV12TS_AY1_ANT_HV11
14
TS_AY1_ANT_HV14
16
TS_AY1_ANT_HV16
18
TS_AY1_ANT_HV18
20
TS_AY1_ANT_HV20
22
TS_AY1_ANT_HV22
24
TS_AY2_ANT_HV0
26
TS_AY2_ANT_HV2
28
TS_AY2_ANT_HV4
30
TS_AY2_ANT_HV6
32
TS_AY2_ANT_HV8
34
TS_AY2_ANT_HV10
36
TS_AY2_ANT_HV12
38
TS_AY2_ANT_HV14
40
TS_AY2_ANT_HV16
42
TS_AY2_ANT_HV18
44
TS_AY2_ANT_HV20
46
TS_AY2_ANT_HV22
48 50
52 54
H0 to H47 are the horizontal sensor traces V0 to V71 are the vertical sensor lines
H0
H4 H6 H8 H10 H12 H14 H16 H18 H20 H22 H24 H26 H28 H30 H32 H34 H36 H38 H40 H42 H44 H46
V1 V0 V3 V5 V7 V9 V11 V13 V15 V17 V19 V21 V23 V25 V27 V29 V31 V33 V35 V37 V39 V41 V43 V45 V47 V49 V51 V53 V55 V57 V59 V61 V63 V65 V67 V69 V71
50 pin Flex Breakout
5
4
1P8V_TS
6.3V
1P8V_TS
VCC
MTG
VSS
C49008 2.2u
6.3V
C49061 0.1u
C49062 100p
C49085 10u
C49005 2.2u
6.3V
C49065 0.1u
C49066 100p
B8
F11
G3
F5
RESERVED_GND[0] RESERVED_GND[1] RESERVED_GND[2]
VDE_F
VDE_H
VDD_CORE
8
9 4
RESERVED_GND[3] RESERVED_GND[4] RESERVED_GND[5] RESERVED_GND[6] RESERVED_GND[7] RESERVED_GND[8] RESERVED_GND[9]
RESERVED_NC[0] RESERVED_NC[1] RESERVED_NC[2] RESERVED_NC[3] RESERVED_NC[4] RESERVED_NC[5] RESERVED_NC[6]
GND1B9GND2
J2
C49019
2.2u 16V
VDD_SSI
D6 B4 D5 C5 B5 C6 B6 C3 C4 B3
D8 J10 H10 J9 H9 J8 H8
TS_AY_RSTN_D
J1
RSTN_D
VDD_OK_F
RSTN
SCKL
SD10 SD11
Special keepout made to isolate buck and boost ground from system ground
SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9
1P8V_TS
TS_VDD_OK_F
J5
TS_VDD_OK_H
B2
G10
TS_SD0 TS_SD0
B10
TS_SD1 TS_SD1
B11
TS_SD2 TS_SD2
C9
TS_SD3 TS_SD3
C10
TS_SD4
C11
TS_SD5
C8
TS_SD6
D9
TS_SD7
D10
TS_SD8
F8
TS_SD9
G8
TS_SD10
F9
TS_SD11
G9
X950113-001
L49003
0.47uH
0805
6.3V
C4905210u
0603
80 pin Sense Connector
J49003
1
1
3
TS_AY2_ANT_LV6 TS_AY2_ANT_LV4 TS_AY2_ANT_LV2
TS_AY2_ANT_LV14 TS_AY2_ANT_LV12 TS_AY2_ANT_LV10 TS_AY2_ANT_LV8 TS_AY2_ANT_LV22 TS_AY2_ANT_LV20 TS_AY2_ANT_LV18 TS_AY2_ANT_LV16 TS_AY1_ANT_LV22 TS_AY1_ANT_LV23 TS_AY1_ANT_LV20 TS_AY1_ANT_LV21 TS_AY1_ANT_LV18 TS_AY1_ANT_LV19 TS_AY1_ANT_LV16 TS_AY1_ANT_LV17 TS_AY1_ANT_LV14 TS_AY1_ANT_LV12 TS_AY1_ANT_LV10 TS_AY1_ANT_LV8 TS_AY1_ANT_LV6 TS_AY1_ANT_LV4 TS_AY1_ANT_LV2 TS_AY1_ANT_LV0 TS_AY0_ANT_LV6 TS_AY0_ANT_LV4 TS_AY0_ANT_LV2 TS_AY0_ANT_LV0 TS_AY0_ANT_LV14 TS_AY0_ANT_LV12 TS_AY0_ANT_LV10 TS_AY0_ANT_LV8 TS_AY0_ANT_LV22 TS_AY0_ANT_LV20 TS_AY0_ANT_LV18 TS_AY0_ANT_LV16
5
7
9
51 53 55 57 59 61 63 65 67 69 71 73 75 77 79
81 83
3 5 7 9 111112 131314 151516 171718 191920 212122 232324 252526 272728 292930 313132 333334 353536 373738 393940 414142 434344 454546 474748 494950 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79
MTG1 MTG3
MTG2 MTG4
5024268010
2 4 6 8
10
52 54 56 58 60 62 64 66 68 70 72 74 76 78 80
2 4
TS_AY2_ANT_LV7
6
TS_AY2_ANT_LV5
8
TS_AY2_ANT_LV3
10
TS_AY2_ANT_LV1TS_AY2_ANT_LV0
12
TS_AY2_ANT_LV15
14
TS_AY2_ANT_LV13
16
TS_AY2_ANT_LV11
18
TS_AY2_ANT_LV9
20
TS_AY2_ANT_LV23
22
TS_AY2_ANT_LV21
24
TS_AY2_ANT_LV19
26
TS_AY2_ANT_LV17
28 30 32 34 36
TS_AY1_ANT_LV15
38
TS_AY1_ANT_LV13
40
TS_AY1_ANT_LV11
42
TS_AY1_ANT_LV9
44
TS_AY1_ANT_LV7
46
TS_AY1_ANT_LV5
48
TS_AY1_ANT_LV3
50
TS_AY1_ANT_LV1
52
TS_AY0_ANT_LV7
54
TS_AY0_ANT_LV5
56
TS_AY0_ANT_LV3
58
TS_AY0_ANT_LV1
60
TS_AY0_ANT_LV15
62
TS_AY0_ANT_LV13
64
TS_AY0_ANT_LV11
66
TS_AY0_ANT_LV9
68
TS_AY0_ANT_LV23
70
TS_AY0_ANT_LV21
72
TS_AY0_ANT_LV19
74
TS_AY0_ANT_LV17
76 78 80
82 84
80 pin Flex Breakout
4
R49018 22.1
6.3V
C4902110u
0603
6.3V
C4902010u
0603
MTP49038
TS_V1P0_TCH_SSI
C49032
4.99K
TS_SCKLTS_SCKL0
TS_V1P8A
V1P8 Analog
V2 V4 V6 V8 V10 V12 V14 V16 V18 V20 V22 V24 V26 V28 V30 V32 V34 V36 V38 V40 V42 V44 V46 V48 V50 V52 V54 V56 V58 V60 V62 V64 V66 V68 V70
0402
MTP49032
5V_TS
C49068
0.1u
0201
C49035
0.1u
16V
3
MTP49035
TS_HV_IN
C49001
25V
10u
0603
C49036 100p
C49069 100p
0201
3
TS_BOOST_HV_IN TS_HV_IN
TS_BOOST_HV_IN
TS_HV_IN
C49002
2.2u 2 5V
0402
L49001
2.0X1.6X1.0MM
0805
C49013
0.1u
0201
MTP49047
TS_SCKL TS_SD0 TS_SD4 TS_SD8
C49018
2.2u 2 5V
0402
TS_VDD_OK_H TS_AY_RSTN_D
C49026
2.2u 25V
0402
TS_VDD_OK_H TS_AY_RSTN_D
TS_BOOST_HV_IN
1.4A
C49007 10u
TS_V1P0_TCH_SSI
C49010 4.7u 040 2 C49011 2.2u 0402
C49070 0.1u 020 1 C49058 100p020 1
C49012 2.2u 040 2 C49071 0.1u 020 1 C49072 100p020 1
C49014 0.033u
C49015 0.033u
1P8V_TS
TS_V1P0_TCH_SSI
C49033 2.2u 040 2 C49075 0.1u 020 1 C49074 100p020 1
C49022 2.2u 040 2 C49076 0.1u 020 1 C49057 100p020 1
C49023 2.2u 040 2 C49077 0.1u 020 1
C49024 0.033u 0201
C49025 0.033u 0201
1P8V_TS
C49034 2.2u 040 2 C49080 0.1u 020 1 C49081 100p020 1
C49028 2.2u 040 2 C49056 0.1u 020 1 C49082 100p020 1
C49029 2.2u 040 2 C49083 0.1u 020 1 C49084 100p020 1
C49087 10u 060 3
C49030 0.033u 0201
C49031 0.033u 0201
C49003
10u6.3V
0603
TS_V1P0_TCH_DIG
L49002 4 .7uH
C49009 10u 6.3V
0603
TS_V1P8A
TPANEL_RST_N
MTP49003 MTP49004 MTP49005 MTP49006
TS_HV_IN
TS_HV_IN
TS_V1P8A
TS_HV_IN
TS_HV_IN
TS_V1P0_TCH_SSI
TS_V1P8A
2.2uH
A K
PMEG4015EPK315
C49067
0.1u
25V 0201
TS_HV_IN
TS_BOOST_HV_IN
0603
TS_AYALON1_LVDCDC_LX
TS_V1P8A
0201
0201
TPANEL_RST_N
TS_AY_RSTN_D
TS_VDD_OK_F TS_VDD_OK_H
TS_SCKL
TS_HV_IN
C49073
0.1u
25V 0201
TS_SCKL
TS_SD4 TS_SD5 TS_SD6 TS_SD7
TS_HV_IN
C49079
0.1u
25V 0201
TS_SCKL
TS_SD8 TS_SD9 TS_SD10 TS_SD11
D49001
1P8V_TS
1P8V_TS
1P8V_TS
C49055 100p
0201
D4
C8
H3 G3
M6
M5
C49054
100p
0201
D4
C8
H3 G3
M6
M5
C49053
100p
0201
D4
C8
H3 G3
M6
M5
TS_HV_IN
E3
A2
A1
B1
B8 A7
A8 B7
B5
J3
F3
L5
B2
K5 A3
A6
A5 B4 B3 A4
B6
E3
A2
A1
B1
B8 A7
A8 B7
B5
J3
F3
L5
B2
K5 A3
A6
A5 B4 B3 A4
B6
E3
A2
A1
B1
B8 A7
A8 B7
B5
J3
F3
L5
B2
K5 A3
A6
A5 B4 B3 A4
B6
U49002
HV_IN
BOOST_HV_OUT
BOOST_HV_IN
BOOST_VSS
BUCK_1V8_IN BUCK_VSS
BUCK_OUT_FB BUCK_LX
VDD_SSI
LDO_1V0_OUT
VDD_1V8_IN
AVDD_IN
AVDD_1V8_3 AVDD_1V8_2 AVDD_1V8_1
VDE_H
VDE_F
RSTN_H RSTN_D VDD_OK_F VDD_OK_H
SCLK
A5_SSI_D0 A5_SSI_D1 A5_SSI_D2 A5_SSI_D3
GND
DS-A5048_82BGA
U49004
HV_IN
BOOST_HV_OUT
BOOST_HV_IN
BOOST_VSS
BUCK_1V8_IN BUCK_VSS
BUCK_OUT_FB BUCK_LX
VDD_SSI
LDO_1V0_OUT
VDD_1V8_IN
AVDD_IN
AVDD_1V8_3 AVDD_1V8_2 AVDD_1V8_1
VDE_H
VDE_F
RSTN_H RSTN_D VDD_OK_F VDD_OK_H
SCLK
A5_SSI_D0 A5_SSI_D1 A5_SSI_D2 A5_SSI_D3
GND
DS-A5048_82BGA
U49005
HV_IN
BOOST_HV_OUT
BOOST_HV_IN
BOOST_VSS
BUCK_1V8_IN BUCK_VSS
BUCK_OUT_FB BUCK_LX
VDD_SSI
LDO_1V0_OUT
VDD_1V8_IN
AVDD_IN
AVDD_1V8_3 AVDD_1V8_2 AVDD_1V8_1
VDE_H
VDE_F
RSTN_H RSTN_D VDD_OK_F VDD_OK_H
SCLK
A5_SSI_D0 A5_SSI_D1 A5_SSI_D2 A5_SSI_D3
GND
DS-A5048_82BGA
2
RESERVED_GND1 RESERVED_GND2 RESERVED_GND3
Add underfill
RESERVED_GND1 RESERVED_GND2 RESERVED_GND3
Add underfill
RESERVED_GND1 RESERVED_GND2 RESERVED_GND3
Add underfill
2
ANT_HV0 ANT_HV1 ANT_HV2 ANT_HV3 ANT_HV4 ANT_HV5 ANT_HV6 ANT_HV7 ANT_HV8
ANT_HV9 ANT_HV10 ANT_HV11 ANT_HV12 ANT_HV13 ANT_HV14 ANT_HV15 ANT_HV16 ANT_HV17 ANT_HV18 ANT_HV19 ANT_HV20 ANT_HV21 ANT_HV22 ANT_HV23
ANT_LV0 ANT_LV1 ANT_LV2 ANT_LV3 ANT_LV4 ANT_LV5 ANT_LV6 ANT_LV7 ANT_LV8
ANT_LV9 ANT_LV10 ANT_LV11 ANT_LV12 ANT_LV13 ANT_LV14 ANT_LV15 ANT_LV16 ANT_LV17 ANT_LV18 ANT_LV19 ANT_LV20 ANT_LV21 ANT_LV22 ANT_LV23
RESERVED_NC1 RESERVED_NC2 RESERVED_NC3
ANT_HV0 ANT_HV1 ANT_HV2 ANT_HV3 ANT_HV4 ANT_HV5 ANT_HV6 ANT_HV7 ANT_HV8
ANT_HV9 ANT_HV10 ANT_HV11 ANT_HV12 ANT_HV13 ANT_HV14 ANT_HV15 ANT_HV16 ANT_HV17 ANT_HV18 ANT_HV19 ANT_HV20 ANT_HV21 ANT_HV22 ANT_HV23
ANT_LV0 ANT_LV1 ANT_LV2 ANT_LV3 ANT_LV4 ANT_LV5 ANT_LV6 ANT_LV7 ANT_LV8
ANT_LV9 ANT_LV10 ANT_LV11 ANT_LV12 ANT_LV13 ANT_LV14 ANT_LV15 ANT_LV16 ANT_LV17 ANT_LV18 ANT_LV19 ANT_LV20 ANT_LV21 ANT_LV22 ANT_LV23
RESERVED_NC1 RESERVED_NC2 RESERVED_NC3
ANT_HV0 ANT_HV1 ANT_HV2 ANT_HV3 ANT_HV4 ANT_HV5 ANT_HV6 ANT_HV7 ANT_HV8
ANT_HV9 ANT_HV10 ANT_HV11 ANT_HV12 ANT_HV13 ANT_HV14 ANT_HV15 ANT_HV16 ANT_HV17 ANT_HV18 ANT_HV19 ANT_HV20 ANT_HV21 ANT_HV22 ANT_HV23
ANT_LV0 ANT_LV1 ANT_LV2 ANT_LV3 ANT_LV4 ANT_LV5 ANT_LV6 ANT_LV7 ANT_LV8
ANT_LV9 ANT_LV10 ANT_LV11 ANT_LV12 ANT_LV13 ANT_LV14 ANT_LV15 ANT_LV16 ANT_LV17 ANT_LV18 ANT_LV19 ANT_LV20 ANT_LV21 ANT_LV22 ANT_LV23
RESERVED_NC1 RESERVED_NC2 RESERVED_NC3
1
C1 C2 D1 D2 C3 D3 E2 E1 F2 F1 G2 G1 H2 H1 J2 J1 K2 K1 L2 L1 M2 M1 M3 L3
TS_AY0_ANT_LV0
M8
TS_AY0_ANT_LV1
M7
TS_AY0_ANT_LV2
L8
TS_AY0_ANT_LV3
L7
TS_AY0_ANT_LV4
L6
TS_AY0_ANT_LV5
K8
TS_AY0_ANT_LV6
K7
TS_AY0_ANT_LV7
K6
TS_AY0_ANT_LV8
J8
TS_AY0_ANT_LV9
J7
TS_AY0_ANT_LV10
J6
TS_AY0_ANT_LV11
H6
TS_AY0_ANT_LV12
H7
TS_AY0_ANT_LV13
H8
TS_AY0_ANT_LV14
G6
TS_AY0_ANT_LV15
G7
TS_AY0_ANT_LV16
G8
TS_AY0_ANT_LV17
F6
TS_AY0_ANT_LV18
F7
TS_AY0_ANT_LV19
F8
TS_AY0_ANT_LV20
E7
TS_AY0_ANT_LV21
E8
TS_AY0_ANT_LV22
D7
TS_AY0_ANT_LV23
D8
D5 D6 C6
K3 C5 C4
C7
ATB
TS_AY1_ANT_HV0
C1
TS_AY1_ANT_HV1
C2
TS_AY1_ANT_HV2
D1
TS_AY1_ANT_HV3
D2
TS_AY1_ANT_HV4
C3
TS_AY1_ANT_HV5
D3
TS_AY1_ANT_HV6
E2
TS_AY1_ANT_HV7
E1
TS_AY1_ANT_HV8
F2
TS_AY1_ANT_HV9
F1
TS_AY1_ANT_HV10
G2
TS_AY1_ANT_HV11
G1
TS_AY1_ANT_HV12
H2
TS_AY1_ANT_HV13
H1
TS_AY1_ANT_HV14
J2
TS_AY1_ANT_HV15
J1
TS_AY1_ANT_HV16
K2
TS_AY1_ANT_HV17
K1
TS_AY1_ANT_HV18
L2
TS_AY1_ANT_HV19
L1
TS_AY1_ANT_HV20
M2
TS_AY1_ANT_HV21
M1
TS_AY1_ANT_HV22
M3
TS_AY1_ANT_HV23
L3
TS_AY1_ANT_LV0
M8
TS_AY1_ANT_LV1
M7
TS_AY1_ANT_LV2
L8
TS_AY1_ANT_LV3
L7
TS_AY1_ANT_LV4
L6
TS_AY1_ANT_LV5
K8
TS_AY1_ANT_LV6
K7
TS_AY1_ANT_LV7
K6
TS_AY1_ANT_LV8
J8
TS_AY1_ANT_LV9
J7
TS_AY1_ANT_LV10
J6
TS_AY1_ANT_LV11
H6
TS_AY1_ANT_LV12
H7
TS_AY1_ANT_LV13
H8
TS_AY1_ANT_LV14
G6
TS_AY1_ANT_LV15
G7
TS_AY1_ANT_LV16
G8
TS_AY1_ANT_LV17
F6
TS_AY1_ANT_LV18
F7
TS_AY1_ANT_LV19
F8
TS_AY1_ANT_LV20
E7
TS_AY1_ANT_LV21
E8
TS_AY1_ANT_LV22
D7
TS_AY1_ANT_LV23
D8
D5 D6 C6
K3 C5 C4
C7
ATB
TS_AY2_ANT_HV0
C1
TS_AY2_ANT_HV1
C2
TS_AY2_ANT_HV2
D1
TS_AY2_ANT_HV3
D2
TS_AY2_ANT_HV4
C3
TS_AY2_ANT_HV5
D3
TS_AY2_ANT_HV6
E2
TS_AY2_ANT_HV7
E1
TS_AY2_ANT_HV8
F2
TS_AY2_ANT_HV9
F1
TS_AY2_ANT_HV10
G2
TS_AY2_ANT_HV11
G1
TS_AY2_ANT_HV12
H2
TS_AY2_ANT_HV13
H1
TS_AY2_ANT_HV14
J2
TS_AY2_ANT_HV15
J1
TS_AY2_ANT_HV16
K2
TS_AY2_ANT_HV17
K1
TS_AY2_ANT_HV18
L2
TS_AY2_ANT_HV19
L1
TS_AY2_ANT_HV20
M2
TS_AY2_ANT_HV21
M1
TS_AY2_ANT_HV22
M3
TS_AY2_ANT_HV23
L3
TS_AY2_ANT_LV0
M8
TS_AY2_ANT_LV1
M7
TS_AY2_ANT_LV2
L8
TS_AY2_ANT_LV3
L7
TS_AY2_ANT_LV4
L6
TS_AY2_ANT_LV5
K8
TS_AY2_ANT_LV6
K7
TS_AY2_ANT_LV7
K6
TS_AY2_ANT_LV8
J8
TS_AY2_ANT_LV9
J7
TS_AY2_ANT_LV10
J6
TS_AY2_ANT_LV11
H6
TS_AY2_ANT_LV12
H7
TS_AY2_ANT_LV13
H8
TS_AY2_ANT_LV14
G6
TS_AY2_ANT_LV15
G7
TS_AY2_ANT_LV16
G8
TS_AY2_ANT_LV17
F6
TS_AY2_ANT_LV18
F7
TS_AY2_ANT_LV19
F8
TS_AY2_ANT_LV20
E7
TS_AY2_ANT_LV21
E8
TS_AY2_ANT_LV22
D7
TS_AY2_ANT_LV23
D8
D5 D6 C6
K3 C5 C4
C7
ATB
MTTP49001
MTTP49002
MTTP49003
49. Touch
49. Touch
49. Touch
Title:
Title:
Microsoft Confidential
Microsoft Confidential
Microsoft Confidential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Title:
Surface
Surface
Surface
Engineer:
Engineer:
Engineer:
A
A
A
1
49 76Thursday, April 26, 2018
49 76Thursday, April 26, 2018
49 76Thursday, April 26, 2018
1.0.0.1
1.0.0.1
1.0.0.1
5
Vinafix.com
1P8V_WIFI_ INT_OUT
VDD1V8_RF_K9
0201
0201
C50005
3.3p
25V
0201
C50008 100p
25V 0201
C50010 100p
25V 0201
C50013 100p
25V 0201
C50030 100p
25V 0201
PCIE_WIFI_CL KREQ_N [20,50 ]
PCIE_WIFI_W AKE_N [25 ,50]
J50001 MM8030-261 0RK0
C50003 1u
6.3V 0201
VDD1V8_RF_K3
C50007 1u
D D
VDD1V8_RF_J1
VDD1V8_RF_H1
VDD1V8_RF_G1
VDD1V8_RF_F1
VDD1V8_RF_M14
VDD1V8_RF_NFC_E14
C C
3P3V_RADIO
B B
P50001
SIG
6.3V 0201
C50014 1u
6.3V 0201
C50023
0.1u
6.3V 0201
C50029
2.2u
6.3V 0402
C50034
0.1u 6.3V
0201
R50042 10K
R50036 10K
R50037 49.9K
DNP 020 1
WF_RF_PATH_A_ ANT
3
GND 2,3,4
20449-001E
X864717-001
P50002
SIG
A A
GND 2,3,4
20449-001E
X864717-001
WF_RF_PATH_B_ANT
PROBE
OUT2IN
GND4
GND3
1P8V_WIFI_ INT_OUT
VDD1V8_RF_H16
VDD1V8_RF_K16
VDD1V8_RF_G16
VDD1V8_RF_D2
VDD1V8_RF_C1
VDD1V8_RF_PCIE_HSIC_A10
3P3V_RADIO
VDD3V3_RF_M3
VDD3V3_RF_M9
VDD3V3_RF_B11
VIO_RF_L12
1
4
J50002 MM8030-261 0RK0
OUT2IN
3
GND3
WF_RF_PATH_COAX
PROBE
GND4
C50002 100p 25V
0201
C50006 100p 25V
0201
C50011 100p 25V
0201
C50012 100p 25V
0201
C50016 1u 6.3V
0201
C50026 10u
6.3V 0603
C50031 10u
6.3V 0603
C50035 1u 6.3V
0201
C50039
0.1u
6.3V 0201
1
4
C50001 100p 25V
0201
C50017 10p 50V
0201
C50027 100p 25V
0201
C50032 100p 25V
0201
C50037
0.1u 6.3V
0201
3P3V_RADIO
R50038 10K
DNP 0201
R50039 49.9K
R50040
DNP 0201
R50041 49.9K
A1A2
L50006 LXES15AAA1-153
X935756-001
Done: 4.7k 0402 for ESD
1
2
3
4
MTTP50004
SMD RND 22.8mi l
C50028
25V
3.3p
0201
C50033
25V
3.3p
0201
0201
10K
0201
U50002 LFD182G45MJ 6D431
5G_IN
GND1
GND
ANT
2G_IN
GND3
WF_RF_PATH_B
A1A2
L50009 LXES15AAA1-153
X935756-001
1P8V_WIFI_ INT_OUT
3P3V_RADIO
VDD3V3_RF_D16
C50009
0201
0.1u6.3V
VIO
C50070 2p 25V
0201
OPTION HOST VIO
1P8V_WIFI_ INT_OUT
DNP
R50014 0
0201
R50015 0
VIO
C50036
0.1u 6.3V
0201
C50071 2p 25V
0201
3P3V_RADIO
0201
WIFI > PCIe3
PCIE_WIFI_CL KREQ_N[20,50] PCIE_WIFI_RCL K_DN[20] PCIE_WIFI_RCL K_DP[20] PCIE_WIFI_TX9_DN[2 4] PCIE_WIFI_TX9_DP[24] PCIE_WIFI_RX9_ DN[24] PCIE_WIFI_RX9_ DP[24]
PCIE_WIFI_DIS ABLE_N [25,50]
PCIE_WIFI_PER ST_N [25,50]
DNP
C50050
5.6p
0201
6
RF_TR_5_A_C
5
WIFI_RF_2_ A_OUT RF_TR_2_A
4
DNP
C50056
25V
5.6p
0201
U50004 LFD182G45MJ 6D431
1
5G_IN
GND1
2
3
ANT
GND3
GND
2G_IN
C50054 5.6 p
C50055 1 0p
0201
6
5
4
GND
PCIE_WIFI_W AKE_N[25,50]
WLAN_PWD_ N[25]
25V0201
50V
C50058
25V
5.6p
0201 DNP
RF_TR_5_B_C
U50001A
A10
AVDD18_1
J1
AVDD18_10
K3
AVDD18_11
K9
AVDD18_12
K16
AVDD18_13
M14
AVDD18_14
C1
AVDD18_2
D2
AVDD18_3
E14
AVDD18_4
F1
AVDD18_5
G1
AVDD18_6
G16
AVDD18_7
H1
AVDD18_8
H16
AVDD18_9
B11
AVDD33_1
D16
AVDD33_2
M3
AVDD33_3
M9
AVDD33_4
D15
AVSS1
H10
AVSS10
H15
AVSS11
J15
AVSS12
J16
AVSS13
K1
AVSS14
K15
AVSS15
L2
AVSS16
L3
AVSS17
L5
AVSS18
L7
AVSS19
F2
AVSS2
L9
AVSS20
L10
AVSS21
L13
AVSS22
L16
AVSS23
F3
AVSS3
F16
AVSS4
G2
AVSS5
G15
AVSS6
H2
AVSS7
H3
AVSS8
H9
AVSS9
88W8897-B 1-CBK2-T
RF_TR_5_A
C50063 5.6 p
WIFI_RF_2_ B_FIL_IN
GPIO[13]/PCIE_W_DISABLE
25V
0201
3
GPIO[0] GPIO[1] GPIO[2] GPIO[3] GPIO[4] GPIO[5] GPIO[6]
GPIO[8]/LED_OUT_WLAN
GPIO[9]/LED_OUT_BT
GPIO[11]/LED_OUT_NFC
GPIO[12]/PCIE_PERSTn
GPIO[7]
GPIO[10]/SER_WB
GPIO[14] GPIO[15] GPIO[16] GPIO[17] GPIO[18] GPIO[19] GPIO[20] GPIO[21] GPIO[22] GPIO[23] GPIO[24]
CONFIG_HOST[0] CONFIG_HOST[1] CONFIG_HOST[2] CONFIG_HOST[3]
BRF_ANT
BUCK11_SENSE
BUCK11_VOUT
BUCK18_SENSE
BUCK18_VOUT
R50021 0 0201 R50022 0 0201 R50023 0 0201
C50045 0.1u 6.3V 0201 C50046 0.1u 6.3V 0201
R50025 0
0201
RF_TR_5_B
R50034 0
C3 D5 B2 A3 E7 E8 E9 E10 K13 J13 E6 E11 D8 B7 B6 A5 D6 B5 C6 C4 C5 B3 B4 C2 D4
G5 E5 F4 E4
M15
B14 A15
C15 B16
C50038 0.1 u
R50024 0
0201
MTP_BF50001
R50027 49.9K
0201
SMD RND 31.5mi l
MTP_BF50003
C50066 10p
50V
0201
0201
WIFI_GPIO0 WIFI_GPIO1 WIFI_GPIO2
PCIE_W_PERST_N PCIE_W_DISABL E
WF_CNFG_HST0 WF_CNFG_HST1 WF_CNFG_HST2 WF_CNFG_HST3
BRF_ANT_M15 [50]
WF_BUCK11_V OUT
WF_BUCK18_V OUT
6.3V
0201
PCIE_WIFI_CL KREQ_N_R PCIE_WIFI_RCL K_R_DN PCIE_WIFI_RCL K_R_DP
PCIE_WIFI_C_ RX9_DN PCIE_WIFI_C_ RX9_DP
SMD RND 31.5mi l
M_PDN
SMD RND 31.5mi l
MTP_BF50002
WIFI_RF_2_B_FIL_IN_C
RF_CNTL1_P_R
C50069 10p
0201
SMD RND 22.8mi l SMD RND 22.8mi l
MTTP50001 MTTP50002
SMD RND 22.8mi l
MTTP50003
L50003 2.2uH
NFC_SWP1_VDDIN
PCIE_WAKE_N_ R
Done: RF_CNTL0_N = 1 for 40MHz auto calibration
RF_CNTL0_N RF_CNTL1_P RF_TR_2_A RF_TR_2_B RF_TR_5_A RF_TR_5_B
R50030 49.9K
0201
3P3V_RADIO
R50033 0
0201
C50060 10p
50V
0201
U50005 BGS12SN6
4
VDD
5
RFIN
6
CTRL
2
50V
GND
R50005 49.9K 0201 R50007 49.9K 0201 R50008 49.9K 0201
R50009 49.9K 0201
MTTP50005 SMD RND 22.8mil MTTP50006 SMD RND 22.8mil MTTP50007 SMD RND 22.8mil MTTP50008 SMD RND 22.8mil
1.67A2.5X2X1.2MM
U50001B
D10
RES_D10
C10
RES_C10
E15
NFC_ANT_N
E16
NFC_ANT_P
F13
NFC_SWP1_IO
F14
NFC_SWP1_VDDIN
F15
NFC_SWP1_VDDOUT
F12
NFC_SWP2_IO
E13
NFC_SWP2_VDDOUT
G14
NFC_TWSI_CLK
G13
NFC_TWSI_SDA
E12
NFC_VDDANT
G12
NFC_WI_IN
C7
PCIE_CLKREQn
D9
PCIE_RCLK_N
C8
PCIE_RCLK_P
C9
PCIE_RX_N
B9
PCIE_RX_P
B8
PCIE_TX_N
A8
PCIE_TX_P
D7
PCIE_WAKEn
D13
PDn
D14
RES1
H11
RES10
H12
RES11
J12
RES12
K12
RES13
F8
RES2
F9
RES3
F10
RES4
F11
RES5
G4
AT0
G7 G8
G11
G9
G10
M5
M10
M2 M7
B12 C12
3P3V_RADIO
<HDL_POWER>
RF1
RF2
RES6 RES7 RES8 RES9
RF_CNTL0_N RF_CNTL1_P RF_TR_2_A RF_TR_2_B RF_TR_5_A RF_TR_5_B
SD_CLK SD_CMD
88W8897-B 1-CBK2-T
3
BRF_ANT_M15_C
1
2
DNP
C50004 0.1 u
6.3V
0201
PCIE_W_PERST_N
PCIE_W_DISABL E
0201
0201
R50001220
R500020
1.1V
R50003 0
0201
1P8V_WIFI_ INT_OUT
R50006 0
1P1V_WIFI_ INT
C50015 10u
6.3V
1.67A2.5X2X1.2MM
C50024 10u
6.3V 0603
0603L50002 2.2uH
1P8V_WIFI_ INT
TCK
TDO TMS
USB_DMNS
USB_DPLS
VBAT_IN
VBLDO33_CNTL
VBLDO33_SENSE
VDD11 VDD12
VIO VIO_RF VIO_SD
VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8
XTAL_IN
XTAL_OUT
SLP_CLK_IN
SER_DAT SER_CSn SER_CLK
SD_DAT[0] SD_DAT[1] SD_DAT[2] SD_DAT[3]
J14 H14
TDI
H13 L14
D11 C11
B15 F7 F6
A7 B10
A2 L12 A12
A6 A9 A11 A14 B1 C14 C16 D1
E1 E2
A4
E3 F5 D3
D12 C13 B13 A13
USB_DMNS USB_DPLS
WF_VBAT_IN_3V3
VDD11
VDD12_B1
REF_CLK_IN REF_CLK_OUT
SER_DAT
SER_CLK
3P3V_WW AN
R50018 0 0201 R50019 0 0201
C50042 0.1 u 6 .3V
0201 DNP
SER_CSN
R50028 49.9K
R50029 49.9K
MTTP50015
SMD RND 22.8mi l
MTTP50016
SMD RND 22.8mi l
U50003 AT24C16D-MAHM
1
NC
2
NC1
3
NC2 GND4SDA
9
PAD
X912618-001
C50018
0.1u 6.3V
0201
R50016 49.9K
0201
R50017 49.9K
GND
3P3V_RADIO
MTTP50013 SMD RND 22.8mil
0201
DNP020 1
MTTP50014
SMD RND 22.8mi l
1P8V_WIFI_ INT_OUT
8
Vcc
WF_EEP_WP
7
WP
6
SCL
5
VIO
DNP020 1
R50031 10K
0201
1P1V_WIFI_ INT_OUT
R50032 10K
1
PCIE_WIFI_PER ST_N [25,50]
PCIE_WIFI_DIS ABLE_N [25,50]
1.8V
0201
L50001
2.2A0402
30 OHM
30 Ohm
MTTP50009
MTTP50010 MTTP50011
MTTP50012SMD RND 22.8mi l
3P3V_RADIO
C50020 10u
6.3V 0603
SMD RND 22.8mi l
SMD RND 22.8mi l SMD RND 22.8mi l
BT -> USB2.0(5)
USB2_BT_DN [24] USB2_BT_DP [24]
C50041 1u
6.3V 0201
C50047
0.1u 6.3V
0201
1P8V_WIFI_ INT_OUT
0201
SER_CLK SER_DAT
1P1V_WIFI_ INT_OUT1P1V_WIFI_ INT
1P8V_WIFI_ INT_OUT1P8V_WIFI_ INT
3P3V_RADIO
C50021
0.1u
6.3V 0201
PLACE TP's on BOTTOM,
R50020 0
0201
C50040 10u
6.3V 0603
31
3.2X2.5MM
C50057
0.1u 6.3V
0201
Y50001 FL4000023
2 4
3P3V_RADIO
EEPROM
C50065 1 0p
0201 50V
C50067 1 0p
0201
RF_TR_2_BRF_TR_2_B_1
50V
BRF_ANT_M15 [50]
50. Wi-Fi_BT
50. Wi-Fi_BT
50. Wi-Fi_BT
Title:
Title:
Microsoft Co nfidential
Microsoft Co nfidential
Microsoft Co nfidential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Title:
Surface
Surface
Surface
Engineer:
Engineer:
Engineer:
1.0.0.1
1.0.0.1
A
A
A
1
50 79Thursday, April 26, 2018
50 79Thursday, April 26, 2018
50 79Thursday, April 26, 2018
1.0.0.1
5
Vinafix.com
D D
4
3
2
1
C C
B B
A A
51. Empty
51. Empty
51. Empty
Surface
Surface
Surface
1
1.0.0.1
1.0.0.1
1.0.0.1
51 79Thursday, April 26, 2018
51 79Thursday, April 26, 2018
51 79Thursday, April 26, 2018
Title:
Title:
Title:
Microsoft Confidential
Microsoft Confidential
Microsoft Confidential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
B
B
B
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
A
A
A
Engineer:
Engineer:
Engineer:
5
Vinafix.com
D D
4
3
2
1
C C
B B
A A
52. Empty
52. Empty
52. Empty
Surface
Surface
Surface
1
1.0.0.1
1.0.0.1
1.0.0.1
52 79Thursday, April 26, 2018
52 79Thursday, April 26, 2018
52 79Thursday, April 26, 2018
Title:
Title:
Title:
Microsoft Confidential
Microsoft Confidential
Microsoft Confidential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
B
B
B
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
A
A
A
Engineer:
Engineer:
Engineer:
5
Vinafix.com
4
3
2
1
mDP mux to HDMI/DVI Dongle control
V3P3_DSW V3P3_DSW
PCH Side DP Side
D D
DDPB_CTRL_DATA[10 ]
DDPB_CTRL_CLK[10]
R53013
2.2K
0201
R53012
2.2K
0201
VDD
V3P3_DSW
9
1
Y+
2
Y-
3
C53001
0.1u 6.3V
0201
U53002
MDP_DDI1_AUX _DN[10]
MDP_DDI1_AUX _DP[10]
DP_CONFIG1[5 3]
C53004 0.1u 6.3V
0201
C53003 0.1u 6.3V
0201
ALL
C53002
0.1u 25V
0201
DDPB_AUX_C_D N
DDPB_AUX_C_D P
5
M+
7
D+
4
M-
6
D-
10
SEL
8
OE
PI3USB102GZLEX
X936286-001 10-WFQF N
GND
V3P3_DSW
R53011 100K
0201
R53014 100K
0201
DDPB_AUX_MU X_DN [53]
DDPB_AUX_MU X_DP [53]
NOTE:
Place ESD Diodes close to DP connector
C C
MDP_SNK1_HPD[10]
RES_0201_12mil
R53002 100K
DP_CONFIG1[5 3]
RES_0201_12mil
R53001 1M
V5.5MLA0402NR
D53001
A1 A2
D53002
A1 A2
V5.5MLA0402NR
NOTE:
Place those AC Caps near to DP connector.
WLCSP- 5
0201
MDP_DDI1_ML0_ DP[10]
MDP_DDI1_ML0_ DN[10]
B B
MDP_DDI1_ML1_ DP[10]
MDP_DDI1_ML1_ DN[10]
MDP_DDI1_ML2_ DP[10]
MDP_DDI1_ML2_ DN[10]
MDP_DDI1_ML3_ DP[10]
MDP_DDI1_ML3_ DN[10]
C53015 0.1u
C53016 0.1u
0201
C53013 0.1u
C53014 0.1u
0201
C53018 0.1u
C53017 0.1u
0201
C53012 0.1u
C53011 0.1u
0201
DDI1_DATA0_C_DP
6.3V
6.3V
0201
DDI1_DATA1_C_DP
6.3V
6.3V
0201
DDI1_DATA2_C_DP
6.3V
DDI1_DATA2_C_DN ML_LANE2_DN
6.3V
0201
DDI1_DATA3_C_DP
6.3V
DDI1_DATA3_C_DN
6.3V
PCMF1USB3S
C2
OUT_1m
C1
OUT_1p
WLCSP- 5
PCMF1USB3S
C2
OUT_1m
C1
OUT_1p
WLCSP- 5
PCMF1USB3S
C2
OUT_1m
C1
OUT_1p
WLCSP- 5
PCMF1USB3S
C2
OUT_1m
C1
OUT_1p
GND
IN_1m
IN_1p
U53008
GND
IN_1m
IN_1p
U53007
GND
IN_1m
IN_1p
U53006
GND
IN_1m
IN_1p
U53004
B1
A2 A1
B1
A2 A1
B1
A2 A1
B1
A2 A1
ML_LANE0_DP ML_LANE0_DNDDI1_DATA0_C_DN
ML_LANE1_DP ML_LANE1_DNDDI1_DATA1_C_DN
ML_LANE2_DP
ML_LANE3_DP ML_LANE3_DN
R53009 1M
RES_0201_12mil
ML_LANE1_DP
ML_LANE1_DN
ML_LANE2_DP
ML_LANE2_DN
V3P3_DSW
R53010 10K
0201
ML_CONFIG2
ML_LANE3_DP
ML_LANE3_DN
ML_AUX_CONN _DP
ML_AUX_CONN _DN
ML_3P3V_PW R
DNP
ML_FLAG_N
U53005 NCP380HMUAJ AATBG
dfn7_2x2xp55_p65mm
4 5 7
GND
J53001
1
GND1
2
Hot_Plug_Detect
3
ML_Lane0(p)
4
CONFIG1
5
ML_Lane0(n)
6
CONFIG2
7
GND2
8
GND3
9
ML_Lane1(p)
10
ML_Lane3(p)
11
ML_Lane1(n)
12
ML_Lane3(n)
13
GND4
14
GND5
15
ML_Lane2(p)
16
AUX_CH(p)
17
ML_Lane2(n)
18
AUX_CH(n)
19
GND6
20
DP_PWR
M1019977-001
FLAG#3IN EN
OUT
GND1
ILIM
GND2
GND MTG9 MTG8 MTG7 MTG6 MTG5 MTG4 MTG3 MTG2 MTG1
6
ML_3P3V_PW R
1
ML_V3P3_FUSE_ILIM
2
GND 29 28 27 26 25 24 23 22 21
C53021 22u
0603
6.3V
V3P3_DSW
C53010 1u 6.3V
0201
C53007
6.3V
22u
0603
U53001 IP3319CX6
bga6_2x3ns_p95x1p34xp6_p4mm
DDPB_AUX_MU X_DP[53]
A A
DDPB_AUX_MU X_DN[53]
5
DP_OA1
B1
DM_O
DP_I A2 DM_I B2
ID
GND
4
C2
C1
ML_AUX_CONN _DP ML_AUX_CONN _DN
mDP_PW R_EN[10]
3
PESD5V0S1UA D53003
A K
R53018
49.9K
0201
C53008 470p 25V
0201
C53009 1u 6.3V
0201
2
R53006 33K
0201
ILIM(33K) ~ 0.8A meet VESA spec
mDP
mDP
1
mDP
Surface
Surface
Surface
53 76Thursday, April 26, 2018
53 76Thursday, April 26, 2018
53 76Thursday, April 26, 2018
Title:
Title:
Title:
Microsoft
Microsoft
Microsoft
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
C
C
C
A
A
Date: Sheet of
Date: Sheet of
Date: Sheet of
A
Engineer:
Engineer:
Engineer:
2.89.6
2.89.6
2.89.6
5
Vinafix.com
4
3
2
1
Sensor Connector to IR and RGB Cameras, Left and Right Microphones, and ALS Sensor
C54001
0.01u
0201
To IR LED on FPC through J54001
R54012
49.9K
0201
V+
V-
U54001 MP2370DJ
1
BST
5
IN
4
EN
TSOT23-6
V3P3_DSW
C54007
6
1
2
0201
0.1u
CAM_IR_STB_ERR
6
SW
IR_FB
3
FB
2
GND
MTP54001
SMD RND 22.8mil
IRLED_C_N [54]
DMIC_CLK [20,40]
CAM_F_XO_EN[20,25,54]
L54001
IR_SW IRLED_A_P
4.7uH 100KHz
A K
R54018 100K
0201
D54002
C54004
0402
4.7u
IR_FB_R IRLED_C_N
C54006 220p
0201
R54021 1K
R54020
7.5K
0201
DNP
C54005
0201
10p
0201
RN54001, RN54002, RN54003, RN54005 need common footprint from DFX and to be stuffed with X869109-001
R54030 1K0201
0nH 2.5GHZ
4
1
RN54001
0nH 2.5GHZ
4
1
RN54002
0nH 2.5GHZ
4
1
RN54003
CAM_IR_XO_EN[25]
2
3
2
X869109-001
3
2
X869109-001
3
2
U54004
2
A
1
B
74LVC1G32GX
CSI2_CLK1_FCAM_DN [23]
CSI2_CLK1_FCAM_DP [23]
X869109-001
5
VCC
4
Y
3
GND
Microsoft Confidential
Microsoft Confidential
Microsoft Confidential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
B
B
B
Date: Sheet of
Date: Sheet of
Date: Sheet of
A
A
A
MTP54010
SMD RND 22.8mil
Title:
Title:
Title:
Engineer:
Engineer:
Engineer:
R54019 1K
0402
R54022
0.25
1206U54002
MTP54009
SMD RND 22.8mil
CAM_F_XO_EN [20,25,54]
CSI2_IRCAM8_DP [23]
CSI2_IRCAM8_DN [23]
CSI2_CLK2_IRCAM_DP [23]
CSI2_CLK2_IRCAM_DN [23]
54. Camera/Sensor Conn
54. Camera/Sensor Conn
54. Camera/Sensor Conn
Surface
Surface
Surface
DNP
C54008
6.3V
1u
0402
CAM_IR_XO_EN_R
V1P8A
1
MTP54003
IRLED_A_P [54]
IRLED_C_N [54]
MTP54004
4.7K 0201 C54016
0.1u 6.3V
0201
SMD RND 22.8mil
R54029
54 79Thursday, April 26, 2018
54 79Thursday, April 26, 2018
54 79Thursday, April 26, 2018
SMD RND 22.8mil
1.0.0.1
1.0.0.1
1.0.0.1
MTP54002 SMD RND 22.8mil
VSYS
D D
V3P3_DSW
C C
B B
CAM_LED_F_EN[25]
A A
V5A
NX3008CBKS
L54007
120 Ohm 100MHz
120 Ohm 100MHz
CAM_IR_PWR_DN_N[25]
CAM_F_PWR_DN_N[25]
I2C_SDA_CAM[25]
CSI2_FCAM4_DN[23]
CSI2_FCAM4_DP[23]
NX3008CBKS
R54025 10K
0201
Q54001A
2
1.3A
0402
L54006
CAM_IR_STB[54] DMIC_DATA[20,40]
I2C_SCL_CAM[25]
Q54001B
5
6
1
GND
1.3A
0402
X869109-001
34
Place caps close to U52001
C54009
0.1u 16V
0201
Place close to pin 23
C54013
0.1u 6.3V
0201
CAM_IR_PWR_DN_N
CAM_IR_STB
0nH 2.5GHZ
3
2
RN54005
R54026 3.48K
0402
GND
C54010 10u 16V
0603
C54014 10u 6.3V
0402
4
1
SMD RND 22.8mil
MTP54007
ALS_IRQ_N[25]
SMD RND 22.8mil
CAM_IR_STB[54]
C54002 1u
0402
IRLED_A_P[54]
CAM_IR_XO_EN_R
RGB_LED_A_P
I2C_SDA_ALS[25]
I2C_SCL_ALS[25]
MTP54006
SMD RND 22.8mil
V3P3_DSW
R54008
10K
0201
CAM_IR_LED_IN
MTP54005
R54013 2.05K
R54015 150K
0201
TLV3011
CAM_IR_STB_ERR_INM
R54016 4.99K
CAM_IR_STB_ERR_INP
R54017 10K
0201 DNP
Layout Note: J54001 Pin 1 and Odd Pins along North Edge
Place C54003 near connector
IRLED_A_P
C54003
0.1u 6.3V
0201
CAM_IR_STB_ERR_REF
0201
J54001
2 4 6
8 10 12 14 16 18 20 22 24 26 28 30 32 34 36
38 40
WP3-S036VA1-R6000
GND
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36
MT2 MT4
1 3 5 7
9 11 13 15 17 19 21 23 25 27 29 31 33 35
MT1 MT3
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35
37 39
4
5
3
GND
IN-
REF
IN+
SC70-6
Pullups for I2C are on the Camera Flex.
MTP54008
SMD RND 22.8mil
ALS 7-bit I2C Address = 0x44
IR_BST
0201
OUT
IRLED_C_N
CAM_F_XO_EN_R
RGB Cam 7-bit I2C Address = 0x36
Check with Camera/RF/Power team for regulation, filtering, and component info Power regulation, Privacy LED and sensors moved locally on
RGB EEPROM 7-bit I2C Address = TBD IR Cam 7-bit I2C Address = 0x60
sensor board. IRLED Buck regulation local to mb Odd side of the J54001 connector faces the North edge of the PCB
5
4
3
5
Vinafix.com
3P3V_PANEL3P3V_PANEL 3P3V_PANEL
D D
EDP_AUX_DP[10]
EDP_AUX_DN[10]
C C
C55002
0.47u 6.3V
0201
6.3V 0201
C550100.1u
6.3V 0201
C550110.1u
GTP55004SMD RND 22.8mil
C55003 1u 6.3V
0201
TCON_VENDOR_ID[25,55]
EDP_HPD[10]
3
2
PANEL_BIST
VCC_EDP_BKLT_OUT
C55004
0.1u 6.3V
0201
TCON_BRD_REV[25,55]
4
L55004 DLP11TB800UL2L
1
1.25X1.0X.3MM
4
EDP_AUX_R_DP EDP_AUX_R_DN
BKLT_FB6[72] BKLT_FB4[72] BKLT_FB2[72]
3
3P3V_PANEL 3P3V_PANEL
J55001 AXE550127
2 4 6
8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50
52 54
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50
MTG2 MTG4
11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49
MTG1 MTG3
1
1
3
3
5
5
7
7
9
9
11 13 15 17 19 21 23 25 27 29 31 33 35 37
PANEL_LOGO
39 41 43 45 47 49
51 53
EDP_TX0_R_DN EDP_TX0_R_DP
EDP_TX1_R_DN EDP_TX1_R_DP
EDP_TX2_R_DN EDP_TX2_R_DP
EDP_TX3_R_DN EDP_TX3_R_DP
PANEL_LOGO [30] BKLT_FB5 [72] BKLT_FB3 [72] BKLT_FB1 [72]
VCC_EDP_BKLT_OUT
2
L55001 DLP11TB800UL2L
1.25X1.0X.3MM
3
2
L55002 DLP11TB800UL2L
1.25X1.0X.3MM
3
2
L55003 DLP11TB800UL2L
1.25X1.0X.3MM
3
2
L55005 DLP11TB800UL2L
1.25X1.0X.3MM
3
2
4
1
4
1
4
1
4
1
0.1u6.3V
0201
0.1u6.3V
0201
0.1u6.3V
0201
0.1u6.3V
0201
0.1u6.3V
0201
0.1u6.3V
0201
0.1u6.3V
0201
0.1u6.3V
0201
C55001
C55005
C55006
C55007
C55008
C55009
C55012
C55013
1
EDP_TX0_DN [10]
EDP_TX0_DP [10]
EDP_TX1_DN [10]
EDP_TX1_DP [10]
EDP_TX2_DN [10]
EDP_TX2_DP [10]
EDP_TX3_DN [10]
EDP_TX3_DP [10]
V3P3_DSW
B B
V3P3_DSW
TCON_VENDOR_ID[25,55]
TCON_BRD_REV[25,55]
SMD RND 22.8mil
SMD RND 22.8mil
GTP55006
GTP55005
Caps are for EDP plane discontinuities, connect to GND
VCC_EDP_BKLT_OUT
C55022
330p0201
C55015
0.1u 50V
0603
C55023
330p0201
Place at connector J55001
STITCHING CAPS for Plane splits; one note item 101
A A
5
C55026
0.1u 6.3V
0201
C55027
0.1u 6.3V
0201
C55028
0.1u 6.3V
0201
4
C55029
0.1u 6.3V
0201
C55030
0.1u 6.3V
0201
C55031
0.1u 6.3V
0201
C55032
0.1u 6.3V
0201
3
C55033
0.1u 6.3V
0201
55. eDP connector
55. eDP connector
Title:
Title:
Title:
Microsoft Confidential
Microsoft Confidential
Microsoft Confidential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
B
B
B
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
A
A
A
Engineer:
Engineer:
Engineer:
55. eDP connector
Surface
Surface
Surface
55 79Thursday, April 26, 2018
55 79Thursday, April 26, 2018
55 79Thursday, April 26, 2018
1
1.0.0.1
1.0.0.1
1.0.0.1
5
Vinafix.com
1.5A
D56002 PMEG4015EPK315
PWR_SL_F
D D
VDD_BAT
C C
PM_THERMTRIP_N[1 0]
PLT_RST_BUF_N[22,27,34,38,43,44]
B B
SAM_PWR BTN_N[29]
A A
A K
1.5A
D56003 PMEG4015EPK315
A K
R56021 100
0201
C56007 1000p
0201 25V
PWR_SW _N[48]
S56001
DEBUG_GP
SWITCH- N-O_6P_1-3_2-4_2M P
12
N-O
34
GND
5
6
VCCST_CPU
R56043 330
0201
B
CE
Q56001 MMBT3904TT1G
MTTP_BF56001
SMD RND 31.5mil
R56017 10K
0201
C56008
0.1u 6.3V
0201
MTP_BF56001
SMD RND 31.5mil
MTTP56007
C56023
0.1u
6.3V 0201
A1
A1A2
D56006 V5.5MLA0402NR
Q56002 NX3008NBKMB315
s
2
1
A2
BAT54CW
K
G
3P3VA3P3VA_SW
D56005
GTP56003
SP_TP_SMDp58mm
D
3
R56018 10K
0201
GP_SAM_COLD_BO OT[27]
POWER BUTTON
5
3P3VA_SW
C56009
0.1u 6.3V
0201
GP_TSYS[39]
GTP56006
R56019 100
0201
4
3P3VA
R56045 100K
0201
4
R56005 33K
0201
3P3VA_EN
C56010 1000p
0201 25V
0201
R560590
R56006 10K
0201
11
SAM_GP_RST[28]
SAM_GP_DEEPSLP[27]
U56002
3
EN
7
PG
8
SLEEP
4
NC
1
PGND
6
AGND AGND/PGND
TPS62177DQCR
VDD_BAT
PCH_DPW ROK[22,27,34,59]
SSD_FLUSH_DO NE[27,43]
V_ALWAYS_ON
2
VIN
VA_SW_NODE
9
SW
10
VOS
5
FB
R56003100K
0201
R56004100K
0201
3P3VA_SW
R56058
200K
0201
C56003
4.7u
35V 0603
L56001
10uH
X881302-001
4.0X4.0X1.2MM MAX
MASTER_THERM TRIP_N [27]
SL_VDET[69]
0201
R56022301K
R56023100K
0201
R56026499
0402
R56001 10K 0201
R56002 10K 0201
SAM_RTC_W AKEUP[28]
R56072 1K0201
C56015
0.1u6.3V
0201
21
0201
C56025 1u
6.3V 0201
3
R56024499
SOT-363
0201
GP_VDD_BATA_A
PCH_DPW ROK_A
3
R5602533K
C56026 1u
6.3V 0201
C56027 1u
6.3V 0201
Q56005A NX3008NBKS
6 1
2
C56012 1u
6.3V 0201 DNP
C56005 22u 6.3V
0603
R56076
0201
1M
U56004
15
VDD_VBAT_A
3
SL_VDET
4
DPWROK
2
PWR_BTN_N
18
SAM_RST
19
SAM_DEEPSLP
12
TSYS_A
13
DBG_MODE
6
RTC_WAKE_N
14
COLD_BOOT
10
FLUSH_DONE
16
SSD_FLUSH
SLG4X4955VTR FW R028_012U
TBL2304
GP_SSD_FLUSH [43]
GTP56008
SMD RND 22.8m il
C56004 22u 6.3V
0603
VCCRTC_RST[27]
VDD
SL_PG
NC_7
3P3VA_SW_EN
NC_9
BAT_SHDN
PBTN_STATE
GND
C56022 22u 6.3V
0603
C56013
0.1u 6.3V
0201
1
5
7
8
9
20
17
11
2
SMD RND 31.5m il
0201
C56021
3P3VA
3P3VA_SW_EN
1u
6.3V 0201
R56060 499
0201
R56069 499 0201
GP_BAT_SHUTDOW N [70]
GP_DBGACC [29,31,47]
2
MTP_BF56002
R56008 499
0201
R56042 499K
0201
C56024
0.1u6.3V
0201
DNP
R56073 499
GND
A2
B2
D56007
A K
1PS79SB30
U56005 NX3P1108UK
VIN
EN
WLCSP4
3P3VA
A K
R56071
100K
0201
A1
VOUT
B1
GND
GTP56010
SMD RND 22.8m il
GP_SYS_PWR_E N [63]
GTP56009
SMD RND 22.8m il
DNP
PCH_DPW ROK_A
DNP
1
5
C56020
0.1u 6.3V
0201
A
A
A
VCC_RTC
34
Q56005B NX3008NBKS
R56015 200K
0201
MTP56003
SMD RND 22.8m il
R56047 249K
0201 DNP
3P3VA_SW
SL_PG [27,69]
SAM_PCH_RSM RST_N [18,22,29]
SAM_PWR _BTN_STATE [29,34]
56. 3P3VA & Reset
56. 3P3VA & Reset
56. 3P3VA & Reset
Title:
Title:
Title:
Surface
Surface
Surface
Engineer:
Engineer:
Engineer:
1
56 79Thursday, April 26, 2018
56 79Thursday, April 26, 2018
56 79Thursday, April 26, 2018
MTP56004
D56004
1PS79SB30
R56013 200K
0201
0201
R560770
0201
R560780
Microsoft Conf idential
Microsoft Conf idential
Microsoft Conf idential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
1.0.0.1
1.0.0.1
1.0.0.1
5
Vinafix.com
D D
4
3
2
1
C C
B B
A A
57. VCCEDRAM & VCCEOPIO
57. VCCEDRAM & VCCEOPIO
57. VCCEDRAM & VCCEOPIO
Surface
Surface
Surface
1.0.0.1
1.0.0.1
1.0.0.1
57 79Thursday, April 26, 2018
57 79Thursday, April 26, 2018
1
57 79Thursday, April 26, 2018
Title:
Title:
Microsoft Confidential
Microsoft Confidential
Microsoft Confidential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
B
B
U SPECIFIC
5
4
3
2
B
Date: Sheet of
Date: Sheet of
Date: Sheet of
A
A
A
Title:
Engineer:
Engineer:
Engineer:
5
Vinafix.com
D D
4
3
2
1
C58006
10u 16V
VSYS
C58005
0.01u
0201
1-2
VIN
TG
8
7 6
3 4
VSW
TGR
BG
5
PGND
9
R58062
100K
0201
VCCIO V3P3A_PCH
Q58001
CSD87333Q3D
L58002
C58012
22u
6.3V
0603
C58016
22u
6.3V
0603
C58013
22u
6.3V
0603
C58017
0603
22u
6.3V
C58018
22u
6.3V
0603
0.47uH
4.6A
3.2x2.5x1.2mm
IND-PW R,SM,0.47 uH,4.6 A,.025 OH M,20%,3.2X2.5X1.2MM,H EI322512A-R47M-Q8
C58164 1u 02016.3V
R58015 10 0201
VCCIO_SENSE[12]
VSSIO_SENSE[12]
C C
C58026 10u 16V
VSYS
C58025
0.01u
25V 0201
MTP58005
V5A
0402
R58067
150
150
R58068
0402
3P3VA
Q58008B NX3008NBKS
34
B B
5
R58069
200K
0201
Q58008A NX3008NBKS
61
2
C58032
22u
6.3V
0603
C58162
22u
6.3V
0603
R58073
499 0201
C58033
22u
6.3V
0603
C58163
22u
6.3V
0603
6.3V
0201
DNP
V5A_VR_FB_R[70]
C58034
22u
6.3V
0603
C58064
22u
6.3V
0603
C581661u
C58035
C58065
SKL_SLP_SUS_N [22,27,34,58,59]
22u
6.3V
0603
22u
6.3V
0603
R58030
C58036
00201
22u
6.3V
0603
VSYS
V3P3_VCCDSW
C58055
22u
6.3V
0603
C58056
0603
22u
6.3V
C58058
22u
6.3V
0603
C58060
6.3V
0603
22u
C58061
6.3V
0603
22u
L58004
WPN4020H R47MTJ02
4X4X2MM
L58007
WPN4020H R47MTJ02
CSD87333Q3D
CSD87333Q3D
4X4X2MM
Q58002
Q58006
1-2
VIN
TG
8
7 6
3 4
VSW
TGR
BG
5
PGND
9
C58046
10u 16V
0805
C58045
0.01u
25V
0201
1-2
VIN
TG
8
7 6
3 4
VSW
TGR
BG
5
PGND
0805
25V
0805
REG5
C58007
0.1u
16V 10%
0402
C58027
0.1u 16V
0402
C58047
0.1u 16V
0402
R58005 0
0201
R58020 10 0201
R58035 10 0201
C58002
0402
HG4
BOOT4
LG4
VOUT4
HG5
SW5
BOOT5
LG5
HG6
SW6
BOOT6
9
LG6
C58168
1u
0201 6.3V DNP
R58045
R58077 150
0603
A A
Q58010B NX3008NBKS
34
3P3VA
R58078 200K
0201
5
Q58010A NX3008NBKS
61
2
499
V3P3_DSW_V R_FB_R[58]
R58079
PMIC_EN [29,58,59]
0201
SKL_SLP_SUS_N[22,27,34,58,59]
5
0 0201
R58076 0 0201
DNP
R58075 10K
0201 DNP
R58081
0.005 0603
A2
VIN1
B2
VIN2
C2
VIN3
D2
ON
PI3PD22920GBEX
DNP
4
U58002
VOUT1 VOUT2 VOUT3
GND
V3P3_DSW
22u
6.3V
DNP
34
A1 B1 C1
C58059
D1
22u
6.3V
0603
C58057
0603
L2
1u
6.3V
J1
K1
K2
L1
M1 M2
L3
K3
A8
A7
A9
A6
B6
B9
J14
K14
J13
L14
M13 M14
K13
R58070 150
0603
Q58009B NX3008NBKS
5
DNP
U58001A
PVCC4
HG4
SW4
BOOT4
LG4
PGND4_1 PGND4_2
VOUT4
(SGND4)
SGND4
HG5
SW5
BOOT5
LG5
PGND5
VOUT5
(AGND)
HG6
SW6
BOOT6
LG6
PGND6_1 PGND6_2
VOUT6
BD99992GW- E2
3P3VA
R58071 200K
0201
Q58009A
DNP
NX3008NBKS
61
DNP
3
2
PVCC7
VIN7_1 VIN7_2
BOOT7
SW7_1 SW7_2
PGND7_1 PGND7_2
VOUT7
VIN8_1 VIN8_2
BOOT8
SW8_1 SW8_2
PGND8_1 PGND8_2
VOUT8
PVCC9
VIN9_1 VIN9_2
BOOT9
SW9_1 SW9_2
PGND9_1 PGND9_2
VPPID
VOUT9
PVCC10
HG10
SW10
BOOT10
LG10
PGND10
DDRID
VOUT10
(AGND)
(AGND)
(AGND)
(AGND)(AGND)
499
499
F13
E13 E14
F14
BOOT7
D13
SW7
D14
C13 C14
F12
A5 B5
C5
BOOT8
A4
SW8
B4
A3 B3
C6
C12
A10 B10
C11
BOOT9
A11
SW9
B11
A12 B12
D12
C10
G2
F1
HG10
G1
SW10
F2
BOOT10
H1
LG10
H2
G8
H3
V3P3_VCCDSW
R58072
DNP
0201
R58080
0201 DNP
C58015
0.1u 16V
0402
C58003
REG5
25V
0603
10u
C58001
1u
6.3V
0402
R58006 10
0201
VOUT7
R58013
0201
C58019
0.1u 16V
10
0402
C58020
10u
25V
0603
VOUT8
C58028 1u 6.3V
0402
C58029
16V
R58025
10 0201
0.1u
0402
C58030
25V
0603
10u
VOUT9
REG5
C58041 1u 6.3V
0402
C58042
R58033
0.1u 16V
10 0201
0402
VOUT10VOUT6
R58074 0
0201
SKL_SLP_SUS_N [22,27,34,58,59]
PMIC_EN [29,58,59]
VSYS
L58001
1.0uH
C58004
3.6A
0.01u
25V
2.5X2.0X1.2mm
0201
IND-PW R,SM,1.0 uH,3.6 A,.042 OH M,20%,2.5X2.0X1.2MM,H EI252012A-1R0M-Q8
VSYS
L58005
1.5uH
C58021
2.7A
0.01u
25V
2.5X2.0X1.2mm
0201
IND-PW R,SM,1.5 uH,2.7 A,.065 OH M,20%,2.5X2.0X1.2MM,H EI252012A-1R5M-Q8
REG5
VSYS
L58003
2.2uH
C58031
2.5A
0.01u
25V
2.5X2.0X1.2mm
0201
IND-PW R,SM,2.2 uH,2.5 A,.083 OH M,20%,2.5X2.0X1.2MM,H EI252012A-2R2M-Q8
C5804310u
16V0805
C58044
0.01u
VSYS
25V0201
Q58007
1-2
CSD87333Q3D
VIN
TG
3 4
5
8
7
VSW
TGR
6
BG
PGND
L58006
WPN4020H R47MTJ02
4X4X2MM
9
V3P3_DSW_V R_FB_R [58]
2
C58008 22u
6.3V 0603
MTP58004
C58011 22u
6.3V 0603
C58009 22u
6.3V 0603
C58010 22u
6.3V 0603
C58165 1u
DNP
R58010
0 0201
6.3V 0201
3P3V_WW AN_IN_VR_FB_R [65]
MTP58008
V1P8A
C58022 22u
6.3V 0603
R58018 0 0201
C58023 22u
6.3V 0603
C58024 22u
6.3V 0603
1u
DNP
C58167
6.3V 0201
V1P8A_VR_FB_R [62]
C58037 22u
6.3V 0603
MTP58010
C58038 22u
6.3V 0603
C58039 22u
6.3V 0603
V1P8U_2P5U
C58169
1u
6.3V 0201
R58065
100K
0201
1P8V_DUAL_VR_FB_R [16]
R58029 10 0201
V1P2U
C58048 22u
6.3V 0603
C58049 22u
6.3V 0603
C58050 22u
6.3V 0603
R58044 10 0201
C58051 22u
6.3V 0603
C58052 22u
6.3V 0603
C58170 1u
6.3V 0201
C58053 22u
6.3V 0603
V1P2U_VR_FB_R [16]
58. PMIC 1
58. PMIC 1
58. PMIC 1
Title:
Title:
Microsoft Conf idential
Microsoft Conf idential
Microsoft Conf idential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
A
A
A
Title:
Engineer:
Engineer:
Engineer:
1
Surface
Surface
Surface
58 79Thursday, April 26, 2018
58 79Thursday, April 26, 2018
58 79Thursday, April 26, 2018
R58063
200K
0201
R58064
C58054 22u
6.3V 0603
100K
0201
R58066
100K
0201
1.0.0.1
1.0.0.1
1.0.0.1
5
Vinafix.com
4
3
2
1
VSYS
D D
3P3VA
R59082
200K
R59083
0201
200K
0201
Q60001A
NX3008NBKS
SOT-363
PMIC_EN[29,58]
R59084
I2C_SCL_MCU[29,34,39]
R59088 10K
0201
PMIC_SAM_ALL_SYS_PW RGD[22,29,34]
I2C_SDA_MCU[29,34,39]
C C
V3P3_DSW
B B
MTTP59001
SMD RND 22.8m il
MTTP59002
SMD RND 22.8m il
MTTP59003
SMD RND 22.8m il
MTTP59004
SMD RND 22.8m il
MTTP59012
SMD RND 22.8m il
2
300K
0201
SAM_PMIC_PW RBTN_N[34,59]
MTTP59009
SKL_SLP_S0_N [22,27,31,34 ,38,59,61]
SKL_SLP_S3_N [22,34,59,61 ]
PMIC_SAM_RSM RST_N [28,34,59]
DDR_VTT_CTL [11,34,59]
SKL_SLP_S4_N [22,27,34,45 ,59,61]
61
R59001
0402
3P3VA_SW
2K
1%
5
PMIC_SAM_RSM RST_N[28,34,59]
VSYS
R59002 2K
1%
0402
R59095
3.01K 0402
34
Q60001B NX3008NBKS
SOT-363
MTTP59005
3P3VA
GTP59001
SMD RND 22.8m il
SKL_SLP_S0_N[22,27,31,34,38,59,61]
PCH_DPW ROK[22,27,34,56]
SKL_SLP_SUS_N[22,27,34,58]
MTTP59007
PCH_PW RBTN_N[22,34]
SKL_SLP_S4_N[22,27,34,45,59,61]
SKL_SLP_S3_N[22,34,59,61]
VCCST_CPU
V3P3_DSW
SKL_VCCST_PW RGD[22,34]
DDR_VTT_CTL[11,34,59]
SKL_PCH_PW ROK[22,34]
SKL_SYS_PWRO K[22,34]
MTTP59010
MTTP59011
3P3VA_SW
C59025 1u
6.3V
V3P3_DSW
V1P8A
C59040
0.1u
16V 0201
PMIC_SAM_INT_N[28]
C59034 10u 16V
0805
PMIC_EN_P
0402
MTTP59006
R59009 10K
0201
SAM_PMIC_PW RBTN_N
MTTP59008
24.9K
R59029
0201
R59016
22
C59042
0.068u
16V 0201 DNP
C59039
0.01u
25V 0201
REG33
0201
U58001B
M11
VBATTBKUP
L7
ECVCC
L6
EC_RST_N
L12
ECWAKECLK
K9
BC_ACOK
D10
PMIC_INT_N
H14
VIN
H11
LOWBATTSENSE
(AGND)
G11
VDCSENSE
(AGND)
E10
RBATTPOS
F11
RBATTNEG
K8
ACOK
E11
RADPPOS
E12
RADPNEG
H12
PMIC_EN
L5
ENSEL
F7
SLP_S0_N
K12
VDD_V3P3A_RTC
L10
RTCRST_N
K5
DPWROK
N4
CLK
P4
DATA
M4
ADRS_SEL
B7
SLP_SUS_N
D6
V1P8A_EN
D7
DS3_VREN
M10
V5_EN
H7
V7_EN
G7
V12_EN
H8
V11_EN
J5
RSMRST_N
K7
PWRBTN_N
J7
EC_ONOFF_N
J8
PCH_ONOFF_N
F6
SLP_S4_N
D9
V1P8U_2P5U_EN
G6
SLP_S3_N
G9
V1P00S
(AGND)
E9
V1P8S
(AGND)
F9
V3P3S
(AGND)
K6
VCCST_PWRGD
J6
ALL_SYS_PWRGD
F4
DDR_VTT_CTL
L4
PCH_PWROK
H6
SYS_PWROK
PVCC11
HG11
SW11
BOOT11
LG11
PGND11
VOUT11
(SGND11)
SGND11
PVCC12
VIN12_1 VIN12_2
BOOT12
SW12_1 SW12_2
PGND12_1 PGND12_2
VOUT12
(SGND12)
SGND12
VDDQ
VIN13_1 VIN13_2
VTT_1 VTT_2
PGND13_1 PGND13_2
(AGND)
N6
P7
P6
N7
P5
N5
M6
M7
M8
N8 P8
M9
N9 P9
N10 P10
N11
P11
F3
E1 E2
D1 D2
C1 C2
HG11
SW11
BOOT11
LG11
VOUT11
SGND11
BOOT12
SW12
C59033
0.22u
0201
VOUT12
0201
C59026
C59001
1u
6.3V
0402
R59020
C59016
1u
6.3V
0402
R59026
0201
R59030
25V
10u
0603
R59004 10
0201
0
10
0
REG5
C59007
0.1u 16V
0402
0201
C59019
0.1u 16V
0402
REG5
C59017
10u
25V
0603
DNP
C59002
16V
10u
0805
0.01u 25V C59008
0201
1-2
VIN
Q59001 CSD87333Q3D
TG
3 4
5
C59018
0.01u
25V 0201
IND-PW R,SM,0.47 uH,4.6 A,.025 OH M,20%,3.2X2.5X1.2MM,H EI322512A-R47M-Q8
C59027 22u
6.3V
0603
VSW
TGR
BG
PGND
8
7 6
9
L59002
0.47uH
4.6A
3.2x2.5x1.2mm
V1P2U
L59001
0.47uH
4.6A
3.2x2.5x1.2mm
IND-PW R,SM,0.47 uH,4.6 A,.025 OH M,20%,3.2X2.5X1.2MM,H EI322512A-R47M-Q8
VSYS
VSYS
C59003 22u
6.3V 0603
C59021 22u
6.3V 0603
V0P6DX_LPDDR3
C59004 22u
6.3V 0603
C59022 22u
6.3V 0603
C59010 22u
6.3V 0603
C59023 22u
6.3V 0603
C59005 22u
6.3V 0603
V0P85A
C59024 22u
6.3V 0603
C59006 22u
6.3V 0603
C59037 22u
6.3V 0603
V1P00A
C59011 22u
6.3V 0603
C59038 22u
6.3V 0603
C59035
1u
0201 6.3V
R59019
100201
R59028
R59090
100K
0201 DNP
V1P00A_VR_FB_R [61]
C59036
1u
0201 6.3V
100201
V0P85A_VR_FB_R [26]
R59091
100K
0201 DNP
E3
VTTS
SKL_SLP_S4_N[22,27,34,45,59,61]
C59041
68p
BD99992GW- E2
(AGND)
VTTS
0201
0
R59037
Place C59041 next to R59016
A A
SAM_PMIC_PW RBTN_N [34,59]
3
59. PMIC 2
59. PMIC 2
59. PMIC 2
Title:
Title:
Microsoft Conf idential
Microsoft Conf idential
Microsoft Conf idential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
C
C
C
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
A
A
A
Title:
Engineer:
Engineer:
Engineer:
1
Surface
Surface
Surface
1.0.0.1
1.0.0.1
59 79Thursday, April 26, 2018
59 79Thursday, April 26, 2018
59 79Thursday, April 26, 2018
1.0.0.1
R59042
499
SAM_PMIC_PW RBTN[29]
5
SAM_PMIC_PW RBTN_R
0201
R59043
100K
0201
4
D
G
Q59003 RUM002N02GT2L
S
C59009
1u
6.3V
0402
5
Vinafix.com
D D
4
REG33
C60009
1u 10V
0201
U58001C
N13
TESTSEL2
B13
TESTSEL1
B2
TESTSEL0
F8
NO_FAULT
N2
LDO_UVLO_OFF
N1
TEST00
P1
TEST01
P2
TEST02
B1
TEST10
A1
TEST11
A2
TEST12
B14
TEST20
A14
TEST21
A13
TEST22
N14
TEST30
P14
TEST31
P13
TEST32
K11
DVCC33
G12
DGND_1
J3
DGND_2
3
MTTP60002
16V
0603
16V
C60008
10V
1u
0201
R60041
R60043
MTTP60003
200K
0201
150K
0201
REG5
REG33
AVCC33_1 AVCC33_2 AVCC33_3 AVCC33_4 AVCC33_5
REGIN
ILIM5 ILIM6
ILIM4 ILIM10 ILIM11
C9
J12
M3 C3 G14 M12 D3
H13 B8 L13
J2 G3 M5
C60006
1u 10V
0201
PMIC_REGIN ILIM5 ILIM6
R60040
301K
0201
ILIM4 ILIM10 ILIM11
R60042
499K
0201
C60017
0.047u
C60019
0.047u
0603
C60005
1u
0201
C60020
0.047u
0603
2
10V
C60018
0.047u
16V 0603
16V
C60004
10V
1u
0201
R60044
475K
0201
C60007
10V
1u
0201
150
R60004
0402
C60003 1u 10V
0201
C60021
0.047u
16V 0603
REG33
C60010
10V
4.7u
0402
R60049 200K
0201
REG33
C60011
10V
4.7u
0402
1
REG5
R60048 200K
0201
REG33
C60022
1u 10V
20%
0201
GTP60002
R60033
100
0201
C60012 1u 6.3V
0201
MTTP60001
SMD RND 22.8m il
t
NTC_REF[34]
R60006
24.9K
0201
RT60002
0.14 mA
0201
t
R60007
24.9K
RT60003
0.14 mA
C C
R60005
24.9K
0201
RT60001
0.14 mA
t
t
R60008
24.9K
0201
RT60004
0.14 mA
PROCHOT_N[10,34,63,66]
SMD RND 22.8m il
PMIC_ICPROC HOT_N
R60038 10K 0402
V_THERM_GNSS_TH ERMISTOR
C60013
1u 10V
0201
PMIC_MBI
PMIC_BATTID
NTC_REF SYSTHERM0 SYSTHERM1
SYSTHERM3
PMIC_VREF
L11
CLK_VDD
J11
CLK_GND
G4
LED1
H4
LED2
J4
LED3
K4
LED4
D11
PROCHOT_N
L8
MBI
K10
BATTID
J10
NTC_REF
F10
SYSTHERM0
G10
SYSTHERM1
H10
SYSTHERM2
H9
SYSTHERM3
L9
VREF
J9
ADC_GND
BD99992GW- E2
GPIO_VDD1
GPIO1 GPIO2
GPIO_VDD2
GPIO3 GPIO4
GPIO5 GPIO6 GPIO7 GPIO8 GPIO9
GPIO10
AGND1 AGND2 AGND3 AGND4 AGND5 AGND6
E4 C7 C8
D5 D8 E8
E7 E6 E5 F5 G5 H5
C4 G13 N3 N12 P3 P12
C60014 1u 10V
0201
C60015 1u 10V
0201
R60037 47K
0201
V1P8A
V3P3_DSW
B B
A A
60. PMIC 3
60. PMIC 3
60. PMIC 3
Title:
Title:
Microsoft Conf idential
Microsoft Conf idential
Microsoft Conf idential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
C
C
C
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
A
A
A
Title:
Engineer:
Engineer:
Engineer:
1
Surface
Surface
Surface
1.0.0.1
1.0.0.1
60 79Thursday, April 26, 2018
60 79Thursday, April 26, 2018
60 79Thursday, April 26, 2018
1.0.0.1
5
Vinafix.com
4
3
2
1
V1P2UV3P3_DSW
D D
C61003
0.1u 6.3V
0201
V3P3_DSW VCCSTG
C61005
0.1u 6.3V
0201
V3P3_DSW
C C
DEBUG_OSG
U61007
XDP_PRESENT_LOGIC[18,61]
1
A
2
VCC
B
NC
GND3Y
SN74AUP1G32DRYR
V1P00A
C61006 1u 6.3V
0201
DEBUG_OSG
C61019
0.1u 6.3V
6 5 4
0201
VCCSTG_EN
U61002 SLG5NT1477VTR
1
VDD
2
D1
3-4
D2
9
ON
S1 S2
GND
5-6 7
8
S0iX_EN[61]
C61007 10u 4V
0402
C61004 1u 6.3V
0201
U61001 SLG5NT1477VTR
1
VDD
2
D1
3-4
D2
9
ON
S1 S2
GND
5-6 7
8
C61001 1u 6.3V
0201
VCCPLL_OC
MTP61002
C61002 10u 10V
0603
V1P00A
R61002 0
0201
V1P00A_VR_FB_R [59]
R61003 0 0201
NDEBUG_OSG
VCC
NC
V3P3_DSW
6 5
VCCST_EN
4
DEBUG_OSG
C61018
0.1u 6.3V
0201
0201
V1P00A
V3P3_DSW
C61009
1u6.3V
C61012 1u 6.3V
0201
MTP61001
U61003 SLG5NT1477VTR
1
VDD
2
D1
3-4
D2
9
ON
S1 S2
GND
VCCST_CPU
5-6 7
8
C61011 10u 6.3V
0402
S0iX_EN
V3P3_DSW
B B
SKL_SLP_S3_N[22,34,59] SKL_SLP_S0_N
A A
U61004 SN74AUP1G08DRYR
1
A
2
B
3 4
GND
VCC
NC
Y
V1P00A
6 5
C61014 1u 6.3V
0201
C61008
0.1u 6.3V
0201
XDP_PRESENT_LOGIC[18,61]
SKL_SLP_S4_N[22,27,34,45,59]
S0iX_EN [61]
C61015 1u 6.3V
0201
C61016 10u 6.3V
0402
DEBUG_OSG
U61006
1
A
2
B GND3Y
SN74AUP1G32DRYR
R61004 0 0201
NDEBUG_OSG
61. Discrete Load Switches
61. Discrete Load Switches
Title:
Title:
Microsoft Confidential
Microsoft Confidential
Microsoft Confidential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
B
B
B
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
A
A
A
Title:
Engineer:
Engineer:
Engineer:
61. Discrete Load Switches
Surface
Surface
Surface
61 79Thursday, April 26, 2018
61 79Thursday, April 26, 2018
1
61 79Thursday, April 26, 2018
1.0.0.1
1.0.0.1
1.0.0.1
5
Vinafix.com
D D
V5A
C62003 1u 6.3V
0201
PCH_AUD_1V8_EN[20,25]
V1P8A
C62001
1u6.3V
0201
C C
C62010
2p
25V 0201
U62001
1
VDD
2
ON
3-4
D1-D2
SLG59M1448V
STDFN8
4
S1-S2
CAP
GND
5-6
CAP_1P8V_AUDIO
7
8
C62002 2200p 25V
0201
C62005
0.1u 6.3V
0201
3
2
1
1P8V_AUDIO
SMD RND 22.8mil
MTP62001
V1P8A
B B
C62009
V1P8A
R62001 0
0201
V1P8A_VR_FB_R [58]
10u
6.3V 0402
PCH_TPANEL_PWR_EN[25,64]
C62007 1u 6.3V
0201
U62003 NX3P1108UK
A2
VIN
B2
EN
WLCSP4
VOUT
GND
A1
B1
C62008
0.1u 6.3V
0201
1P8V_TS
SMD RND 22.8mil
MTP62003
A A
62. +1.8VSB & Load SW
62. +1.8VSB & Load SW
Title:
Title:
Title:
Microsoft Confidential
Microsoft Confidential
Microsoft Confidential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
A
A
A
Engineer:
Engineer:
Engineer:
62. +1.8VSB & Load SW
Surface
Surface
Surface
62 79Thursday, April 26, 2018
62 79Thursday, April 26, 2018
1
62 79Thursday, April 26, 2018
1.0.0.1
1.0.0.1
1.0.0.1
5
Vinafix.com
STITCHING CAPS for Plane splits
PCHGR_IN
4
3
2
1
One-note item 102
Q63005A
0201
C63064
0.1u
25V
0201
3P3VA
61
2
PROCHOT _N[10,34,60,66 ]
SAM_CHG _IMON[28]
VSYSV3P3_DSW
C63060
16V
0.1u
0201
D D
C C
B B
A A
VSYS
SAM_CHG R_PSU_ON[29,34]
SAM_CHG _ACOK[29]
C63061
16V
0.1u
0201
BATGONE[27,70]
C63062
0.1u
0201
PCHGR_IN
R63015 0 020 1
C63063
I2C_ROP_SC L[27,3 1,70]
I2C_ROP_SD A[27,31,70]
R63014 301K
0201
3P3VA_S W
0201
R63011 200K
0.1u
25V
0201
NX3008N BKS
R63029 100K
DNP
25V
R63059 100K
0201
C63065
0.1u
25V
0201
PWR_ SL_F
R6301749.90201
R6301649.90201
R63050 499
AON7405 Q63008
3 2 1
5
5,6,7,8
D
S
G
4
R63034
150K 0201
D63001 BAT54CW
200mA
A1
K
VSYS
0201
R63005 100
VAMON = 18x(VCSIP-VCSIN); VBMON = 18x(VCSON-VCSOP)
SAM_SL_ 5V_PG[27]
A2
C630331u
25V 0402
C630184.7u
6.3V 0402
C630234.7u
6.3V 0 402
R630320020 1
0201
0201
C630200.04 7u
1K
25V0402
C63027
100p
25V 0201 DNP
SAM_SL_ 5V_EN[27,69]
R63061
499 0201
R63049
1
0603
VDD
R63012
4.7
0402
VDDP
CHG_PRO CHOT_N_R
CHG_ACO K
CHG_SCL
CHG_SDA
GP_BATGONE_R
R63020133K
ILIM = 0.475A
R63021
3P3VA_S W
R63060
200K
0201
AON7405
3 2 1
S
5
R63022
14.7K
0201
CHG_ILIM_A
R63056 499
0201
Q63009
G
4
34
PCHGR_IN
5,6,7,8
5
D
Q63005B NX3008N BKS
SOT-363
17
DCIN
18
VDD
8
VDDP
23
PROCHOT
29
AMON_BMON
24
ACOK
22
SCL
21
SDA
25
BATGONE
27
PROG
28
COMP
20
OTG_EN_CMP_IN
26
OTGPG_CMP_OUT
ISL9237HR Z
C63019
0.1u
6.3V 0201
U63001
PCHGR_IN
19
ACIN
0603 25V
C63032 10u
R63033 0
0201
R63055 0
0201
13
16
ADP
ASGATE
7-bit I2C Address = 0x12 ??
C63034
0.047u
25V 0402 DNP
ACP
15
CSIP
R63002 1
0201
R63001
0.02
0612
C63001
1u
6.3V 0201
14
CSIN
LOAD
I1I2
SENSE
E1E2
BOOT1
UGATE1
PHASE1
LGATE1
BOOT2
PHASE2
LGATE2
UGATE2
VSYS
CSOP
CSON
BGATE
VBAT
PSYS
GND_PAD
R63003 1
0201
ACN
12
11
10
9
4
6
7
5
3
2
1
32
31
30
33
PTP6300 5
PTP6300 6
0603 25V
C63013 10u
C63035
0.047u
25V 0402 DNP
BOOT1
CHG_HIDRV1 _D
CHG_SW 1
CHG_LOD RV1_D
BOOT2
CHG_SW 2
CHG_LOD RV2_D
CHG_HIDRV2 _D
C63056
0.22u
0603 25V DNP
CHGR_VINCH GR_VIN
25V0603
25V0603
25V0603
C63006 10u
C63005 10u
C63004 10u
C63015
0.22u 2 5V
0603
0.22u 2 5V
0603
CHG_SRP _A
CHG_SRN _A
CHG_BAT DRV_N
CHG_PMO N
change to 7.87K based on Pyxis, and this charg er is 1.44uA/W, TI charge is 1u A/W. and MPS voltage limit is 0.8V
C63016
R63051
R63031
0402
R63030
0402
0 040 2
0603
C63003 1000p
25V 0201
0
0
R63006
0
R63008
7.87K
0201
C63026
0.01u
25V 0201
1-2
Q63001
VIN
CSD8733 4Q3D
TG
3
8
4
7
VSW
TGR
6
BG
5
PGND
9
PMON [66]
CSD8733 4Q3D
L63001
1.2uH
ind_13p7x12p 8x2mm
L63002
1.2uH
IND_13X13 X2
Q63002
1-2
8
7
VSW
6
PGND
9
R63058
0.10402
C63025
C63024
1000p
0.01u
25V
25V
0201
0201
VIN
TG
3 4
TGR
BG
5
VSYS
25V
25V
25V
25V
C63008 10u
C63007 10u
25V
25V
C63012 10u
C63011 10u
C63010 10u
C63009 10u
R63048 150
0603
Q63006B NX3008N BKS
34
0603
R63052 150
3P3VA
R63046 200K
0201
MTP6300 1
5
Q63006A NX3008N BKS
61
+
C63070 47uF
16V 1210
C630220.04 7u
25V 0402DNP
C630210.04 7u
25V 0402DNP
C63017
1u
6.3V
0201
+
R63053 100
0201
C63057
0.047u
0201 16V
C63071 47uF
16V 1210
R63007
1
0201
R63010
1
0201
C63031 4700p 10V
0201
2
PTP6300 3
SENSE
LOAD
0612
0.01 R63009
I1 I2
E1 E2
5-81
S
2
2
D DD
S
SON-8
CSD2540 2Q3A Q63003
DD D
3
VBAT_CHGR
3
Q63004 CSD2540 2Q3A
SON-8
4
G
G
4
5-8 1
R63019 100K
0201
25V
C63029 10u
VDD_BAT
5
25V
C63030 10u
34
PTP6300 4
VBAT_CH GR [28]
Q63007B NX3008N BKS
499
0201
R63044
GP_SYS_PW R_EN [56,63]
61
Q63007A
2
GP_SYS_PW R_EN[56,63]
5
4
3
2
R63013
499
0201
R63028
200K
0201
NX3008N BKS
R63057
5.11K
0201
63. CHARGER
63. CHARGER
63. CHARGER
Title:
Title:
1
Title:
Engineer:
Engineer:
Engineer:
Surface
Surface
Surface
63 79Thursday, April 26, 2018
63 79Thursday, April 26, 2018
63 79Thursday, April 26, 2018
Microsoft Confidential
Microsoft Confidential
Microsoft Confidential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
Custom
Custom
Custom
A
A
Date: Sheet of
Date: Sheet of
Date: Sheet of
A
1.0.0.1
1.0.0.1
1.0.0.1
5
Vinafix.com
V5A
D D
PCH_TPANEL_PW R_EN[25,62]
4
C64003
0201
3
5V_TS
C64001 U64002 SLG59M1448V
1
VDD
2
ON
3-4
D1-D2
1u6.3V
STDFN8
C64008
0.1u 6.3V
0201
S1-S2
CAP
GND
5-6
7
8
C64024 1000p 25V
0201
C64025 10u 6.3V
0402
10u6.3V
0402
2
MTP64001
SMD RND 22.8mil
1
Note: connect pins 1, 3, 4 together at the chip
V5A
Fat trace; 1uF input cap should be next to IC (pin 3-4)
C C
U64004 SLG59M1448V
1
VDD
3-4
2
STDFN8
ON
D1-D2
PCH_AUD_5V_EN[25]
C64015 1u 6.3V
0201
B B
C64018 1u 6.3V
0201
V5A
C64029
2p
25V 0201
S1-S2
CAP
GND
5-6
CAP_5V_AUDIO_REG
7
8
C64017 1000p 25V
0201
MTP64005
SMD RND 22.8mil
C64016 10u 6.3V
0402
5V_AUDIO
MTP64004
SMD RND 22.8mil
A A
64. +5V Load SW
64. +5V Load SW
64. +5V Load SW
Surface
Surface
Surface
64 79Thursday, April 26, 2018
64 79Thursday, April 26, 2018
1
64 79Thursday, April 26, 2018
1.0.0.1
1.0.0.1
1.0.0.1
SMD RND 22.8mil
MTP64006
5
Title:
Title:
Microsoft Confidential
Microsoft Confidential
Microsoft Confidential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
U SPECIFIC
4
3
2
B
B
B
Date: Sheet of
Date: Sheet of
Date: Sheet of
A
A
A
Title:
Engineer:
Engineer:
Engineer:
5
Vinafix.com
4
3
2
1
V3P3_DSW
A2 B2
D D
DISPLAY_VDD_EN[30]
C C
R65006 1K
0201
C65001
1u6.3V
0201
3P3V_PANEL_EN
C2
D2
PI3PD22920GBEX
U65001
VOUT1
VIN1
VOUT2
VIN2
VOUT3
VIN3
ON
GND
MTP65002
SMD RND 22.8mil
A1 B1 C1
D1
C65002
0.1u
6.3V 0201
3P3V_PANEL
MTP65001
SMD RND 22.8mil
3P3V_SSD
MTP65003
SMD RND 22.8mil
V3P3_DSW
A2 B2
C2
C65006 1u 6.3V
0201
B B
3P3V_SSD_EN[29]
D2
PI3PD22920GBEX
R65031 100K
0201
VIN1 VIN2 VIN3
ON
U65003
VOUT1 VOUT2 VOUT3
GND
A1 B1 C1
D1
C65007
0.1u 6.3V
0201
V3P3A_PCH
C65005 1u 6.3V
0201
WW AN_PW REN[25]
C65009 2p 25V
0201
A2 B2 C2
D2
PI3PD22920GBEX
V3P3A_PCH
VIN1 VIN2 VIN3
ON
U65004
VOUT1 VOUT2 VOUT3
GND
A1 B1 C1
D1
C65008
0.1u 6.3V
0201
R65016 0
0201
3P3V_WW AN
MTP65006
SMD RND 22.8mil
3P3V_WW AN_IN_VR_FB_R [58]
A A
65. +3P3V Load SW
65. +3P3V Load SW
Title:
Title:
Title:
Microsoft Confidential
Microsoft Confidential
Microsoft Confidential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
B
B
B
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
A
A
A
Engineer:
Engineer:
Engineer:
65. +3P3V Load SW
Surface
Surface
Surface
65 79Thursday, April 26, 2018
65 79Thursday, April 26, 2018
1
65 79Thursday, April 26, 2018
1.0.0.1
1.0.0.1
1.0.0.1
5
Vinafix.com
D D
4
3
V3P3_DSW
R6602 10K
PE_CORE
R6637 0
DNP
2
1
PMON[63]
Should these be pull up to 3V3? VCCST?
V3P3_DSW
C C
PROCHOT_N[10,34,60,63]
VRM_PW RGD[22]
SVID_ALERT#[12]
VIDSOUT[12]
VIDSCLK[12]
B B
TEMP_CORE[67,68]
R6638 0 0201
R6639 0 0201
Scale to 0.80V for Psys Max.
Check Psys Settings
R6604 0
VCCST_CPU
PR660410K
R6605100
R6614 0
IMVP8 PROG
R660649.9
R6634 0
IMVP_SCL_P[33]
IMVP_SDA_P[33]
VR_HOT#
VR_READY
SVID_ALERT#_R
R6616 10
R6617 49.9
GND GND
VIDSOUT_R
VIDSCLK_R
C6601
4700p
PR660110K
PR660210K
VDD1V8_CORE ADDR_P_CO RE
R6601
76.8K
DNP
EV2.5 18 Oct 2016
PR661110K
0
DNP
C6608
330p
VSYS
C6603
10V
1u
20%
GND GND
VRM_PW R_EN[22,29]
R6620
0
GND
R6631
57.6K
ALL
GND GND
C6613 DNP
GND
R6636 2M
VDD33_CORE
VDD1V8_CORE
C6604
1u
GND
R6621
61.9K
C6609
330p
GND GND
GND
IREF_CORE
CSSUMA_COR E
CSSUMB_COR E
CSSUMC_CO RE
R6603 133K
R6632 121K
VIN_SEN_CORE
C6602
0.01u
GND
44
VDD33
26
VDD18
37
EN
35
SLP_S0_N
33
SCL_P
32
SDA_P
31
VRHOT_N
30
VRRDY
29
ALT_N
28
SDIO
27
SCLK
25
ADDR_P
24
IREF
C6610
47p
49
EPAD
IMONA_CORE VO RTNC_SA
IMONB_CORE
GND GND GND
36
46
47
PSYS
VIN_SEN
CS_SUMA18CS_SUMB19IMONA21IMONB22IMONC
CS_SUMC
20
IMONC_COR E
R6633 619K
43
PE
TEMP
23
45
PWM638PWM539PWM440PWM341PWM242PWM1
VDIFFC14VFBC15VOSENC16VORTNC
VFBC_SA
R6625 8.06K
34
U6601
STB
CS1 CS2 CS3 CS4 CS5 CS6
VDIFFA
VFBA
VOSENA
VORTNA
VDIFFB
VFBB
VOSENB
VORTNB
MP2949A-003F-C555
17
R6629 0
DNP 0201_P28
C6611
0.1u 16V
0201_p33mm DNP
5 4 3 2 1 48
6
R6607 1.91K
VFBA_CORE
7
VOSENA_CORE
8
VORTNA_CORE
9
10
R6612 2.43K
VFBB_CORE
11
VOSENB_GT
12
VORTNB_GT
13
VOSENC_SA
PR6605 1.5K PR6606 1.5K
PR6608 1.5K PR6610 1.5K
R6608 0
DNP
DNP
R6615 0
DNP
DNP
CSSUMA_COR E
CSSUMB_COR E CSSUMC_CO RE
C66060.1u
GND
C66070.1u
GND
R6622 0
R6623 0
R6610 0R6618
R6611 0
R6627 0
R6628 0
R6619 100
R6624 100
R6609 100
R6613 100
R6626 100
R6630 100
PWM_C ORE1 [67]
PWM_C ORE2 [67]
PWM_GT1 [68]
PWM_SA [67]
SYNC_CORE [67,68]
CS_CORE1 [67] CS_CORE2 [67]
CS_GT1 [68]
CS_SA [67]
VCORE
VCC_CORE_SEN SE [12]
VSS_CORE_SENSE [12]
GND
VCCGT
VCCGT_SENSE [13]
VSSGT_SENSE [13]
GND
VCCSA
VCCSA_SENSE [12]
VSSSA_SENSE [12]
GND
R6635
49.9K
GND GND
A A
5
4
6.3V
C6612 1u
66. VCPU Controller
66. VCPU Controller
66. VCPU Controller
Title:
Title:
Microsoft Conf idential
Microsoft Conf idential
Microsoft Conf idential
Size Project Name Rev
Size Project Name Rev
U SPECIFIC
3
2
Size Project Name Rev
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
A
A
A
Title:
Engineer:
Engineer:
Engineer:
1
Surface
Surface
Surface
1.0.0.1
1.0.0.1
66 79Tuesday, May 01, 2018
66 79Tuesday, May 01, 2018
66 79Tuesday, May 01, 2018
1.0.0.1
5
Vinafix.com
4
3
2
1
9V to 12V
D D
VSYS
Place at DrMOS
U6701
PWM_C ORE1[66]
SYNC_CORE[66,67,68]
TEMP_CORE[66,67,68]
V3P3_DSW
C6702
0402S_P5
6.3V
1u
GND
15 21
PWM
16
SYNC
17
VTEMPFLT
20
VCC
18
CS
DRIVE CONTROL
CS_CORE1[66]
C C
PWM_C ORE2[66]
SYNC_CORE[66,67,68]
TEMP_CORE[66,67,68]
V3P3_DSW
C6703
0402S_P5
6.3V
1u
GND
19
AGND
MP86902B
GND
U6702
15 21
PWM
16
SYNC
17
VTEMPFLT
20
VCC
18
CS
DRIVE CONTROL
CS_CORE2[66]
19
AGND
MP86902B
GND GND
VIN14
HSFET
SW2
LSFET
PGND13 PGND12
PGND511
VIN14
HSFET
SW2
LSFET
PGND13 PGND12
PGND511
BST
VIN1
SW3 SW4
BST
VIN1
SW3 SW4
1 14
2 3 4
13 12 5-11
1 14
2 3 4
13 12 5-11
C6701
1u
CORE1_SW
C6721
470p
DNP
R6721
0
DNP
GND GND GND
C6716
1u
CORE2_SW
C6705
470p
DNP
R6705
0
DNP
GND
C6717 1u
L6704
0.15uH
L6701
0.15uH
PC6702
10u
16V 0603
ALL
Idc 30A/Isat 40A
GND
C6704
C6706
1u
10u
Idc 30A/Isat 40A
GND
PC6701
10u
16V 0603
ALL
+
C6712 220u
+
C6711 220u
C6743
+
47u
DNP
C6714 10u
C6744
+
47u
DNP
C6770
+
47u
C6745
+
47u
C6771
+
47u
C6746
+
47u
DNP
VSYS
GND
C6747
+
47u
1K
R6703
0201S_P28-W35
VCORE
GND
B B
VSYS
Place at DrMOS
U6703
PWM_SA[66]
SYNC_CORE[66,67,68]
TEMP_CORE[66,67,68]
CS_SA[66]
A A
V3P3_DSW
C6708
1u
0402S_P5
6.3V
7 13
PWM
8
SYNC
9
VTEMPFLT
12
VCC
10
CS
11
DRIVE CONTROL
AGND
MP86901-AGQT-Z
HSFET
LSFET
PGND4 PGND5
QFN13_3X3XP8_P4MM
BST
VIN1 VIN6
SW2 SW3
C6713
L6703
0.36uH
9.5A
1u
25V 0402
Idc 11.5A/Isat 9.5A
GND GND
C6719
0805S_1P45
1 6
C6707
1u
25V
0402S_P55
2 3
4 5
SA_SW
470p
C6723
50V
SMC0603
R6723
0
DNP
0603_P6
DNP
47u
DNP
PC6705
10u
16V 0603
C6709
47u
6.3V
0805S_1P45
6.3V
PC6706
10u
16V 0603
C6720 22u
6.3V
0603S_1-W100
DNP
C6710 22u
6.3V
0603S_1-W100
1K
R6704
0201S_P28-W35
VCCSA
67. VCORE VCCSA
67. VCORE VCCSA
67. VCORE VCCSA
Title:
Title:
Microsoft Conf idential
Microsoft Conf idential
Microsoft Conf idential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
C
C
C
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
A
A
A
Title:
Engineer:
Engineer:
Engineer:
1
Surface
Surface
Surface
1.0.0.1
1.0.0.1
67 79Thursday, April 26, 2018
67 79Thursday, April 26, 2018
67 79Thursday, April 26, 2018
1.0.0.1
5
Vinafix.com
D D
4
3
2
VSYS
1
Place at DrMOS
U6801
PWM_GT1[66]
SYNC_CORE[66,67]
C C
TEMP_CORE[66,67]
V3P3_DSW
C6806
6.3V
1u
0402S_P5
GND
15 21
PWM
16
SYNC
17
VTEMPFLT
20
VCC
18
CS
DRIVE CONTROL
CS_GT1[66]
GND
19
MP86902B
AGND
BST
VIN1
VIN14
HSFET
SW2
SW3 SW4
LSFET
PGND13 PGND12
PGND511
1 14
2 3 4
13 12 5-11
C6804 1u
GT1_SW
GND GND
C6801
470p
DNP
R6801
0603_P6
DNP
C6803 1u
25V 0402
GND GND GND
L6801
Idc 30A/Isat 40A
0.1uH
0
GND
+
PC6802
10u
16V 0603
ALL
C6805 220u
PC6801
10u
16V 0603
ALL
GND
C6802
+
47u
1K
R6802
0201S_P28-W35
GND
VCCGT
B B
A A
68. VCCGT
68. VCCGT
Title:
Title:
Title:
Microsoft Confidential
Microsoft Confidential
Microsoft Confidential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
B
B
U SPECIFIC
5
4
3
2
B
Date: Sheet of
Date: Sheet of
Date: Sheet of
A
A
A
Engineer:
Engineer:
Engineer:
68. VCCGT
Surface
Surface
Surface
1
1.0.0.1
1.0.0.1
1.0.0.1
68 79Thursday, April 26, 2018
68 79Thursday, April 26, 2018
68 79Thursday, April 26, 2018
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Vinafix.com
HPD FOR SL1 (ONE/TWO WIRE UART)
U69002
QFN10_1P4X1P8XP55_P4MM
SL_UART_TX[29]
D D
C C
SL_UART_RX[29]
R69001
200K
0201
SL_ADC[2 8]
SL_ADC_RD_EN[27]
R69009
200K
0201
GND GN D
R69006
100K
0201
34
5
GND
GND
SL_UART_SEL_N[27]
3
9
R69014
100
0201
R69019
5.49K
0201
SL_ADC_RD_EN_R
Q69002B NX3008NBKS
OUT1
OUT2
TS3A5223
S1A S1B
SEL1
S2A S2B
SEL2
VCC
GND
5 2 4
7 10 8
3P3VA_SW
1
6
C69003
0.1u 6.3V
0201_p33
4
3P3VA_SW
K
BAT54CW
D69007
A2
R69003
499K
0201
A1
GND
R69028
200
SL_HPD1B_U_MOS
0201
R69029
200
SL_HPD1A_U_MOS
0201
V18MLA0402 NR
ex_dio_0402_p 6mm_aa
PWR_SL PWR_SL_F
A1A2
D69003
GND
R69017
300K
0201
GND
VSYS
3
3P3VA_SW
C69005 100p
25V
0201
2
2
G
SL_HPD1A_U_MOS
SL_HPD1B_U_MOS
R69007
8.06
0402
6
1
MTP_BF69014 SMD RND 31.5mil
MTTP_BF69014 SMD RND 3 1.5mil
R69011
8.06
0402
D
S
C69013
0.1u 6.3V
R69018
8.06
0402
C69006
1u25V
0402
GND
Q69003A
NX3008NBKS
2
G
R69005
PWR_SL_F_C
8.06
0402
6
Q69005A NX3008NBKS
D
S
1
C69012
100p
0201
25V
R69022
200
R69023
200
D69006 PESD24VS1UL
DIO-ESD,SM,PESD24V S1UL,24 V,50 pF,1X.6X.5
A K
D69005 PESD24VS1UL
DIO-ESD,SM,PESD24V S1UL,24 V,50 pF,1X.6X.5
A K
C69010
0.1u
25V
0201
GNDGND
C69011 100p
25V
0201
PWR_SL_F
GNDGNDGNDGN D
PROT_3V3_SW_G [33]
3A
70 OHM
ind_0805_44mil
3A
70 OHM
ind_0805_44mil
L69001
L69002
R69040
A2
D69010
BAT54CW
NX3008NBKS Q69003B
Q69005B NX3008NBKS
C69001
0.1u
25V
0201
249K
0201
A1
K
R69020
100K
0201
3
5
5
D
G
S
4
3
D
G
S
4
C69007
0.1u
25V
0201
1
SL_HPD1A [47]
SL_HPD1B [47]
PWR_SL_F
AK
D69009 RB520CS3002L
6
Q69008A NX3008NBKS
G
GND
3
Q69008B NX3008NBKS
D
S
4
1
GND
D
R69026
C69016
47000p
6.3V DNP
200K
0201 1%
R69027 20K
0201 1%
GND
S
SL_PWR_GOOD_R
R69012 33K
0201
PWR_SL_F
SOT-323
R69004
1K
0603
SL_PWR_GOOD_RR
32
1
GND
Q68001 MMBT3904W T1G
SL_VDET [56 ]
Q69002A NX3008NBKS
6 1
SAM_SL_VDET [ 28]
2
3P3VA_SW
2
B B
SL_PG[27,56]
SAM_SL_5V_EN[27,63]
R69037 200K
0201
GND
GND
R69035 200K
0201 DNP
5
G
A A
5
SL1 port discharger limit PSU anti-arc pulse voltage
69. SF1 POWER
69. SF1 POWER
69. SF1 POWER
Title:
Title:
Microsoft Co nfidential
Microsoft Co nfidential
Microsoft Co nfidential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
4
3
2
Date: Sheet of
A
A
A
Title:
Engineer:
Engineer:
Engineer:
1
Surface
Surface
Surface
1.0.0.1
1.0.0.1
69 79Thursday, April 26, 2018
69 79Thursday, April 26, 2018
69 79Thursday, April 26, 2018
1.0.0.1
5
Vinafix.com
D D
4
3
2
1
C C
MTTP_BF70015 SMD RND 3 1.5mil
MTP_BF70015 SMD RND 31.5mil
V5A
B B
GP_BAT_SHUTDOWN[56 ]
MTP70008
SMD RND 22.8mi l
A A
VDD_BAT
R70043 100 0201
5
R70041 100K
0201
MTP70005
SMD RND 22.8mi l
MTP70006
SMD RND 22.8mi l
R70040
0
0201
V5A_VR_FB_R [5 8]
Battery Connector
MTP_BF70001
R70042 100K
0201
BAT_SHUTDOWN_N
BATT_I2C_DATA[70]
D
Q70007
G
RUM002N02GT2L
S
3P3VA_SW
R70070 200K
0201
BATGONE[27,63]
MTP70007
SMD RND 22.8mi l
BATT_I2C_CLK[70]
TP70005
SMD SQ 29.5mi l
WHEN SHORTED BATTERY TURNS OFF
J70003 2287111-2
1 2 3 4 5 6 7 8
J70001 X950860-001
11223366778
NO-PIN
J70002 2287111-2
1 2 3 4 5 6 7 8
NO-PIN
J70003 to be place North of J70001
8
NOTE: 1.7A/pin
North of Board Edge
Board Edge
C70015
0.1u 10V
0201
MTP_BF70007
SMD RND 31.5mi l
MTP_BF70009
SMD RND 31.5mi l
MTP_BF70011
SMD RND 31.5mi l
MTTP_BF70007
SMD RND 31.5mi l
MTTP_BF70008
SMD RND 31.5mi l
MTTP_BF70009
SMD RND 31.5mi l
SMD RND 31.5mi l
MTP_BF70002
SMD RND 31.5mi l
MTP_BF70003
SMD RND 31.5mi l
MTP_BF70004
SMD RND 31.5mi l
MTP_BF70005
SMD RND 31.5mi l
MTP_BF70006
SMD RND 31.5mi l
MTP_BF70008
SMD RND 31.5mi l
MTP_BF70010
SMD RND 31.5mi l
MTP_BF70012
SMD RND 31.5mi l
MTTP_BF70010
SMD RND 31.5mi l
MTTP_BF70011
SMD RND 31.5mi l
MTTP_BF70012
SMD RND 31.5mi l
Place TP's 0.2 inch apart, Place on component side, near battery. Must be accessible when battery is installed
4
3
MTTP_BF70001
SMD RND 31.5mi l
MTTP_BF70002
SMD RND 31.5mi l
MTTP_BF70003
SMD RND 31.5mi l
MTTP_BF70004
SMD RND 31.5mi l
MTTP_BF70005
SMD RND 31.5mi l
MTTP_BF70006
SMD RND 31.5mi l
L70001
I2C_ROP_SCL[27 ,31,63]
I2C_ROP_SDA[27,31,63]
2
DNP
C70016 100p
0201
DNP
C70017 100p
0 04 02
16V
L70002
0 04 02
16V
0201
BATT_I2C_CLK [70]
MTP70003
SMD RND 22.8mi l
BATT_I2C_DATA [70]
MTP70004
SMD RND 22.8mi l
70. BATT CONN, power input
70. BATT CONN, power input
Title:
Title:
Microsoft Co nfidential
Microsoft Co nfidential
Microsoft Co nfidential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
Date: Sheet of
A
A
A
Title:
Engineer:
Engineer:
Engineer:
1
70. BATT CONN, power input
Surface
Surface
Surface
70 79Thursday, April 26, 2018
70 79Thursday, April 26, 2018
70 79Thursday, April 26, 2018
1.0.0.1
1.0.0.1
1.0.0.1
5
Vinafix.com
D D
4
3
2
1
C C
B B
A A
71. Empty
71. Empty
71. Empty
Surface
Surface
Surface
1
1.0.0.1
1.0.0.1
1.0.0.1
71 79Thursday, April 26, 2018
71 79Thursday, April 26, 2018
71 79Thursday, April 26, 2018
Title:
Title:
Microsoft Confidential
Microsoft Confidential
Microsoft Confidential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
B
B
B
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
A
A
A
Title:
Engineer:
Engineer:
Engineer:
5
Vinafix.com
D D
Q72008
VSYS
R72010 100K
0201
3P3V_PANEL
R72012 22K
C C
R72013 100K
0201
0201
IRLML6402
SOT-23
C72001 1000p 25V
0201
BKLT_EDP_IN_DRI
BKLT_EDP_IN_R
2
S
R72007
1
200K
0201
D
G
5
3
BKLT_EDP_IN_DRI_R
3
D
G
S
4
Q72002B SSM6N15AFU
SOT-363
4
VCC_EDP_BKLT_IN
R72004
2.49K
0402
VCC_EDP_BKLT_IN_DISC
6
D
Q72002A
2
G
SSM6N15AFU
SOT-363
S
1
I2C testpoints are shown on page 25
I2C_SCL_BKLT[25 ]
I2C_SDA_BKLT[25]
3
VCC_EDP_BKLT_IN
R72003 10
SMD RND 22.8mi l
L_BKLT_CTRL_IN[30]
VCC_BKLT
C72004
1u
25V 0402
GND
L_BKLTEN[30]
MTP72009
MTP72003
R72008 1 K
U72001
VIN_D1 VIN_C1
EN
PWM
SCL
SDA
PGND_A2 PGND_B2
GND_D3 GND_C3
RT8555CWSC
C72014
10u
0805 16V
LX_B1 LX_A1
C72013 10u
0805 16V
GND GN D GND
D1 C1
BKLT_EN
B4
B3
A4
A3
A2 B2
D3 C3
GNDGND
VOUT
VCP
FB1
FB2
FB3
FB4
FB5
FB6
C72005
1u
0402 25V
C2
D2
B1 A1
E4
D4
C4
E3
E2
E1
2
L72001
10uH
X950454-001
BKLT_VCP
GND
C72009 1u
BKLT_LX
D72001
A K
PMEG6010CEH
BKLT_FB1 [5 5,72]
BKLT_FB2 [5 5,72]
BKLT_FB3 [5 5,72]
BKLT_FB4 [5 5,72]
BKLT_FB5 [5 5,72]
BKLT_FB6 [5 5]
GND
C72006
2.2u
50V 0805
C72007
2.2u
50V 0805
GND GND
C72008
2.2u
50V 0805
C72015
0.1u 50V
0603
1
VCC_EDP_BKLT_OUT
MTP72001
R72036 499K
0201
7-bit I2C Address = 0x31
SMD RND 22.8mi l
SMD RND 22.8mi l
SMD RND 22.8mi l
SMD RND 22.8mi l
SMD RND 22.8mi l
MTP72004
MTP72005
MTP72006
MTP72007
MTP72008
BKLT_FB1 [55 ,72]
BKLT_FB2 [55 ,72]
BKLT_FB3 [55 ,72]
BKLT_FB4 [55 ,72]
BKLT_FB5 [55 ,72]
isolated ground on layer 2 to tie Cin GND, Cout GND, and controller PGND together. Then tie this isolated ground plane to main GND under the exposed pads.
B B
A A
72. Backlight Controller
72. Backlight Controller
Title:
Title:
Microsoft Co nfidential
Microsoft Co nfidential
Microsoft Co nfidential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
A
A
A
Title:
Engineer:
Engineer:
Engineer:
1
72. Backlight Controller
Surface
Surface
Surface
72 79Tuesday, May 01, 2 018
72 79Tuesday, May 01, 2 018
72 79Tuesday, May 01, 2 018
1.0.0.1
1.0.0.1
1.0.0.1
5
Vinafix.com
D D
4
3
2
1
C C
B B
A A
73. Empty
73. Empty
73. Empty
1
1.0.0.1
1.0.0.1
1.0.0.1
73 XXThursday, April 26, 2018
73 XXThursday, April 26, 2018
73 XXThursday, April 26, 2018
Title:
Title:
Title:
Microsoft Confidential
Microsoft Confidential
Microsoft Confidential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
B
B
B
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
A
A
A
Engineer:
Engineer:
Engineer:
5
Vinafix.com
D D
4
3
2
1
C C
B B
A A
74. Empty
74. Empty
74. Empty
1
1.0.0.1
1.0.0.1
1.0.0.1
74 XXThursday, April 26, 2018
74 XXThursday, April 26, 2018
74 XXThursday, April 26, 2018
Title:
Title:
Title:
Microsoft Confidential
Microsoft Confidential
Microsoft Confidential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
B
B
B
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
A
A
A
Engineer:
Engineer:
Engineer:
5
Vinafix.com
4
3
2
1
J75001
D D
1
1
J75005
C C
1
1
3
3
3
3
2
M1030044-001
2
2
2
M1030044-001
J75002
J75006
J75003
1
1
1
1
3
3
3
3
2
M1030044-001
2
2
2
M1030044-001
J75007
1
1
1
1
3
3
3
3
2
M1030044-001
2
2
2
M1030044-001
J75004
1
1
3
3
2
M1030044-001
2
B B
A A
75. Clips
75. Clips
Title:
Title:
Microsoft Confidential
Microsoft Confidential
Microsoft Confidential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
B
B
U SPECIFIC
5
4
3
2
B
Date: Sheet of
Date: Sheet of
Date: Sheet of
A
A
A
Title:
Engineer:
Engineer:
Engineer:
75. Clips
Surface
Surface
Surface
1
1.0.0.1
1.0.0.1
1.0.0.1
75 79Thursday, April 26, 2018
75 79Thursday, April 26, 2018
75 79Thursday, April 26, 2018
5
Vinafix.com
BOTTOM SIDE spacers
3
3
1
1
3
3
1
1
3
3
1
1
2
2
MP76021 M1009352-002
MP76024 M1009352-002
2
2
MP76033 M1012486-001
2
2
4
4
4
VCCGT
4
4
4
D D
3
3
1
1
3
3
1
1
3
3
1
1
2
2
MP76023 M1009352-002
MP76025 M1009352-002
2
2
MP76032 M1012486-001
2
2
4
4
4
4
TOP SIDE spacers TOP SIDE spacers
4
4
3
3
1
1
3
3
1
1
3
3
1
1
2
2
MP76027 M1009352-002
MP76026 M1009352-002
2
2
MP76037 M1012486-001
2
2
4
4
4
4
4
4
3
3
4
4
1
1
3
3
4
4
1
1
3
3
4
4
1
1
2
2
MP76029 M1009352-002
MP76028 M1009352-002
2
2
MP76038 M1012486-001
2
2
4
3
3
1
1
3
3
1
1
2
2
2
2
MP76031 M1009352-002
MP76030 M1009352-002
4
4
4
4
3
3
1
1
3
3
1
1
3
3
1
1
2
2
MP76035 M1009352-002
MP76036 M1009352-002
2
2
MP76040 M1012486-001
2
2
4
4
4
4
4
4
4
4
3
MTP_BF76004
SMD RND 31.5m il
MTP_BF76005
SMD RND 31.5m il
MTP_BF76006
3
MP76034 M1009352-002
3
2
2
4
1
1
MP76041
3
M1012486-001
3
2
2
4
1
1
SMD RND 31.5m il
V0P85A
VCCGT
VCCSA
VCCIO
VCCST_CPU
VCCSTG
MTP76001
SMD RND 22.8m il
MTP76003
SMD RND 22.8m il
MTP76004
SMD RND 22.8m il
MTP76005
SMD RND 22.8m il
MTP76006
SMD RND 22.8m il
MTP76007
SMD RND 22.8m il
2
MTTP_BF76004
SMD RND 31.5m il
MTTP_BF76005
SMD RND 31.5m il
MTTP_BF76006
SMD RND 31.5m il
1
C C
H76002
1
1
NO-MSPN-157
1
NO-MSPN-159
NO-MSPN-159
Title:
Title:
Title:
Engineer:
Engineer:
Engineer:
H76001
1
NO-MSPN-157
MTP76010
SMD RND 22.8m il
MTP76011
SMD RND 22.8m il
MTP76012
SMD RND 22.8m il
76. TP's and Mech
76. TP's and Mech
76. TP's and Mech
Surface
Surface
Surface
1
1.0.0.1
1.0.0.1
76 79Thursday, April 26, 2018
76 79Thursday, April 26, 2018
76 79Thursday, April 26, 2018
1.0.0.1
Shield Fences
SOC/SSD
SHT76001
B B
COAX Clips
MP76013
FCAU137A02C5PC
X943446-001
1
MP76014
FCAU137A02C5PC
X943446-001
1
MP76016
FCAU137A02C5PC
X943446-001
1
A A
PEMNUT for XDP
MP76042
1
1
M1019383-001
5
4
MP76015
FCAU137A02C5PC
X943446-001
1
MP76017
FCAU137A02C5PC
X943446-001
1
PEMNUT for SoCs
MP76002 M1019199-001
MP76003 M1019199-001
MP76004 M1019199-001
MP76005 M1019199-001
SHIELD
1
M1016647-001
ZID = 00 ZOD = 00
SHT76003
SHIELD
1
X949515-001
ZID = 00 ZOD = 00
SHT76005
SHIELD
1
X949517-001
ZID = 00 ZOD = 00
SHT76007
SHIELD
1
M1016652-001
ZID = 00 ZOD = 00
SHT76009
SHIELD
1
M1013613-001
ZID = 00 ZOD = 00
SHT76010
SHIELD
1
X949524-001
ZID = 00 ZOD = 00
3
Charger
Backlight/USB
Display/Camera
SHT76008
SHIELD
1
Trackpad
X949521-001
ZID = 00 ZOD = 00
Surflink
SHT76002
SHIELD
1
X949514-001
ZID = 00 ZOD = 00
SHT76004
SHIELD
1
M1016649-001
ZID = 00 ZOD = 00
SHT76006
SHIELD
1
M1016651-001
ZID = 00 ZOD = 00
Wi-Fi
PMIC
Audio
G5/Touch
SHB76003
SHIELD
1
M1016654-001
ZID = 00 ZOD = 00
2.3mm NPTH
H76022
NP
NO-MSPN-00212
1
H76010
NP
NO-MSPN-159
1
Touch
H76016
NP
NO-MSPN-159
1
U SPECIFIC
2
2.5mm NPTH
H76011
NP
NO-MSPN-159
1
H76017
NP
NO-MSPN-159
1
H76012
NP
NO-MSPN-159
1
H76018
NP
NO-MSPN-159
1
V1P2U
V0P6DX_LPDDR3
VCORE
H76013
NP
NO-MSPN-159
1
H76019
NP
NO-MSPN-159
1
Microsoft Conf idential
Microsoft Conf idential
Microsoft Conf idential
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
H76014
NP
1
H76020
NP
1
A
A
A
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