Microchip Technology Inc PIC16C924-CL Datasheet

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

1997 Microchip Technology Inc. DS30444E - page 1

PIC16C9XX

8-Bit CMOS Microcontroller with LCD Driver

Devices included in this data sheet:

• PIC16C923

• PIC16C924

Microcontroller Core Features:

• High performance RISC CPU

• Only 35 single word instructions to learn

• 4K x 14 on-chip EPROM program memory

• 176 x 8 general purpose registers (SRAM)

• All single cycle instructions (500 ns) except for program branches which are two-cycle

• Operating speed: DC - 8 MHz clock input

DC - 500 ns instruction cycle

• Interrupt capability

• Eight level deep hardware stack

• Direct, indirect and relative addressing modes

Peripheral Features:

• 25 I/O pins with individual direction control

• 25-27 input only pins

• Timer0: 8-bit timer/counter with 8-bit prescaler

• Timer1: 16-bit timer/counter, can be incremented during sleep via external crystal/clock

• Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler

• One pin that can be conﬁgured a capture input, PWM output, or compare output

- Capture is 16-bit, max. resolution 31.25 ns

- Compare is 16-bit, max. resolution 500 ns

- PWM max resolution is 10-bits.

Maximum PWM frequency @ 8-bit resolution = 32 kHz, @ 10-bit resolution = 8 kHz

• Programmable LCD timing module

- Multiple LCD timing sources available

- Can drive LCD panel while in Sleep mode

- Static, 1/2, 1/3, 1/4 multiplex

- Static drive and 1/3 bias capability

- 16 bytes of dedicated LCD RAM

- Up to 32 segments, up to 4 commons

Common Segment Pixels

13232 23162 33090 4 29 116

Available in Die Form

• Synchronous Serial Port (SSP) with SPI



and I



• 8-bit multi-channel Analog to Digital converter (PIC16C924 only)

Special Microcontroller Features:

• Power-on Reset (POR)

• Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)

• Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation

• Programmable code-protection

• Power saving SLEEP mode

• Selectable oscillator options

• In-Circuit Serial Programming™ (via two pins)

CMOS Tec hnology

• Low-power, high-speed CMOS EPROM technology

• Fully static design

• Wide operating voltage range: 2.5V to 6.0V

• Commercial and Industrial temperature ranges

• Low-power consumption:

- < 2 mA @ 5.5V, 4 MHz

- 22.5 µ A typical @ 4V, 32 kHz

- < 1 µ A typical standby current @ 3.0V

ICSP is a trademark of Microchip Technology Inc. I

C is a trademark of Philips Corporation. SPI is a trademark of Motorola Corporation.

PIC16C9XX

DS30444E - page 2



1997 Microchip Technology Inc.

Pin Diagrams

TQFP

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

646362616059585756555453525150

171819202122232425262728293031

PIC16C923

RD5/SEG29/COM3 RG6/SEG26

RG3/SEG23 RG2/SEG22 RG1/SEG21 RG0/SEG20 RF7/SEG19 RF6/SEG18 RF5/SEG17 RF4/SEG16 RF3/SEG15 RF2/SEG14 RF1/SEG13 RF0/SEG12

RA4/T0CKI

RA5/SS

RB1

RB0/INT

RC3/SCK/SCL

RC4/SDI/SDA

RC5/SDO

LCD2

LCD3

VDD

VSS

C1 C2

OSC1/CLKIN

OSC2/CLKOUT

RC0/T1OSO/T1CKI

RA3

RA2

VSSRA1

RA0

RB2

RB3

RB4

RB5

RB7

RB6

VDDCOM0

RD7/SEG31/COM1

RD6/SEG30/COM2

RC1/T1OSI

RC2/CCP1

LCD1

VLCDADJ

RD0/SEG00

RD1/SEG01

RD2/SEG02

RD3/SEG03

RD4/SEG04

RE0/SEG05

RE1/SEG06

RE2/SEG07

RE3/SEG08

RE4/SEG09

RE6/SEG11

RE5/SEG10

RG5/SEG25 RG4/SEG24

MCLR/VPP

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44

987654321

68676665646362

2728293031323334353637383940414243

PIC16C923

RD5/SEG29/COM3 RG6/SEG26 RG5/SEG25 RG4/SEG24 RG3/SEG23 RG2/SEG22 RG1/SEG21 RG0/SEG20 RG7/SEG28 RF7/SEG19 RF6/SEG18 RF5/SEG17 RF4/SEG16 RF3/SEG15 RF2/SEG14 RF1/SEG13 RF0/SEG12

RA4/T0CKI

RA5/SS

RB1

RB0/INT

RC3/SCK/SCL

RC4/SDI/SDA

RC5/SDO

LCD2

LCD3

VDD

VSS

C1 C2

OSC1/CLKIN

OSC2/CLKOUT

RC0/T1OSO/T1CKI

RA3

RA2

VSSRA1

RA0

RB2

RB3

MCLR

/VPP

N/C

RB4

RB5

RB7

RB6

VDDCOM0

RD7/SEG31/COM1

RD6/SEG30/COM2

RC1/T1OSI

RC2/CCP1

LCD1

VLCDADJ

RD0/SEG00

RD1/SEG01

RD2/SEG02

RD3/SEG03

RD4/SEG04

RE7/SEG27

RE0/SEG05

RE1/SEG06

RE2/SEG07

RE3/SEG08

RE4/SEG09

RE6/SEG11

RE5/SEG10

PLCC

Input Pin Output Pin

Digital Input/LCD Output Pin

LEGEND:

Input/Output Pin

LCD Output Pin

Shrink PDIP (750 mil)

RB4 RB5 RB7 RB6 V

COM0 RD7/SEG31/COM1 RD6/SEG30/COM2 RD5/SEG29/COM3 RG6/SEG26 RG5/SEG25 RG4/SEG24

RG3/SEG23 RG2/SEG22 RG1/SEG21 RG0/SEG20 RF7/SEG19 RF6/SEG18 RF5/SEG17 RF4/SEG16

MCLR/VPP

RB3 RB2

RA0 RA1

RA2

RA4/T0CKI

RA5/SS

RB1

RB0/INT

RC3/SCK/SCL

RC4/SDI/SDA

RC5/SDO

LCD2

LCD3

VSS

C1 C2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45

PIC16C923

OSC1/CLKIN

OSC2/CLKOUT

RC0/T1OSO/T1CKI

RC1/T1OSI

RC2/CCP1

VLCD1

VLCDADJ RD0/SEG00 RD1/SEG01 RD2/SEG02 RD3/SEG03

21 22 23 24 25 26 27 28 29 30 31 32

RA3

40 39 38 37 36 35 34 33

44 43 42 41

RF3/SEG15 RF2/SEG14 RF1/SEG13 RF0/SEG12 RE6/SEG11 RE5/SEG10 RE4/SEG09 RE3/SEG08 RE2/SEG07 RE1/SEG06 RE0/SEG05 RD4/SEG04

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1997 Microchip Technology Inc. DS30444E - page 3

PIC16C9XX

Pin Diagrams (Cont.’d)

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44

987654321

68676665646362

2728293031323334353637383940414243

PIC16C924

RD5/SEG29/COM3 RG6/SEG26 RG5/SEG25 RG4/SEG24 RG3/SEG23 RG2/SEG22 RG1/SEG21 RG0/SEG20 RG7/SEG28 RF7/SEG19 RF6/SEG18 RF5/SEG17 RF4/SEG16 RF3/SEG15 RF2/SEG14 RF1/SEG13 RF0/SEG12

RA4/T0CKI

RA5/AN4/SS

RB1

RB0/INT

RC3/SCK/SCL

RC4/SDI/SDA

RC5/SDO

LCD2

LCD3

VDD

VSS

C1 C2

OSC1/CLKIN

OSC2/CLKOUT

RC0/T1OSO/T1CKI

RA3/AN3/VREF

RA2/AN2

VSSRA1/AN1

RA0/AN0

RB2

RB3

MCLR

/VPP

N/C

RB4

RB5

RB7

RB6

VDDCOM0

RD7/SEG31/COM1

RD6/SEG30/COM2

RC1/T1OSI

RC2/CCP1

LCD1

VLCDADJ

RD0/SEG00

RD1/SEG01

RD2/SEG02

RD3/SEG03

RD4/SEG04

RE7/SEG27

RE0/SEG05

RE1/SEG06

RE2/SEG07

RE3/SEG08

RE4/SEG09

RE6/SEG11

RE5/SEG10

PLCC

TQFP

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

646362616059585756555453525150

171819202122232425262728293031

PIC16C924

RD5/SEG29/COM3 RG6/SEG26

RG3/SEG23 RG2/SEG22 RG1/SEG21 RG0/SEG20 RF7/SEG19 RF6/SEG18 RF5/SEG17 RF4/SEG16 RF3/SEG15 RF2/SEG14 RF1/SEG13 RF0/SEG12

RA4/T0CKI

RA5/AN4/SS

RB1

RB0/INT

RC3/SCK/SCL

RC4/SDI/SDA

RC5/SDO

LCD2

LCD3

VDD

VSS

C1 C2

OSC1/CLKIN

OSC2/CLKOUT

RC0/T1OSO/T1CKI

RA3/AN3/VREF

RA2/AN2

VSSRA1/AN1

RA0/AN0

RB2

RB3

RB4

RB5

RB7

RB6

VDDCOM0

RD7/SEG31/COM1

RD6/SEG30/COM2

RC1/T1OSI

RC2/CCP1

LCD1

VLCDADJ

RD0/SEG00

RD1/SEG01

RD2/SEG02

RD3/SEG03

RD4/SEG04

RE0/SEG05

RE1/SEG06

RE2/SEG07

RE3/SEG08

RE4/SEG09

RE6/SEG11

RE5/SEG10

RG5/SEG25 RG4/SEG24

MCLR/VPP

Input Pin Output Pin

Digital Input/LCD Output Pin

LEGEND:

Input/Output Pin

LCD Output Pin

Shrink PDIP (750 mil)

RB4 RB5 RB7 RB6 V

COM0 RD7/SEG31/COM1 RD6/SEG30/COM2 RD5/SEG29/COM3 RG6/SEG26 RG5/SEG25 RG4/SEG24

RG3/SEG23 RG2/SEG22 RG1/SEG21 RG0/SEG20 RF7/SEG19 RF6/SEG18 RF5/SEG17 RF4/SEG16

MCLR/VPP

RB3

RB2 RA0/AN0 RA1/AN1

VSS

RA2/AN2

RA4/T0CKI

RA5/AN4/SS

RB1

RB0/INT

RC3/SCK/SCL

RC4/SDI/SDA

RC5/SDO

LCD2

LCD3

VSS

C1 C2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45

PIC16C924

OSC1/CLKIN

OSC2/CLKOUT

RC0/T1OSO/T1CKI

RC1/T1OSI

RC2/CCP1

LCD1

VLCDADJ RD0/SEG00 RD1/SEG01 RD2/SEG02 RD3/SEG03

21 22 23 24 25 26 27 28 29 30 31 32

RA3/AN3/V

REF

40 39 38 37 36 35 34 33

44 43 42 41

RF3/SEG15 RF2/SEG14 RF1/SEG13 RF0/SEG12 RE6/SEG11 RE5/SEG10 RE4/SEG09 RE3/SEG08 RE2/SEG07 RE1/SEG06 RE0/SEG05 RD4/SEG04

PIC16C9XX

DS30444E - page 4



1997 Microchip Technology Inc.

Table of Contents

1.0 General Description..................................................................................................................................................................... 5

2.0 PIC16C9XX Device Varieties...................................................................................................................................................... 7

3.0 Architectural Overview ................................................................................................................................................................ 9

4.0 Memory Organization................................................................................................................................................................ 17

5.0 Ports.......................................................................................................................................................................................... 31

6.0 Overview of Timer Modules....................................................................................................................................................... 43

7.0 Timer0 Module .......................................................................................................................................................................... 45

8.0 Timer1 Module .......................................................................................................................................................................... 51

9.0 Timer2 Module .......................................................................................................................................................................... 55

10.0 Capture/Compare/PWM (CCP) Module .................................................................................................................................... 57

11.0 Synchronous Serial Port (SSP) Module .................................................................................................................................... 63

12.0 Analog-to-Digital Converter (A/D) Module.................................................................................................................................79

13.0 LCD Module .............................................................................................................................................................................. 89

14.0 Special Features of the CPU...................................................................................................................................................103

15.0 Instruction Set Summary......................................................................................................................................................... 119

16.0 Development Support.............................................................................................................................................................. 137

17.0 Electrical Characteristics......................................................................................................................................................... 141

18.0 DC and AC Characteristics Graphs and Tables......................................................................................................................161

19.0 Packaging Information............................................................................................................................................................. 171

Appendix A: ................................................................................................................................................................................... 175

Appendix B: Compatibility ............................................................................................................................................................. 175

Appendix C: What’s New................................................................................................................................................................ 176

Appendix D: What’s Changed........................................................................................................................................................ 176

Index .................................................................................................................................................................................................. 177

List of Equations And Examples ........................................................................................................................................................ 181

List of Figures..................................................................................................................................................................................... 181

List of Tables...................................................................................................................................................................................... 182

Reader Response.............................................................................................................................................................................. 186

PIC16C9XX Product Identification System........................................................................................................................................ 187

To Our Valued Customers

We constantly strive to improve the quality of all our products and documentation. We have spent an exceptional amount of time to ensure that these documents are correct. However, we realize that we may have missed a few things. If you ﬁnd any information that is missing or appears in error, please use the reader response form in the back of this data sheet to inform us. We appreciate your assistance in making this a better document.



1997 Microchip Technology Inc. DS30444E- page 5

PIC16C9XX

1.0 GENERAL DESCRIPTION

The PIC16C9XX is a family of

low-cost, high-performance, CMOS, fully-static, 8-bit microcontrollers with an integrated LCD Driver module, in the PIC16CXXX mid-range family.

All PICmicro™ microcontrollers employ an advanced RISC architecture. The PIC16CXXX microcontroller family has enhanced core features, eight-level deep stack, and multiple internal and external interrupt sources. The separate instruction and data buses of the Harvard architecture allow a 14-bit wide instruction word with the separate 8-bit wide data. The two stage instruction pipeline allows all instructions to execute in a single cycle, except for program branches (which require two cycles). A total of 35 instructions (reduced instruction set) are available. Additionally, a large register set gives some of the architectural innovations used to achieve a very high performance.

PIC16CXXX microcontrollers typically achieve a 2:1 code compression and a 4:1 speed improvement over other 8-bit microcontrollers in their class.

The PIC16C923 devices have 176 bytes of RAM and 25 I/O pins. In addition several peripheral features are available including: three timer/counters, one Capture/Compare/PWM module, one serial port and one LCD module. The Synchronous Serial Port can be conﬁgured as either a 3-wire Serial Peripheral Interface (SPI) or the two-wire Inter-Integrated Circuit (I

The PIC16C924 devices have 176 bytes of RAM and 25 I/O pins. In addition several peripheral features are available including: three timer/counters, one Capture/Compare/PWM module, one serial port and one LCD module. The Synchronous Serial Port can be conﬁgured as either a 3-wire Serial Peripheral Interface (SPI) or the two-wire Inter-Integrated Circuit (I

C) bus. The LCD module features programmable multiplex mode (static, 1/2, 1/3 and 1/4) and drive bias (static and 1/3). It is capable of driving up to 32 segments and up to 4 commons. It can also drive the LCD panel while in SLEEP mode. The PIC16C924 also has an 5-channel high-speed 8-bit A/D. The 8-bit resolution is ideally suited for applications requiring low-cost analog interface, e.g. thermostat control, pressure sensing, and meters.

The PIC16C9XX family has special features to reduce external components, thus reducing cost, enhancing system reliability and reducing power consumption. There are four oscillator options, of which the single pin RC oscillator provides a low-cost solution, the LP oscillator minimizes power consumption, XT is a standard crystal, and the HS is for High Speed crystals. The SLEEP (power-down) feature provides a power saving

mode. The user can wake up the chip from SLEEP through several external and internal interrupts and reset(s).

A highly reliable Watchdog Timer with its own on-chip RC oscillator provides recovery in the event of a software lock-up.

A UV erasable CERQUAD (compatible with PLCC) packaged version is ideal for code development while the cost-effective One-Time-Programmable (OTP) version is suitable for production in any volume.

The PIC16C9XX family ﬁts perfectly in applications ranging from handheld meters, thermostats, to home security products. The EPROM technology makes customization of application programs (LCD panels, calibration constants, sensor interfaces, etc.) extremely fast and convenient. The small footprint pac kages make this microcontroller series perfect for all applications with space limitations. Lo w cost, low power , high perf ormance, ease of use and I/O ﬂexibility make the PIC16C9XX very versatile even in areas where no microcontroller use has been considered before (e.g. timer functions, capture and compare, PWM functions and coprocessor applications).

1.1 F

amily and Upward Compatibility

Users familiar with the PIC16C5X microcontroller family will realize that this is an enhanced version of the PIC16C5X architecture. Please refer to Appendix A for a detailed list of enhancements. Code written for the PIC16C5X can be easily ported to the PIC16CXXX family of devices (Appendix B).

1.2 De

velopment Support

PIC16C9XX devices are supported by the complete line of Microchip Development tools.

Please refer to Section 16.0 for more details about Microchip’s development tools.

PIC16C9XX

DS30444E - page 6

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1997 Microchip Technology Inc.

TABLE 1-1: PIC16C9XX FAMILY OF DEVICES

PIC16C923

PIC16C924

Clock

Maximum Frequency of Operation (MHz) 8 8

Memory

EPROM Program Memory 4K 4K Data Memory (bytes) 176 176

Peripherals

Timer Module(s) TMR0,

TMR1, TMR2

TMR0, TMR1,

TMR2 Capture/Compare/PWM Module(s) 1 1 Serial Port(s)

(SPI/I

C, USART)

SPI/I

C SPI/I

Parallel Slave Port — — A/D Converter (8-bit) Channels — 5 LCD Module 4 Com,

32 Seg

4 Com,

32 Seg

Features

Interrupt Sources 8 9 I/O Pins 25 25 Input Pins 27 27 Voltage Range (Volts) 2.5-6.0 2.5-6.0 In-Circuit Serial Programming Yes Yes Brown-out Reset — — Packages 64-pin SDIP,

TQFP; 68-pin PLCC, Die

64-pin SDIP,

TQFP;

68-pin PLCC,

Die

All PICmicro Family devices ha v e Power-on Reset, selectable Watchdog Timer , selectab le code protect and high I/O current capability . All PIC16C9XX Family devices use serial programming with clock pin RB6 and data pin RB7.



1997 Microchip Technology Inc. DS30444E - page 7

PIC16C9XX

2.0 PIC16C9XX DEVICE VARIETIES

A variety of frequency ranges and packaging options are available . Depending on application and production requirements, the proper device option can be selected using the information in the PIC16C9XX Product Identiﬁcation System section at the end of this data sheet. When placing orders, please use that page of the data sheet to specify the correct part number.

For the PIC16C9XX family, there are two device “types” as indicated in the device number:

1. C , as in PIC16 C 924. These devices have EPROM type memory and operate over the standard voltage range.

2. LC , as in PIC16 LC 924. These devices have EPROM type memory and operate over an extended voltage range.

2.1 UV Erasab

le Devices

The UV erasable version, offered in CERQUAD package, is optimal for prototype dev elopment and pilot programs.

The UV erasable version can be erased and reprogrammed to any of the conﬁguration modes. Microchip's PICSTART



Plus and PRO MATE



II programmers both support the PIC16C9XX. Third party programmers also are available; refer to the

Microchip

Third Party Guide

for a list of sources.

2.2 One-Time-Pr

ogrammable (OTP)

Devices

The availability of OTP devices is especially useful for customers who need the ﬂexibility for frequent code updates and small volume applications.

The OTP devices , packaged in plastic packages, permit the user to program them once. In addition to the program memory, the conﬁguration bits must also be programmed.

2.3 Quic

k-Turnaround-Production (QTP)

Devices

Microchip offers a QTP Programming Service for factory production orders. This service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabilized. The devices are identical to the OTP devices but with all EPROM locations and conﬁguration options already programmed by the factory. Certain code and prototype veriﬁcation procedures apply before production shipments are available. Please contact your local Microchip Technology sales ofﬁce for more details.

2.4 Serializ

ed Quick-Turnaround

Production (SQTP

) De

vices

Microchip offers a unique programming service where a few user-deﬁned locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random or sequential.

Serial programming allows each device to have a unique number which can serve as an entry-code, password or ID number.

PIC16C9XX

DS30444E - page 8



1997 Microchip Technology Inc.

NOTES:



1997 Microchip Technology Inc. DS30444E - page 9

PIC16C9XX

3.0 ARCHITECTURAL OVERVIEW

The high performance of the PIC16CXXX family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16CXXX uses a Harvard architecture, in which, program and data are accessed from separate memories using separate buses. This improves bandwidth over traditional von Neumann architecture where program and data are fetched from the same memory using the same bus. Separating program and data buses further allows instructions to be sized differently than the 8-bit wide data word. Instruction opcodes are 14-bits wide making it possible to have all single word instructions. A 14-bit wide progr am memory access bus fetches a 14-bit instruction in a single cycle. A two-stage pipeline overlaps fetch and execution of instructions (Example 3-1). Consequently, all instructions execute in a single cycle (500 ns @ 8 MHz) e xcept for program branches.

The PIC16C923 and PIC16C924 both address 4K x 14 of program memory and 176 x 8 of data memory.

The PIC16CXXX can directly or indirectly address its register ﬁles or data memory. All special function registers, including the program counter, are mapped in the data memory. The PIC16CXXX has an orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. This symmetrical nature and lack of ‘special optimal situations’ make programming with the PIC16CXXX simple yet efﬁcient, thus signiﬁcantly reducing the learning curve.

PIC16CXXX devices contain an 8-bit ALU and working register. The ALU is a general purpose ar ithmetic unit. It performs arithmetic and Boolean functions between the data in the working register and any register ﬁle.

The ALU is 8-bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically one operand is the working register (W register). The other operand is a ﬁle register or an immediate constant. In single operand instructions, the operand is either the W register or a ﬁle register.

The W register is an 8-bit working register used f or ALU operations. It is not an addressable register.

Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC), and Zero (Z) bits in the STATUS register. The C and DC bits operate as a borro

w bit and a digit borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.

PIC16C9XX

DS30444E - page 10

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1997 Microchip Technology Inc.

FIGURE 3-1: PIC16C923 BLOCK DIAGRAM

EPROM

Program

Memory

4K x 14

Data Bus

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

RAM

File

Registers

176 x 8

Direct Addr

RAM Addr

Addr MUX

Indirect

Addr

FSR reg

STATUS reg

MUX

ALU

W reg

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKIN

OSC2/CLKOUT

MCLR

PORTA

PORTB

PORTC

PORTD

PORTE

RA4/T0CKI RA5/SS

RB0/INT

RB1-RB7

RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO

RD0-RD4/SEGnn

RE0-RE7/SEGnn

LCD

Synchronous

Timer0

Timer1, Timer2,

RA3

RA2

RA1

RA0

CCP1

Serial Port

VLCD1

PORTF

PORTG

RF0-RF7/SEGnn

RG0-RG7/SEGnn

RD5-RD7/SEGnn/COMn

COM0

VDD, VSS

VLCD2 V

LCD3

C1 C2 VLCDADJ

 1997 Microchip Technology Inc. DS30444E - page 11

PIC16C9XX

FIGURE 3-2: PIC16C924 BLOCK DIAGRAM

EPROM

Program

Memory

4K x 14

Data Bus

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

RAM

File

Registers

176 x 8

Direct Addr

RAM Addr

Addr MUX

Indirect

Addr

FSR reg

STATUS reg

MUX

ALU

W reg

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKIN OSC2/CLKOUT

MCLR

PORTA

PORTB

PORTC

PORTD

PORTE

RA4/T0CKI RA5/AN4/SS

RB0/INT

RB1-RB7

RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO

RD0-RD4/SEGnn

RE0-RE7/SEGnn

LCD

Synchronous

Timer0

Timer1, Timer2,

RA3/AN3/VREF

RA2/AN2

RA1/AN1

RA0/AN0

CCP1

Serial Port

PORTF

PORTG

RF0-RF7/SEGnn

RG0-RG7/SEGnn

RD5-RD7/SEGnn/COMn

VDD, VSS

A/D

VLCD1

COM0 VLCD2

LCD3

C1 C2 VLCDADJ

PIC16C9XX

DS30444E - page 12  1997 Microchip Technology Inc.

TABLE 3-1: PIC16C9XX PINOUT DESCRIPTION

Pin Name

DIP

Pin#

PLCC

Pin#

TQFP

Pin#

Type

Buffer

Type

Description

OSC1/CLKIN 22 24 14 I ST/CMOS Oscillator crystal input or external clock source input. This

buffer is a Schmitt Trigger input when conﬁgured in RC oscillator mode and a CMOS input otherwise.

OSC2/CLKOUT 23 25 15 O — Oscillator crystal output. Connects to crystal or resonator

in crystal oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate.

MCLR/VPP 1 2 57 I/P ST Master clear (reset) input or programming voltage input.

This pin is an active low reset to the device. PORTA is a bi-directional I/O port. The AN and VREF multi-

plexed functions are used by the PIC16C924 only. RA0/AN0 4 5 60 I/O TTL RA0 can also be Analog input0. RA1/AN1 5 6 61 I/O TTL RA1 can also be Analog input1. RA2/AN2 7 8 63 I/O TTL RA2 can also be Analog input2. RA3/AN3/VREF 8 9 64 I/O TTL RA3 can also be Analog input3 or A/D Voltage Refer-

ence.

RA4/T0CKI 9 10 1 I/O ST RA4 can also be the clock input to the Timer0

timer/counter. Output is open drain type.

RA5/AN4/SS 10 11 2 I/O TTL RA5 can be the slave select for the synchronous serial

port or Analog input4.

PORTB is a bi-directional I/O port. PORTB can be softw are

programmed for internal weak pull-ups on all inputs. RB0/INT 12 13 4 I/O TTL/ST RB0 can also be the external interrupt pin. This buffer

is a Schmitt Trigger input when conﬁgured as an exter-

nal interrupt. RB1 11 12 3 I/O TTL RB2 3 4 59 I/O TTL RB3 2 3 58 I/O TTL RB4 64 68 56 I/O TTL Interrupt on change pin. RB5 63 67 55 I/O TTL Interrupt on change pin. RB6 61 65 53 I/O TTL/ST Interrupt on change pin. Serial programming clock.

This buffer is a Schmitt Trigger input when used in

serial programming mode. RB7 62 66 54 I/O TTL/ST Interrupt on change pin. Serial programming data.

This buffer is a Schmitt Trigger input when used in

serial programming mode.

PORTC is a bi-directional I/O port.

RC0/T1OSO/T1CKI 24 26 16 I/O ST RC0 can also be the Timer1 oscillator output or

Timer1 clock input. RC1/T1OSI 25 27 17 I/O ST RC1 can also be the Timer1 oscillator input. RC2/CCP1 26 28 18 I/O ST RC2 can also be the Capture1 input/Compare1 out-

put/PWM1 output. RC3/SCK/SCL 13 14 5 I/O ST RC3 can also be the synchronous serial clock

input/output for both SPI and I

C modes.

RC4/SDI/SDA 14 15 6 I/O ST RC4 can also be the SPI Data In (SPI mode) or data

I/O (I2C mode). RC5/SDO 15 16 7 I/O ST RC5 can also be the SPI Data Out (SPI mode). C1 16 17 8 P LCD Voltage Generation. C2 17 18 9 P LCD Voltage Generation.

Legend: I = input O = output P = power L = LCD Driver

— = Not used TTL = TTL input ST = Schmitt Trigger input

 1997 Microchip Technology Inc. DS30444E - page 13

PIC16C9XX

COM0 59 63 51 L Common Driver0

PORTD is a digital input/output port. These pins are also

used as LCD Segment and/or Common Drivers.

RD0/SEG00 29 31 21 I/O/L ST

Segment Driver00/Digital Input/Output.

RD1/SEG01 30 32 22 I/O/L ST

Segment Driver01/Digital Input/Output.

RD2/SEG02 31 33 23 I/O/L ST

Segment Driver02/Digital Input/Output.

RD3/SEG03 32 34 24 I/O/L ST

Segment Driver03/Digital Input/Output.

RD4/SEG04 33 35 25 I/O/L ST

Segment Driver04/Digital Input/Output.

RD5/SEG29/COM3 56 60 48 I/L ST

Segment Driver29/Common Driver3/Digital Input.

RD6/SEG30/COM2 57 61 49 I/L ST

Segment Driver30/Common Driver2/Digital Input.

RD7/SEG31/COM1 58 62 50 I/L ST

Segment Driver31/Common Driver1/Digital Input.

PORTE is a digital input or LCD Segment Driver port.

RE0/SEG05 34 37 26 I/L ST

Segment Driver05.

RE1/SEG06 35 38 27 I/L ST

Segment Driver06.

RE2/SEG07 36 39 28 I/L ST

Segment Driver07.

RE3/SEG08 37 40 29 I/L ST

Segment Driver08.

RE4/SEG09 38 41 30 I/L ST

Segment Driver09.

RE5/SEG10 39 42 31 I/L ST

Segment Driver10.

RE6/SEG11 40 43 32 I/L ST

Segment Driver11.

RE7/SEG27 - 36 - I/L ST

Segment Driver27 (Not available on 64-pin devices).

PORTF is a digital input or LCD Segment Driver port.

RF0/SEG12 41 44 33 I/L ST

Segment Driver12.

RF1/SEG13 42 45 34 I/L ST

Segment Driver13.

RF2/SEG14 43 46 35 I/L ST

Segment Driver14.

RF3/SEG15 44 47 36 I/L ST

Segment Driver15.

RF4/SEG16 45 48 37 I/L ST

Segment Driver16.

RF5/SEG17 46 49 38 I/L ST

Segment Driver17.

RF6/SEG18 47 50 39 I/L ST

Segment Driver18.

RF7/SEG19 48 51 40 I/L ST

Segment Driver19.

PORTG is a digital input or LCD Segment Driver port.

RG0/SEG20 49 53 41 I/L ST

Segment Driver20.

RG1/SEG21 50 54 42 I/L ST

Segment Driver21.

RG2/SEG22 51 55 43 I/L ST

Segment Driver22.

RG3/SEG23 52 56 44 I/L ST

Segment Driver23.

RG4/SEG24 53 57 45 I/L ST

Segment Driver24.

RG5/SEG25 54 58 46 I/L ST

Segment Driver25.

RG6/SEG26 55 59 47 I/L ST

Segment Driver26.

RG7/SEG28 — 52 — I/L ST

Segment Driver28 (Not available on 64-pin devices).

VLCDADJ 28 30 20 P LCD Voltage Generation. A

VDD — 21 — P Analog Power (PIC16C924 only).

VDD — 21 — P Power (PIC16C923 only). VLCD1 27 29 19 P LCD Voltage. VLCD2 18 19 10 P — LCD Voltage.

TABLE 3-1: PIC16C9XX PINOUT DESCRIPTION (Cont.’d)

Pin Name

DIP

Pin#

PLCC

Pin#

TQFP

Pin#

Type

Buffer

Type

Description

Legend: I = input O = output P = power L = LCD Driver

— = Not used TTL = TTL input ST = Schmitt Trigger input

PIC16C9XX

DS30444E - page 14  1997 Microchip Technology Inc.

VLCD3 19 20 11 P — LCD Voltage. VDD 20, 60 22, 64 12, 52 P — Digital power. VSS 6, 21 7, 23 13, 62 P — Ground reference. NC — 1 — — — These pins are not internally connected. These pins should

be left unconnected.

TABLE 3-1: PIC16C9XX PINOUT DESCRIPTION (Cont.’d)

Pin Name

DIP

Pin#

PLCC

Pin#

TQFP

Pin#

Type

Buffer

Type

Description

Legend: I = input O = output P = power L = LCD Driver

— = Not used TTL = TTL input ST = Schmitt Trigger input

 1997 Microchip Technology Inc. DS30444E - page 15

PIC16C9XX

3.1 Clocking Scheme/Instruction Cycle

The clock input (from OSC1) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3 and Q4. Internally, the program counter (PC) is incremented every Q1, the instruction is fetched from the program memory and latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution ﬂow is shown in Figure 3-3.

3.2 Instruction Flow/Pipelining

An “Instruction Cycle” consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g. GOTO) then two cycles are required to complete the instruction (Example 3-1).

A fetch cycle begins with the program counter (PC) incrementing in Q1.

In the execution cycle, the f etched instruction is latched into the “Instruction Register" in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write).

FIGURE 3-3: CLOCK/INSTRUCTION CYCLE

EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW

Q2 Q3 Q4

OSC1

Q1 Q2 Q3

Q4 PC

OSC2/CLKOUT

(RC mode)

PC PC+1 PC+2

Fetch INST (PC)

Execute INST (PC-1) Fetch INST (PC+1)

Execute INST (PC) Fetch INST (PC+2)

Execute INST (PC+1)

Internal phase clock

All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “ﬂushed” from the pipeline while the new instruction is being fetched and then executed.

Tcy0 Tcy1 Tcy2 Tcy3 Tcy4 Tcy5

1. MOVLW 55h

Fetch 1 Execute 1

2. MOVWF PORTB

Fetch 2 Execute 2

3. CALL SUB_1

Fetch 3 Execute 3

4. BSF PORTA, BIT3 (Forced NOP)

Fetch 4 Flush

5. Instruction @ address SUB_1

Fetch SUB_1 Execute SUB_1

PIC16C9XX

DS30444E - page 16  1997 Microchip Technology Inc.

NOTES:

 1997 Microchip Technology Inc. DS30444E - page 17

PIC16C9XX

4.0 MEMORY ORGANIZATION

4.1 Program Memory Organization

The PIC16C9XX family has a 13-bit program counter capable of addressing an 8K x 14 program memory space.

Only the ﬁrst 4K x 14 (0000h-0FFFh) is physically implemented. Accessing a location above the physically implemented addresses will cause a wraparound. The reset vector is at 0000h and the interrupt vector is at 0004h.

FIGURE 4-1: PROGRAM MEMORY MAP

AND STACK

PC<12:0>

0000h

0004h 0005h

07FFh 0800h

0FFFh

1000h

1FFFh

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

On-chip Program

Memory (Page 1)

Memory (Page 0)

CALL, RETURN RETFIE, RETLW

User Memory

Space

4.2 Data Memory Organization

The data memory is partitioned into four Banks which contain the General Purpose Registers and the Special Function Registers. Bits RP1 and RP0 are the bank select bits.

RP1:RP0 (STATUS<6:5>) 11 = Bank 3 (180h-1FFh) 10 = Bank 2 (100h-17Fh) 01 = Bank 1 (80h-FFh) 00 = Bank 0 (00h-7Fh) The lower locations of each Bank are reserved for the

Special Function Registers. Above the Special Function Registers are General Purpose Registers implemented as static RAM. All four banks contain special function registers. Some “high use” special function registers are mirrored in other banks for code reduction and quicker access.

4.2.1 GENERAL PURPOSE REGISTER FILE The register ﬁle can be accessed either directly , or indi-

rectly through the File Select Register FSR (Section 4.5).

The following General Purpose Registers are not physically implemented:

• F0h-FFh of Bank 1

• 170h-17Fh of Bank 2

• 1F0h-1FFh of Bank 3 These locations are used for common access across

banks.

PIC16C9XX

DS30444E - page 18  1997 Microchip Technology Inc.

FIGURE 4-2: REGISTER FILE MAP

TRISF

TRISG

TRISB

PORTF

PORTG

PORTB

Indirect addr.

(1)

TMR0

PCL

STATUS

FSR PORTA PORTB

PORTC

PCLATH

INTCON

PIR1

TMR1L TMR1H T1CON

TMR2

T2CON

SSPBUF

SSPCON

CCPR1L CCPR1H

CCP1CON

ADRES

(2)

ADCON0

(2)

OPTION

PCL

STATUS

FSR TRISA TRISB TRISC

PCLATH

INTCON

PIE1

PCON

PR2

SSPADD

SSPSTAT

ADCON1

(2)

00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh

80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh

20h

A0h

General Purpose Register

7Fh

FFh

Bank 0

Bank 1

EFh F0h

Unimplemented data memory locations, read as '0'.

Note 1: Not a physical register.

2: These registers are not implemented on the PIC16C923.

File

Address

Indirect addr.

(1)

Mapped in

70h-7Fh

Indirect addr.

(1)

PCL

STATUS

FSR

PCLATH INTCON

PCL

STATUS

FSR

PCLATH INTCON

LCDPS

LCDD02 LCDD03 LCDD04

LCDD15

100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh

180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh

120h

1A0h

17F

1FFh

Bank 2

Bank 3

1EFh 1F0h

Indirect addr.

(1)

16F 170

LCDD05 LCDD06 LCDD07 LCDD08 LCDD09 LCDD10 LCDD11 LCDD12 LCDD13 LCDD14

LCDCON

LCDD00 LCDD01

LCDSE

PORTD

PORTE

TRISD

TRISE

TMR0

OPTION

File

Address

File

Address

File

Address

Bank 0

Mapped in

70h-7Fh

Bank 0

Mapped in

70h-7Fh

Bank 0

 1997 Microchip Technology Inc. DS30444E - page 19

PIC16C9XX

4.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by

the CPU and Peripheral Modules for controlling the desired operation of the device. These registers are implemented as static RAM.

The special function registers can be classiﬁed into two sets (core and peripheral). Those registers associated with the “core” functions are described in this section, and those related to the operation of the peripheral features are described in the section of that peripheral feature.

T ABLE 4-1: SPECIAL FUNCTION REGISTER SUMMARY

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

Power-on

Reset

Value on all

other resets

Bank 0

00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu 02h PCL Program Counter's (PC) Least Signiﬁcant Byte 0000 0000 0000 0000 03h STATUS IRP RP1 RP0 T

O PD Z DC C 0001 1xxx 000q quuu 04h FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu 05h PORTA

— — PORTA Data Latch when written: PORTA pins when read

(4) (4) 06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu 07h PORTC

— — PORTC Data Latch when written: PORTC pins when read --xx xxxx --uu uuuu 08h PORTD PORTD Data Latch when written: PORTD pins when read 0000 0000 0000 0000 09h PORTE PORTE pins when read 0000 0000 0000 0000 0Ah PCLATH

— — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 0Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 LCDIF ADIF

(2)

— — SSPIF CCP1IF TMR2IF TMR1IF 00-- 0000 00-- 0000 0Dh — Unimplemented — — 0Eh TMR1L Holding register for the Least Signiﬁcant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding register for the Most Signiﬁcant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 10h T1CON

— — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu 11h TMR2 Timer2 module’s register 0000 0000 0000 0000 12h T2CON

— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 15h CCPR1L Capture/Compare/PWM Register (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM Register (MSB) xxxx xxxx uuuu uuuu 17h CCP1CON

— — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 18h — Unimplemented — — 19h — Unimplemented — — 1Ah — Unimplemented — — 1Bh — Unimplemented — — 1Ch — Unimplemented — — 1Dh — Unimplemented — — 1Eh

(1)

ADRES A/D Result Register xxxx xxxx uuuu uuuu

1Fh

(1)

ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE

(5)

ADON 0000 0000 0000 0000

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0',

shaded locations are unimplemented, read as ‘0’.

Note 1: Registers ADRES, ADCON0, and ADCON1 are not implemented in the PIC16C923, read as '0'.

2: These bits are reserved on the PIC16C923, always maintain these bits clear. 3: These pixels do not display, but can be used as general purpose RAM. 4: PIC16C923 reset values for PORTA: --xx xxxx for a POR, and --uu uuuu for all other resets,

PIC16C924 reset values for PORTA: --0x 0000 when read.

5: Bit1 of ADCON0 is reserved on the PIC16C924, always maintain this bit clear.

PIC16C9XX

DS30444E - page 20  1997 Microchip Technology Inc.

Bank 1

80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 81h OPTION RBPU

INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 82h PCL Program Counter's (PC) Least Signiﬁcant Byte 0000 0000 0000 0000 83h STATUS IRP RP1 RP0 T

O PD Z DC C 0001 1xxx 000q quuu 84h FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu 85h TRISA

— — PORTA Data Direction Register --11 1111 --11 1111 86h TRISB PORTB Data Direction Register 1111 1111 1111 1111 87h TRISC

— — PORTC Data Direction Register --11 1111 --11 1111 88h TRISD PORTD Data Direction Register 1111 1111 1111 1111 89h TRISE PORTE Data Direction Register 1111 1111 1111 1111 8Ah PCLATH

— — — Write Buffer for the upper 5 bits of the PC ---0 0000 ---0 0000 8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 8Ch PIE1 LCDIE ADIE

(2)

— — SSPIE CCP1IE TMR2IE TMR1IE 00-- 0000 00-- 0000 8Dh — Unimplemented — — 8Eh PCON

— — — — — — POR — ---- --0- ---- --u- 8Fh — Unimplemented — — 90h — Unimplemented — — 91h — Unimplemented — — 92h PR2 Timer2 Period Register 1111 1111 1111 1111 93h SSPADD Synchronous Serial Port (I

C mode) Address Register 0000 0000 0000 0000

94h SSPSTAT SMP CKE D/A

P S R/W UA BF 0000 0000 0000 0000 95h — Unimplemented — — 96h — Unimplemented — — 97h — Unimplemented — — 98h — Unimplemented — — 99h — Unimplemented — — 9Ah — Unimplemented — — 9Bh — Unimplemented — — 9Ch — Unimplemented — — 9Dh — Unimplemented — — 9Eh — Unimplemented — — 9Fh

(1)

ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000

TABLE 4-1: SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on Power-on

Reset

Value on all other resets

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0',

shaded locations are unimplemented, read as ‘0’.

Note 1: Registers ADRES, ADCON0, and ADCON1 are not implemented in the PIC16C923, read as '0'.

PIC16C924 reset values for PORTA: --0x 0000 when read.

5: Bit1 of ADCON0 is reserved on the PIC16C924, always maintain this bit clear.

 1997 Microchip Technology Inc. DS30444E - page 21

PIC16C9XX

Bank 2

100h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 101h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu 102h PCL Program Counter's (PC) Least Signiﬁcant Byte 0000 0000 0000 0000 103h STATUS IRP RP1 RP0 T

O PD Z DC C 0001 1xxx 000q quuu 104h FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu 105h — Unimplemented — — 106h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu 107h PORTF PORTF pins when read 0000 0000 0000 0000 108h PORTG PORTG pins when read 0000 0000 0000 0000 109h — Unimplemented — — 10Ah PCLATH

— — — Write Buffer for the upper 5 bits of the PC ---0 0000 ---0 0000 10Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 10Ch — Unimplemented — — 10Dh LCDSE SE29 SE27 SE20 SE16 SE12 SE9 SE5 SE0 1111 1111 1111 1111 10Eh LCDPS

— — — — LP3 LP2 LP1 LP0 ---- 0000 ---- 0000 10Fh LCDCON LCDEN SLPEN

— VGEN CS1 CS0 LMUX1 LMUX0 00-0 0000 00-0 0000

110h LCDD00

SEG07

COM0

SEG06

COM0

SEG05

COM0

SEG04

COM0

SEG03

COM0

SEG02

COM0

SEG01

COM0

SEG00

COM0

xxxx xxxx uuuu uuuu

111h LCDD01

SEG15

COM0

SEG14

COM0

SEG13

COM0

SEG12

COM0

SEG11

COM0

SEG10

COM0

SEG09

COM0

SEG08

COM0

xxxx xxxx uuuu uuuu

112h LCDD02

SEG23

COM0

SEG22

COM0

SEG21

COM0

SEG20

COM0

SEG19

COM0

SEG18

COM0

SEG17

COM0

SEG16

COM0

xxxx xxxx uuuu uuuu

113h LCDD03

SEG31

COM0

SEG30

COM0

SEG29

COM0

SEG28

COM0

SEG27

COM0

SEG26

COM0

SEG25

COM0

SEG24

COM0

xxxx xxxx uuuu uuuu

114h LCDD04

SEG07

COM1

SEG06

COM1

SEG05

COM1

SEG04

COM1

SEG03

COM1

SEG02

COM1

SEG01

COM1

SEG00

COM1

xxxx xxxx uuuu uuuu

115h LCDD05

SEG15

COM1

SEG14

COM1

SEG13

COM1

SEG12

COM1

SEG11

COM1

SEG10

COM1

SEG09

COM1

SEG08

COM1

xxxx xxxx uuuu uuuu

116h LCDD06

SEG23

COM1

SEG22

COM1

SEG21

COM1

SEG20

COM1

SEG19

COM1

SEG18

COM1

SEG17

COM1

SEG16

COM1

xxxx xxxx uuuu uuuu

117h LCDD07

SEG31

COM1

(3)

SEG30

COM1

SEG29

COM1

SEG28

COM1

SEG27

COM1

SEG26

COM1

SEG25

COM1

SEG24

COM1

xxxx xxxx uuuu uuuu

118h LCDD08

SEG07

COM2

SEG06

COM2

SEG05

COM2

SEG04

COM2

SEG03

COM2

SEG02

COM2

SEG01

COM2

SEG00

COM2

xxxx xxxx uuuu uuuu

119h LCDD09

SEG15

COM2

SEG14

COM2

SEG13

COM2

SEG12

COM2

SEG11

COM2

SEG10

COM2

SEG09

COM2

SEG08

COM2

xxxx xxxx uuuu uuuu

11Ah LCDD10

SEG23

COM2

SEG22

COM2

SEG21

COM2

SEG20

COM2

SEG19

COM2

SEG18

COM2

SEG17

COM2

SEG16

COM2

xxxx xxxx uuuu uuuu

11Bh LCDD11

SEG31

COM2

(3)

SEG30

COM2

(3)

SEG29

COM2

SEG28

COM2

SEG27

COM2

SEG26

COM2

SEG25

COM2

SEG24

COM2

xxxx xxxx uuuu uuuu

11Ch LCDD12

SEG07

COM3

SEG06

COM3

SEG05

COM3

SEG04

COM3

SEG03

COM3

SEG02

COM3

SEG01

COM3

SEG00

COM3

xxxx xxxx uuuu uuuu

11Dh LCDD13

SEG15

COM3

SEG14

COM3

SEG13

COM3

SEG12

COM3

SEG11

COM3

SEG10

COM3

SEG09

COM3

SEG08

COM3

xxxx xxxx uuuu uuuu

11Eh LCDD14

SEG23

COM3

SEG22

COM3

SEG21

COM3

SEG20

COM3

SEG19

COM3

SEG18

COM3

SEG17

COM3

SEG16

COM3

xxxx xxxx uuuu uuuu

11Fh LCDD15

SEG31

COM3

(3)

SEG30

COM3

(3)

SEG29

COM3

(3)

SEG28

COM3

SEG27

COM3

SEG26

COM3

SEG25

COM3

SEG24

COM3

xxxx xxxx uuuu uuuu

TABLE 4-1: SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

Power-on

Reset

Value on all

other resets

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0',

shaded locations are unimplemented, read as ‘0’.

Note 1: Registers ADRES, ADCON0, and ADCON1 are not implemented in the PIC16C923, read as '0'.

PIC16C924 reset values for PORTA: --0x 0000 when read.

5: Bit1 of ADCON0 is reserved on the PIC16C924, always maintain this bit clear.

PIC16C9XX

DS30444E - page 22  1997 Microchip Technology Inc.

Bank 3

180h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 181h OPTION RBPU

INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 182h PCL Program Counter's (PC) Least Signiﬁcant Byte 0000 0000 0000 0000 183h STATUS IRP RP1 RP0 T

O PD Z DC C 0001 1xxx 000q quuu 184h FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu 185h — Unimplemented — — 186h TRISB PORTB Data Direction Register 1111 1111 1111 1111 187h TRISF PORTF Data Direction Register 1111 1111 1111 1111 188h TRISG PORTG Data Direction Register 1111 1111 1111 1111 189h — Unimplemented — — 18Ah PCLATH

— — — Write Buffer for the upper 5 bits of the PC ---0 0000 ---0 0000 18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 18Ch — Unimplemented — — 18Dh — Unimplemented — — 18Eh — Unimplemented — — 18Fh — Unimplemented — — 190h — Unimplemented — — 191h — Unimplemented — — 192h — Unimplemented — — 193h — Unimplemented — — 194h — Unimplemented — — 195h — Unimplemented — — 196h — Unimplemented — — 197h — Unimplemented — — 198h — Unimplemented — — 199h — Unimplemented — — 19Ah — Unimplemented — — 19Bh — Unimplemented — — 19Ch — Unimplemented — — 19Dh — Unimplemented — — 19Eh — Unimplemented — — 19Fh — Unimplemented — —

TABLE 4-1: SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on Power-on

Reset

Value on all other resets

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0',

shaded locations are unimplemented, read as ‘0’.

Note 1: Registers ADRES, ADCON0, and ADCON1 are not implemented in the PIC16C923, read as '0'.

PIC16C924 reset values for PORTA: --0x 0000 when read.

5: Bit1 of ADCON0 is reserved on the PIC16C924, always maintain this bit clear.

 1997 Microchip Technology Inc. DS30444E - page 23

PIC16C9XX

4.2.2.1 STATUS REGISTER The ST ATUS register, shown in Figure 4-3, contains the

arithmetic status of the ALU, the RESET status and the bank select bits for data memory.

The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the T

O and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended.

For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged).

It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register because these instructions do not affect the Z, C or DC bits from the STA TUS register. For other instructions, not affecting any status bits, see the “Instruction Set Summary.”

Note 1: The C and DC bits operate as a borrow

and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.

FIGURE 4-3: STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h)

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO PD Z DC C R = Readable bit

W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: IRP: Register Bank Select bit (used for indirect addressing)

1 = Bank 2, 3 (100h - 1FFh) 0 = Bank 0, 1 (00h - FFh)

bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)

11 = Bank 3 (180h - 1FFh) 10 = Bank 2 (100h - 17Fh) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh)

bit 4: T

O: Time-out bit

1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred

bit 3: PD

: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction

bit 2: Z: Zero bit

1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero

bit 1: DC: Digit carry/borro

w bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result

bit 0: C: Carry/borro

w bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity is reversed) 1 = A carry-out from the most signiﬁcant bit of the result occurred 0 = No carry-out from the most signiﬁcant bit of the result occurred Note: A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register.

PIC16C9XX

DS30444E - page 24  1997 Microchip Technology Inc.

4.2.2.2 OPTION REGISTER The OPTION register is a readable and writable regis-

ter which contains various control bits to conﬁgure the TMR0/WDT prescaler, the external RB0/INT pin interrupt, TMR0, and the weak pull-ups on PORTB.

Note: To achieve a 1:1 prescaler assignment for

the TMR0 register, assign the prescaler to the Watchdog Timer.

FIGURE 4-4: OPTION REGISTER (ADDRESS 81h, 181h)

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 R = Readable bit

W = Writable bit U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: RBPU: PORTB Pull-up Enable bit

1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values

bit 6: INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin

bit 5: T0CS: TMR0 Clock Source Select bit

1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT)

bit 4: T0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin

bit 3: PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module

bit 2-0: PS2:PS0: Prescaler Rate Select bits

000 001 010 011 100 101 110 111

1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256

1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128

Bit Value TMR0 Rate WDT Rate

 1997 Microchip Technology Inc. DS30444E - page 25

PIC16C9XX

4.2.2.3 INTCON REGISTER The INTCON Register is a readable and writable regis-

ter which contains various enable and ﬂag bits for the TMR0 register overﬂow, RB Port change and external RB0/INT pin interrupts.

Note: Interrupt ﬂag bits get set when an interrupt

condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>).

FIGURE 4-5: INTCON REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x

GIE PEIE T0IE INTE RBIE T0IF INTF RBIF R = Readable bit

W = Writable bit U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: GIE: Global Interrupt Enable bit

1 = Enables all un-masked interrupts 0 = Disables all interrupts

bit 6: PEIE: Peripheral Interrupt Enable bit

1 = Enables all un-masked peripheral interrupts 0 = Disables all peripheral interrupts

bit 5: T0IE: TMR0 Overﬂow Interrupt Enable bit

1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt

bit 4: INTE: RB0/INT External Interrupt Enable bit

1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt

bit 3: RBIE: RB Port Change Interrupt Enable bit

1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt

bit 2: T0IF: TMR0 Overﬂow Interrupt Flag bit

1 = TMR0 register has overﬂowed (must be cleared in software) 0 = TMR0 register did not overﬂow

bit 1: INTF: RB0/INT External Interrupt Flag bit

1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur

bit 0: RBIF: RB Port Change Interrupt Flag bit

1 = At least one of the RB7:RB4 pins changed state (see Section 5.2 to clear interrupt) 0 = None of the RB7:RB4 pins have changed state

Interrupt ﬂag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt ﬂag bits are clear prior to enabling an interrupt.

PIC16C9XX

DS30444E - page 26  1997 Microchip Technology Inc.

4.2.2.4 PIE1 REGISTER This register contains the individual enable bits for the

peripheral interrupts.

Note: Bit PEIE (INTCON<6>) must be set to

enable any peripheral interrupt.

FIGURE 4-6: PIE1 REGISTER (ADDRESS 8Ch)

R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

LCDIE ADIE

(1)

— — SSPIE CCP1IE TMR2IE TMR1IE R = Readable bit

W = Writable bit U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: LCDIE: LCD Interrupt Enable bit

1 = Enables the LCD interrupt 0 = Disables the LCD interrupt

bit 6: ADIE: A/D Converter Interrupt Enable bit

(1)

1 = Enables the A/D interrupt

0 = Disables the A/D interrupt bit 5-4: Unimplemented: Read as '0' bit 3: SSPIE: Synchronous Serial Port Interrupt Enable bit

1 = Enables the SSP interrupt

0 = Disables the SSP interrupt bit 2: CCP1IE: CCP1 Interrupt Enable bit

1 = Enables the CCP1 interrupt

0 = Disables the CCP1 interrupt bit 1: TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1 = Enables the TMR2 to PR2 match interrupt

0 = Disables the TMR2 to PR2 match interrupt bit 0: TMR1IE: TMR1 Overﬂow Interrupt Enable bit

1 = Enables the TMR1 overﬂow interrupt

0 = Disables the TMR1 overﬂow interrupt Note 1: Bit ADIE is reserved on the PIC16C923, always maintain this bit clear.

 1997 Microchip Technology Inc. DS30444E - page 27

PIC16C9XX

4.2.2.5 PIR1 REGISTER This register contains the individual ﬂag bits for the

peripheral interrupts.

Note: Interrupt ﬂag bits get set when an interrupt

condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt ﬂag bits are clear prior to enabling an interrupt.

FIGURE 4-7: PIR1 REGISTER (ADDRESS 0Ch)

R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 LCDIF ADIF

(1)

— — SSPIF CCP1IF TMR2IF TMR1IF R = Readable bit

W = Writable bit U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: LCDIF: LCD Interrupt Flag bit

1 = LCD interrupt occurred (must be cleared in software) 0 = LCD interrupt did not occur

bit 6: ADIF: A/D Converter Interrupt Flag bit

(1)

1 = An A/D conversion completed (must be cleared in software)

0 = The A/D conversion is not complete bit 5-4: Unimplemented: Read as '0' bit 3: SSPIF: Synchronous Serial Port Interrupt Flag bit

1 = The transmission/reception is complete (must be cleared in software)

0 = Waiting to transmit/receive bit 2: CCP1IF: CCP1 Interrupt Flag bit

Capture Mode

1 = A TMR1 register capture occurred (must be cleared in software)

0 = No TMR1 register capture occurred

Compare Mode

1 = A TMR1 register compare match occurred (must be cleared in software)

0 = No TMR1 register compare match occurred

PWM Mode

Unused in this mode bit 1: TMR2IF: TMR2 to PR2 Match Interrupt Flag bit

1 = TMR2 to PR2 match occurred (must be cleared in software)

0 = No TMR2 to PR2 match occurred bit 0: TMR1IF: TMR1 Overﬂow Interrupt Flag bit

1 = TMR1 register overﬂowed (must be cleared in software)

0 = TMR1 register did not overﬂow Note 1: Bit ADIF is reserved on the PIC16C923, always maintain this bit clear.

PIC16C9XX

DS30444E - page 28  1997 Microchip Technology Inc.

4.2.2.6 PCON REGISTER The Power Control (PCON) register contains a ﬂag bit

to allow differentiation between a Power-on Reset (POR) to an external MCLR

Reset or WDT Reset.

For various reset conditions see Table 14-4 and Table 14-5.

FIGURE 4-8: PCON REGISTER (ADDRESS 8Eh)

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0

— — — — — — POR — R = Readable bit

W = Writable bit U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7-2: Unimplemented: Read as '0' bit 1: POR

: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0: Unimplemented: Read as '0'

 1997 Microchip Technology Inc. DS30444E - page 29

PIC16C9XX

4.3 PCL and PCLATH

The program counter (PC) is 13-bits wide. The lo w byte comes from the PCL register, which is a readable and writable register. The upper bits (PC<12:8>) are not readable, but are indirectly writable through the PCLATH register. On any reset, the upper bits of the PC will be cleared. Figure 4-9 sho ws the two situations for the loading of the PC. The upper example in the ﬁgure shows how the PC is loaded on a write to PCL (PCLATH<4:0> → PCH). The lower example in the ﬁg- ure shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> → PCH).

FIGURE 4-9: LOADING OF PC IN

DIFFERENT SITUATIONS

4.3.1 COMPUTED GOTO A computed GOT O is accomplished by adding an offset

to the program counter (ADDWF PCL). When doing a table read using a computed GOTO method, care should be exercised if the tab le location crosses a PCL memory boundary (each 256 byte block). Refer to the application note

“Implementing a Table Read”

(AN556).

4.3.2 STACK The PIC16CXXX family has an 8 level deep x 13-bit

wide hardware stack. The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation.

The stack operates as a circular buff er . This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the ﬁrst push. The tenth push overwrites the second push (and so on).

12 8 7 0

PCLATH<4:0>

PCLATH

Instr

uction with

ALU result

GOTO, CALL

Opcode <10:0>

12 11 10 0

PCLATH<4:3>

PCH PCL

8 7

PCLATH

PCH PCL

PCL as Destination

4.4 Program Memory Paging

PIC16C9XX devices are capable of addressing a continuous 8K word block of program memory. The CALL and GOTO instructions provide only 11 bits of address to allow branching within any 2K program memory page. When doing a CALL or GOTO instruction the upper 2 bits of the address are provided by PCLATH<4:3>. When doing a CALL or GOTO instruction, the user must ensure that the page select bits are programmed so that the desired program memory page is addressed. If a return from a CALL instruction (or interrupt) is executed, the entire 13-bit PC is pushed onto the stack. Therefore, manipulation of the PCLATH<4:3> bits are not required for the return instructions (which POPs the address from the stack).

Note 1: There are no status bits to indicate stack

overﬂow or stack underﬂow conditions.

Note 2: There are no instructions/mnemonics

called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW, and RETFIE instructions, or the vectoring to an interrupt address.

Note: The PIC16C9XX ignores paging bit

PCLATH<4>, which is used to access program memory pages 2 and 3. The use of PCLATH<4> as a general purpose read/write bit is not recommended since this may affect upward compatibility with future products.

PIC16C9XX

DS30444E - page 30  1997 Microchip Technology Inc.

Example 4-1 shows the calling of a subroutine in page 1 of the program memory . This example assumes that PCLA TH is sa ved and restored by the interrupt service routine (if interrupts are used).

EXAMPLE 4-1: CALL OF A SUBROUTINE IN

PAGE 1 FROM PAGE 0

ORG 0x500 BSF PCLATH,3 ;Select page 1 (800h-FFFh) CALL SUB1_P1 ;Call subroutine in : ;page 1 (800h-FFFh) : : ORG 0x900 SUB1_P1: ;called subroutine : ;page 1 (800h-FFFh) : RETURN ;return to Call subroutine ;in page 0 (000h-7FFh)

4.5 Indirect Addressing, INDF and FSR Registers

The INDF register is not a physical register . Addressing the INDF register will cause indirect addressing.

Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses the register pointed to by the File Select Register (FSR). Reading the INDF register itself indirectly (FSR = '0') will produce 00h. Writing to the INDF register indirectly results in a no-operation (although status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 4-10.

A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 4-2.

EXAMPLE 4-2: INDIRECT ADDRESSING

movlw 0x20 ;initialize pointer movwf FSR ;to RAM NEXT clrf INDF ;clear INDF register incf FSR,F ;inc pointer btfss FSR,4 ;all done? goto NEXT ;no clear next CONTINUE : ;yes continue

FIGURE 4-10: DIRECT/INDIRECT ADDRESSING

For memory map detail see Figure 4-2.

Data Memory

Indirect AddressingDirect Addressing

bank select location select

RP1:RP0 6

from opcode

IRP FSR register

bank select

location select

00 01 10 11

00h

7Fh

00h

7Fh

Bank 0 Bank 1 Bank 2 Bank 3

 1997 Microchip Technology Inc. DS30444E - page 31

PIC16C9XX

5.0 PORTS

Some pins for these ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin.

5.1 PORTA and TRISA Register

The RA4/T0CKI pin is a Schmitt Tr igger input and an open drain output. All other RA port pins hav e TTL input levels and full CMOS output drivers. All RA pins have data direction bits (TRISA register) which can conﬁgure these pins as output or input.

Setting a bit in the TRISA register puts the corresponding output driver in a hi-impedance mode. Clearing a bit in the TRISA register puts the contents of the output latch on the selected pin.

Reading the PORTA register reads the status of the pins whereas writing to it will write to the port latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modiﬁed, and then written to the port data latch.

Pin RA4 is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin.

For the PIC16C924 only, other PORTA pins are multiplexed with analog inputs and the analog V

REF input.

The operation of each pin is selected by clearing/setting the control bits in the ADCON1 register (A/D Control Register1).

The TRISA register controls the direction of the RA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs.

EXAMPLE 5-1: INITIALIZING PORTA

BCF STATUS, RP0 ; Select Bank0 BCF STATUS, RP1 CLRF PORTA ; Initialize PORTA BSF STATUS, RP0 ; MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISA ; Set RA<3:0> as inputs ; RA<5:4> as outputs ; RA<7:6> are always ; read as '0'.

Note: On a Power-on Reset, these pins are con-

ﬁgured as analog inputs and read as '0'.

FIGURE 5-1: BLOCK DIAGRAM OF PINS

RA3:RA0 AND RA5

FIGURE 5-2: BLOCK DIAGRAM OF

RA4/T0CKI PIN

Data bus

Q D

WR Port

WR TRIS

Data Latch

TRIS Latch

RD TRIS

RD PORT

VDD

I/O pin

(1)

Note 1: I/O pins have protection diodes to VDD and VSS.

Analog input mode

TTL input buffer

To A/D Converter (PIC16C924 only)

Data bus

WR PORT

WR TRIS

RD PORT

Data Latch

TRIS Latch

RD TRIS

Schmitt Trigger input buffer

I/O pin

(1)

TMR0 clock input

Note 1: I/O pin has protection diodes to V

SS only.

Q D

PIC16C9XX

DS30444E - page 32  1997 Microchip Technology Inc.

TABLE 5-1: PORTA FUNCTIONS

TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Name Bit# Buffer Function

RA0/AN0

(1)

bit0 TTL Input/output or analog input

RA1/AN1

(1)

bit1 TTL Input/output or analog input

RA2/AN2

(1)

bit2 TTL Input/output or analog input

RA3/AN3/V

REF

(1)

bit3 TTL Input/output or analog input or VREF

RA4/T0CKI bit4 ST Input/output or external clock input for Timer0

Output is open drain type

RA5/AN4/SS

(1)

bit5 TTL Input/output or analog input or slave select input for synchronous serial port

Legend: TTL = TTL input, ST = Schmitt Trigger input Note 1: The AN and V

REF functions are for the A/D module and are only implemented on the PIC16C924.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

Power-on

Reset

Value on

all other

resets

05h PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 (2) (2) 85h TRISA — — PORTA Data Direction Control Register --11 1111 --11 1111 9Fh

(1)

ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000

Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA. Note 1: The ADCON1 register is implemented on the PIC16C924 only.

2: PIC16C923 reset values for PORTA: --xx xxxx for a POR, and --uu uuuu for all other resets,

PIC16C924 reset values for PORTA: --0x 0000 when read.

 1997 Microchip Technology Inc. DS30444E - page 33

PIC16C9XX

5.2 PORTB and TRISB Register

PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. Setting a bit in the TRISB register puts the corresponding output driver in a hi-impedance input mode. Clearing a bit in the TRISB register puts the contents of the output latch on the selected pin(s).

EXAMPLE 5-2: INITIALIZING PORTB

BCF STATUS, RP0 ; Select Bank0 BCF STATUS, RP1 CLRF PORTB ; Initialize PORTB BSF STATUS, RP0 ; MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISB ; Set RB<3:0> as inputs ; RB<5:4> as outputs ; RB<7:6> as inputs

Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU

(OPTION<7>). The weak pull-up is automatically turned off when the port pin is conﬁgured as an output. The pull-ups are also disabled on a Power-on Reset.

FIGURE 5-3: BLOCK DIAGRAM OF

RB3:RB0 PINS

Four of PORTB’s pins, RB7:RB4, have an interrupt on change feature. Only pins conﬁgured as inputs can cause this interrupt to occur (i.e. an y RB7:RB4 pin conﬁgured as an output is excluded from the interrupt on change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of

Data Latch

RBPU

(2)

Q D

Data bus

WR Port

WR TRIS

RD TRIS

RD Port

weak pull-up

RD Port

RB0/INT

I/O pin

(1)

TTL Input Buffer

Note 1: I/O pins have diode protection to V

DD and VSS.

2: To enable weak pull-ups, set the appropriate TRIS bit

and clear the RBPU

bit (OPTION<7>).

Schmitt Trigger Buffer

TRIS Latch

PORTB. The “mismatch” outputs of RB7:RB4 are OR’ed together to generate the RB Port Change Interrupt with ﬂag bit RBIF (INTCON<0>).

This interrupt can wake the device from SLEEP. The user, in the interrupt service routine, can clear the interrupt in the following manner:

a) Any read or write of PORTB. This will end the

mismatch condition.

b) Clear ﬂag bit RBIF. A mismatch condition will continue to set ﬂag bit RBIF.

Reading PORTB will end the mismatch condition, and allow ﬂag bit RBIF to be cleared.

This interrupt on mismatch feature, together with software conﬁgurable pull-ups on these four pins allow easy interface to a keypad and make it possible for wake-up on key-depression. Refer to the

Embedded Control Handbook, "Implementing Wake-Up on Key Stroke"

(AN552).

The interrupt on change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt on change feature. Polling of PORTB is not recommended while using the interrupt on change feature.

FIGURE 5-4: BLOCK DIAGRAM OF

RB7:RB4 PINS

Data Latch

From other

RBPU

(2)

I/O

Q D

Data bus

WR Port

WR TRIS

Set RBIF

TRIS Latch

RD TRIS

RD Port

RB7:RB4 pins

weak pull-up

RD Port

Latch

TTL Input Buffer

(1)

Note 1: I/O pins have diode protection to VDD and VSS.

2: To enable weak pull-ups, set the appropriate TRIS bit

and clear the RBPU

bit (OPTION<7>).

ST Buffer

RB7:RB6 in serial programming mode

PIC16C9XX

DS30444E - page 34  1997 Microchip Technology Inc.

TABLE 5-3: PORTB FUNCTIONS

TABLE 5-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Name Bit# Buffer Function

RB0/INT bit0 TTL/ST Input/output pin or external interrupt input. Internal software

programmable weak pull-up. This buffer is a Schmitt Trigger input when

conﬁgured as the external interrupt. RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up. RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up. RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up. RB4 bit4 TTL Input/output pin (with interrupt on change). Internal software programmable

weak pull-up. RB5 bit5 TTL Input/output pin (with interrupt on change). Internal software programmable

weak pull-up. RB6 bit6 TTL/ST Input/output pin (with interrupt on change). Internal software programmable

weak pull-up. Serial programming clock. This buffer is a Schmitt Trigger

input when used in serial programming mode. RB7 bit7 TTL/ST Input/output pin (with interrupt on change). Internal software programmable

weak pull-up. Serial progr amming data. This buffer is a Schmitt Trigger input

when used in serial programming mode. Legend: TTL = TTL input, ST = Schmitt Trigger input

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

Power-on

Reset

Value on all other resets

06h, 106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu 86h, 186h TRISB PORTB Data Direction Control Register 1111 1111 1111 1111 81h, 181h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.

 1997 Microchip Technology Inc. DS30444E - page 35

PIC16C9XX

5.3 PORTC and TRISC Register

PORTC is an 6-bit bi-directional port. Each pin is individually conﬁgurable as an input or output through the TRISC register. PORTC is multiplexed with several peripheral functions (Table 5-5). PORTC pins have Schmitt Trigger input buffers.

When enabling peripheral functions, care should be taken in deﬁning TRIS bits for each PORTC pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. Since the TRIS bit override is in effect while the peripheral is enabled, read-modify-write instructions (BSF, BCF, XORWF) with TRISC as destination should be avoided. The user should ref er to the corresponding peripheral section for the correct TRIS bit settings.

EXAMPLE 5-3: INITIALIZING PORTC

BCF STATUS,RP0 ; Select Bank0 BCF STATUS,RP1 CLRF PORTC ; Initialize PORTC BSF STATUS,RP0 ; MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISC ; Set RC<3:0> as inputs ; RC<5:4> as outputs ; RC<7:6> always read 0

FIGURE 5-5: PORTC BLOCK DIAGRAM

(PERIPHERAL OUTPUT OVERRIDE)

Data Latch

RBPU

(2)

Q D

Data bus

WR Port

WR TRIS

RD TRIS

RD Port

weak pull-up

RD Port

RB0/INT

I/O pin

(1)

TTL Input Buffer

Note 1: I/O pins have diode protection to V

DD and VSS.

2: To enable weak pull-ups, set the appropriate TRIS bit(s)

and clear the RBPU bit (OPTION<7>).

Schmitt Trigger Buffer

TRIS Latch

TABLE 5-5: PORTC FUNCTIONS

TABLE 5-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

Name Bit# Buffer Type Function

RC0/T1OSO/T1CKI bit0 ST Input/output port pin or Timer1 oscillator output or Timer1 clock input RC1/T1OSI bit1 ST Input/output port pin or Timer1 oscillator input RC2/CCP1 bit2 ST Input/output port pin or Capture input/Compare output/PWM output RC3/SCK/SCL bit3 ST Input/output port pin or the synchronous serial clock for both SPI and

C modes.

RC4/SDI/SDA bit4 ST Input/output port pin or the SPI Data In (SPI mode) or data I/O (I

mode).

RC5/SDO bit5 ST Input/output port pin or Synchronous Serial Port data out Legend: ST = Schmitt Trigger input

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

Power-on

Reset

Value on all

other resets

07h PORTC — — RC5 RC4 RC3 RC2 RC1 RC0 --xx xxxx --uu uuuu 87h TRISC — — PORTC Data Direction Control Register --11 1111 --11 1111

Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PORTC.

PIC16C9XX

DS30444E - page 36  1997 Microchip Technology Inc.

5.4 PORTD and TRISD Registers

PORTD is an 8-bit port with Schmitt Trigger input buffers. The ﬁrst ﬁve pins are conﬁgurable as general purpose I/O pins or LCD segment drivers. Pins RD5, RD6 and RD7 can be digital inputs or LCD segment or common drivers.

TRISD controls the direction of pins RD0 through RD4 when PORTD is conﬁgured as a digital port.

EXAMPLE 5-4: INITIALIZING PORTD

BCF STATUS,RP0 ;Select Bank2 BSF STATUS,RP1 ; BCF LCDSE,SE29 ;Make RD<7:5> digital BCF LCDSE,SE0 ;Make RD<4:0> digital BSF STATUS,RP0 ;Select Bank1 BCF STATUS,RP1 ; MOVLW 0x07 ;Make RD<4:0> outputs MOVWF TRISD ;Make RD<7:5> inputs

Note: On a Power-on Reset these pins are con-

ﬁgured as LCD segment drivers.

Note: To conﬁgure the pins as a digital port, the

corresponding bits in the LCDSE register must be cleared. Any bit set in the LCDSE register overrides any bit settings in the corresponding TRIS register.

FIGURE 5-6: PORTD<4:0> BLOCK

DIAGRAM

Data Bus WR

Data Latch

TRIS Latch

Schmitt Trigger input buffer

Q D

I/O pin

RD TRIS

LCDSE<n>

LCD

LCD Segment

Segment Data

Output Enable

PORT

TRIS

PORT

 1997 Microchip Technology Inc. DS30444E - page 37

PIC16C9XX

FIGURE 5-7: PORTD<7:5> BLOCK

DIAGRAM

RD PORT

Schmitt Trigger input buffer

Q D

Digital Input/

LCDSE<n>

LCD

LCD Segment

LCD Output pin

LCD

LCD Common

Data Bus

RD TRIS

Segment Data

Output Enable

Common Data

Output Enable

TABLE 5-7: PORTD FUNCTIONS

TABLE 5-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD

Name Bit#

Buffer

Type

Function

RD0/SEG00 bit0 ST Input/output port pin or Segment Driver00 RD1/SEG01 bit1 ST Input/output port pin or Segment Driver01 RD2/SEG02 bit2 ST Input/output port pin or Segment Driver02 RD3/SEG03 bit3 ST Input/output port pin or Segment Driver03 RD4/SEG04 bit4 ST Input/output port pin or Segment Driver04 RD5/SEG29/COM3 bit5 ST Digital input pin or Segment Driver29 or Common Driver3 RD6/SEG30/COM2 bit6 ST Digital input pin or Segment Driver30 or Common Driver2 RD7/SEG31/COM1 bit7 ST Digital input pin or Segment Driver31 or Common Driver1

Legend: ST = Schmitt Trigger input

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

Power-on

Reset

Value on all

other resets

08h PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 0000 0000 0000 0000 88h TRISD PORTD Data Direction Control Register 1111 1111 1111 1111 10Dh LCDSE SE29 SE27 SE20 SE16 SE12 SE9 SE5 SE0 1111 1111 1111 1111

Legend: Shaded cells are not used by PORTD.

PIC16C9XX

DS30444E - page 38  1997 Microchip Technology Inc.

5.5 PORTE and TRISE Register

PORTE is an digital input only port. Each pin is multiplexed with an LCD segment driver. These pins have Schmitt Tr igger input buffers.

EXAMPLE 5-5: INITIALIZING PORTE

BCF STATUS,RP0 ;Select Bank2 BSF STATUS,RP1 ; BCF LCDSE,SE27 ;Make all PORTE BCF LCDSE,SE5 ;and PORTG<7> BCF LCDSE,SE9 ;digital inputs

Note 1: On a Power-on Reset these pins are con-

ﬁgured as LCD segment drivers.

Note 2: To conﬁgure the pins as a digital port, the

corresponding bits in the LCDSE register must be cleared. An y bit set in the LCDSE register overrides any bit settings in the corresponding TRIS register.

FIGURE 5-8: PORTE BLOCK DIAGRAM

RD PORT

Schmitt Trigger input buffer

Q D

Digital Input/

LCDSE<n>

LCD

LCD Segment

LCD Output pin

LCD

LCD Common

Data Bus

RD TRIS

Segment Data

Output Enable

Common Data

Output Enable

TABLE 5-9: PORTE FUNCTIONS

TABLE 5-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE

Name Bit# Buffer Type Function

RE0/SEG05 bit0 ST Digital input or Segment Driver05 RE1/SEG06 bit1 ST Digital input or Segment Driver06 RE2/SEG07 bit2 ST Digital input or Segment Driver07 RE3/SEG08 bit3 ST Digital input or Segment Driver08 RE4/SEG09 bit4 ST Digital input or Segment Driver09 RE5/SEG10 bit5 ST Digital input or Segment Driver10 RE6/SEG11 bit6 ST Digital input or Segment Driver11 RE7/SEG27 bit7 ST Digital input or Segment Driver27 (not available on 64-pin devices)

Legend: ST = Schmitt Trigger input

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

Power-on

Reset

Value on all other resets

09h PORTE RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 0000 0000 0000 0000 89h TRISE PORTE Data Direction Control Register 1111 1111 1111 1111 10Dh LCDSE SE29 SE27 SE20 SE16 SE12 SE9 SE5 SE0 1111 1111 1111 1111

Legend: Shaded cells are not used by PORTE.

 1997 Microchip Technology Inc. DS30444E - page 39

PIC16C9XX

5.6 PORTF and TRISF Register

PORTF is an digital input only port. Each pin is multiplexed with an LCD segment driver. These pins have Schmitt Tr igger input buffers.

EXAMPLE 5-6: INITIALIZING PORTF

BCF STATUS,RP0 ;Select Bank2 BSF STATUS,RP1 ; BCF LCDSE,SE16 ;Make all PORTF BCF LCDSE,SE12 ;digital inputs

Note 1: On a Power-on Reset these pins are con-

ﬁgured as LCD segment drivers.

Note 2: To conﬁgure the pins as a digital port, the

corresponding bits in the LCDSE register must be cleared. An y bit set in the LCDSE register overrides any bit settings in the corresponding TRIS register.

FIGURE 5-9: PORTF BLOCK DIAGRAM

RD PORT

Schmitt Trigger input buffer

Q D

Digital Input/

LCDSE<n>

LCD

LCD Segment

LCD Output pin

LCD

LCD Common

Data Bus

RD TRIS

Segment Data

Output Enable

Common Data

Output Enable

TABLE 5-11: PORTF FUNCTIONS

TABLE 5-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF

Name Bit# Buffer Type Function

RF0/SEG12 bit0 ST Digital input or Segment Driver12 RF1/SEG13 bit1 ST Digital input or Segment Driver13 RF2/SEG14 bit2 ST Digital input or Segment Driver14 RF3/SEG15 bit3 ST Digital input or Segment Driver15 RF4/SEG16 bit4 ST Digital input or Segment Driver16 RF5/SEG17 bit5 ST Digital input or Segment Driver17 RF6/SEG18 bit6 ST Digital input or Segment Driver18 RF7/SEG19 bit7 ST Digital input or Segment Driver19

Legend: ST = Schmitt Trigger input

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

Power-on

Reset

Value on all

other resets

107h PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0 0000 0000 0000 0000 187h TRISF PORTF Data Direction Control Register 1111 1111 1111 1111 10Dh LCDSE SE29 SE27 SE20 SE16 SE12 SE9 SE5 SE0 1111 1111 1111 1111

Legend: Shaded cells are not used by PORTF.

PIC16C9XX

DS30444E - page 40  1997 Microchip Technology Inc.

5.7 PORTG and TRISG Register

PORTG is an digital input only port. Each pin is multiplexed with an LCD segment driver. These pins have Schmitt Tr igger input buffers.

EXAMPLE 5-7: INITIALIZING PORTG

BCF STATUS,RP0 ;Select Bank2 BSF STATUS,RP1 ; BCF LCDSE,SE27 ;Make all PORTG BCF LCDSE,SE20 ;and PORTE<7> ;digital inputs

Note 1: On a Power-on Reset these pins are con-

ﬁgured as LCD segment drivers.

Note 2: To conﬁgure the pins as a digital port, the

corresponding bits in the LCDSE register must be cleared. An y bit set in the LCDSE register overrides any bit settings in the corresponding TRIS register.

FIGURE 5-10: PORTG BLOCK DIAGRAM

RD PORT

Schmitt Trigger input buffer

Q D

Digital Input/

LCDSE<n>

LCD

LCD Segment

LCD Output pin

LCD

LCD Common

Data Bus

RD TRIS

Segment Data

Output Enable

Common Data

Output Enable

TABLE 5-13: PORTG FUNCTIONS

TABLE 5-14: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG

Name Bit# Buffer Type Function

RG0/SEG20 bit0 ST Digital input or Segment Driver20 RG1/SEG21 bit1 ST Digital input or Segment Driver21 RG2/SEG22 bit2 ST Digital input or Segment Driver22 RG3/SEG23 bit3 ST Digital input or Segment Driver23 RG4/SEG24 bit4 ST Digital input or Segment Driver24 RG5/SEG25 bit5 ST Digital input or Segment Driver25 RG6/SEG26 bit6 ST Digital input or Segment Driver26 RG7/SEG28 bit7 ST Digital input or Segment Driver28 (not available on 64-pin devices)

Legend: ST = Schmitt Trigger input

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

Power-on

Reset

Value on all other resets

108h PORTG RG7 RG6 RG5 RG4 RG3 RG2 RG1 RG0 0000 0000 0000 0000 188h TRISG PORTG Data Direction Control Register 1111 1111 1111 1111 10Dh LCDSE SE29 SE27 SE20 SE16 SE12 SE9 SE5 SE0 1111 1111 1111 1111

Legend: Shaded cells are not used by PORTG.

 1997 Microchip Technology Inc. DS30444E - page 41

PIC16C9XX

5.8 I/O Programming Considerations

5.8.1 BI-DIRECTIONAL I/O PORTS Any instruction which writes, operates internally as a

read followed by a write operation. The BCF and BSF instructions, for example, read the register into the CPU, ex ecute the bit operation and write the result back to the register. Caution must be used when these instructions are applied to a port with both inputs and outputs deﬁned. For example, a BSF operation on bit5 of PORTB will cause all eight bits of PORTB to be read into the CPU. Then the BSF operation takes place on bit5 and PORTB is written to the output latches. If another bit of PORTB is used as a bi-directional I/O pin (e.g., bit0) and it is deﬁned as an input at this time, the input signal present on the pin itself would be read into the CPU and rewritten to the data latch of this particular pin, overwriting the previous content. As long as the pin stays in the input mode, no problem occurs . Ho we ver, if bit0 is switched into output mode later on, the contents of the data latch may now be unknown.

Reading the port register, reads the values of the port pins. Writing to the por t register wr ites the value to the port latch. When using read-modify-write instructions (ex. BCF, BSF) on a por t, the value of the port pins is read, the desired operation is done to this value, and this value is then written to the port latch.

Example 5-8 shows the effect of two sequential read-modify-write instructions on an I/O port.

EXAMPLE 5-8: READ-MODIFY-WRITE

INSTRUCTIONS ON AN I/O PORT

;Initial PORT settings: PORTB<7:4> Inputs ; PORTB<3:0> Outputs ;PORTB<7:6> have external pull-ups and are ;not connected to other circuitry ; ; PORT latch PORT pins ; ---------- -------- BCF PORTB, 7 ; 01pp pppp 11pp pppp BCF PORTB, 6 ; 10pp pppp 11pp pppp BCF STATUS, RP1 ; BSF STATUS, RP0 ; BCF TRISB, 7 ; 10pp pppp 11pp pppp BCF TRISB, 6 ; 10pp pppp 10pp pppp ; ;Note that the user may have expected the ;pin values to be 00pp ppp. The 2nd BCF ;caused RB7 to be latched as the pin value ;(high).

A pin actively outputting a Low or High should not be driven from external devices at the same time in order to change the level on this pin (“wired-or”, “wired-and”). The resulting high output currents may damage the chip.

5.8.2 SUCCESSIVE OPERATIONS ON I/O P ORTS The actual write to an I/O port happens at the end of an

instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (Figure 5-11). Therefore, care must be exercised if a write followed by a read operation is carried out on the same I/O port. The sequence of instructions should be such to allow the pin voltage to stabilize (load dependent) before the next instruction which causes that ﬁle to be read into the CPU is executed. Otherwise, the previous state of that pin may be read into the CPU rather than the new state. When in doubt, it is better to separate these instructions with a NOP or another instruction not accessing this I/O port.

FIGURE 5-11: SUCCESSIVE I/O OPERATION

PC PC + 1 PC + 2

PC + 3

Q1 Q2

Instruction

fetched

RB7:RB0

MOVWF PORTB

write to PORTB

NOP

Port pin sampled here

NOP

MOVF PORTB,W

Instruction

executed

MOVWF PORTB

write to PORTB

NOP

MOVF PORTB,W

TPD

Note: This example shows a write to PORTB

followed by a read from PORTB. Note that: data setup time = (0.25TCY - TPD) where TCY = instruction cycle

TPD = propagation delay

Therefore, at higher clock frequencies, a write followed by a read ma y be problematic.

PIC16C9XX

DS30444E - page 42  1997 Microchip Technology Inc.

NOTES:

 1997 Microchip Technology Inc. DS30444E - page 43

PIC16C9XX

6.0 OVERVIEW OF TIMER MODULES

Each module can generate an interrupt to indicate that an event has occurred (e.g. timer overﬂow). Each of these modules is explained in full detail in the following sections. The timer modules are:

• Timer0 Module (Section 7.0)

• Timer1 Module (Section 8.0)

• Timer2 Module (Section 9.0)

6.1 Timer0 Overview

The Timer0 module is a simple 8-bit timer/counter. The clock source can be either the internal system clock (Fosc/4) or an external clock. When the clock source is an external clock, the Timer0 module can be selected to increment on either the rising or falling edge.

The Timer0 module also has a programmable prescaler option. This prescaler can be assigned to either the Timer0 module or the Watchdog Timer. Bit PSA (OPTION<3>) assigns the prescaler, and bits PS2:PS0 (OPTION<2:0>) determine the prescaler value. Timer0 can increment at the following rates: 1:1 when prescaler assigned to Watchdog timer, 1:2, 1:4, 1:8, 1:16, 1:32, 1:64, 1:128, and 1:256.

Synchronization of the external clock occurs after the prescaler. When the prescaler is used, the external clock frequency may be higher then the device’s frequency. The maximum frequency is 50 MHz, given the high and low time requirements of the clock.

6.2 Timer1 Overview

Timer1 is a 16-bit timer/counter. The clock source can be either the internal system clock (Fosc/4), an external clock, or an external crystal. Timer1 can operate as either a timer or a counter. When operating as a counter (external clock source), the counter can either operate synchronized to the device or asynchronously to the device. Asynchronous operation allows Timer1 to operate during sleep, which is useful for applications that require a real-time clock as well as the power savings of SLEEP mode.

Timer1 also has a prescaler option which allows Timer1 to increment at the following rates: 1:1, 1:2, 1:4, and 1:8. Timer1 can be used in conjunction with the Capture/Compare/PWM module. When used with a CCP module, Timer1 is the time-base for 16-bit capture or the 16-bit compare and must be synchronized to the device. Timer1 oscillator is also one of the clock sources for the LCD module.

6.3 Timer2 Overview

Timer2 is an 8-bit timer with a programmable prescaler and postscaler, as well as an 8-bit period register (PR2). Timer2 can be used with the CCP1 module (in PWM mode) as well as the clock source for the Syn-

chronous Serial Port (SSP). The prescaler option allows Timer2 to increment at the following rates: 1:1, 1:4, 1:16.

The postscaler allows the TMR2 register to match the period register (PR2) a programmable number of times before generating an interrupt. The postscaler can be programmed from 1:1 to 1:16 (inclusive).

6.4 CCP Overview

The CCP module can operate in one of these three modes: 16-bit capture, 16-bit compare, or up to 10-bit Pulse Width Modulation (PWM).

Capture mode captures the 16-bit value of TMR1 into the CCPR1H:CCPR1L register pair. The capture event can be programmed for either the falling edge, rising edge, fourth rising edge, or the sixteenth rising edge of the CCP1 pin.

Compare mode compares the TMR1H:TMR1L register pair to the CCPR1H:CCPR1L register pair. When a match occurs an interrupt can be generated, and the output pin CCP1 can be forced to given state (High or Low), TMR1 can be reset and star t A/D conversion. This depends on the control bits CCP1M3:CCP1M0.

PWM mode compares the TMR2 register to a 10-bit duty cycle register (CCPR1H:CCPR1L<5:4>) as well as to an 8-bit period register (PR2). When the TMR2 register = Duty Cycle register, the CCP1 pin will be forced low . When TMR2 = PR2, TMR2 is cleared to 00h, an interrupt can be generated, and the CCP1 pin (if an output) will be forced high.

PIC16C9XX

DS30444E - page 44  1997 Microchip Technology Inc.

NOTES:

 1997 Microchip Technology Inc. DS30444E - page 45

PIC16C9XX

7.0 TIMER0 MODULE

The Timer0 module has the following features:

• 8-bit timer/counter

• Readable and writable

• 8-bit software programmable prescaler

• Internal or external clock select

• Interrupt on overﬂow from FFh to 00h

• Edge select for external clock

Figure 7-1 is a simpliﬁed block diagram of the Timer0 module.

Timer mode is selected by clearing bit T0CS (OPTION<5>). In timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is inhibited for the following two instruction cycles (Figure 7-2 and Figure 7-3). The user can work around this by writing an adjusted value to the TMR0 register.

Counter mode is selected by setting bit T0CS (OPTION<5>). In counter mode Timer0 will increment either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit T0SE (OPTION<4>). Clearing

bit T0SE selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 7.2.

The prescaler is mutually exclusively shared between the Timer0 module and the Watchdog Timer. The prescaler assignment is controlled in software by control bit PSA (OPTION<3>). Clearing bit PSA will assign the prescaler to the Timer0 module. The prescaler is not readable or writable. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4, ..., 1:256 are selectable. Section 7.3 details the operation of the prescaler.

7.1 Timer0 Interrupt

The TMR0 interrupt is generated when the TMR0 register overﬂows from FFh to 00h. This overﬂow sets bit T0IF (INTCON<2>). The interrupt can be masked by clearing bit T0IE (INTCON<5>). Bit T0IF must be cleared in software by the Timer0 module interrupt service routine before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor from SLEEP since the timer is shut off during SLEEP. Figure 7-4 displays the Timer0 interrupt timing.

FIGURE 7-1: TIMER0 BLOCK DIAGRAM

FIGURE 7-2: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE

Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION<5:0>).

2: The prescaler is shared with Watchdog Timer (refer to Figure 7-6 for detailed block diagram).

RA4/T0CKI

T0SE

T0CS

FOSC/4

Programmable

Prescaler

Sync with

Internal

clocks

TMR0

PSout

(2 cycle delay)

PSout

Data bus

PSA

PS2, PS1, PS0

Set interrupt

ﬂag bit T0IF

on overﬂow

PC-1

Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC (Program Counter)

Instruction

Fetch

TMR0

PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6

T0+1 T0+2 NT0 NT0 NT0 NT0+1 NT0+2

MOVWF TMR0

MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

Write TMR0 executed

Read TMR0 reads NT0

Read TMR0 reads NT0 + 1

Read TMR0 reads NT0 + 2

Instruction Executed

PIC16C9XX

DS30444E - page 46  1997 Microchip Technology Inc.

FIGURE 7-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2

FIGURE 7-4: TIMER0 INTERRUPT TIMING

PC+

PC-1

Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC (Program Counter)

Instruction

Fetch

TMR0

PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6

T0 NT0+1

MOVWF TMR0

MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

Write TMR0 executed

Read TMR0 reads NT0

Read TMR0 reads NT0 + 1

T0+1

NT0

Instruction Execute

Q2Q1 Q3 Q4Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4

OSC1

CLKOUT(3)

Timer0

T0IF bit (INTCON<2>)

FEh

GIE bit (INTCON<7>)

INSTR

UCTION

Instruction fetched

PC +1 PC +1 0004h 0005h

Instruction executed

Inst (PC)

Inst (PC-1)

Inst (PC+1)

Inst (PC)

Inst (0004h) Inst (0005h)

Inst (0004h)Dummy cycle Dummy cycle

FFh 00h 01h 02h

Note 1: Interrupt ﬂag bit T0IF is sampled here (every Q1).

2: Interrupt latency = 4T

CY where TCY = instruction cycle time.

3: CLKOUT is available only in RC oscillator mode.

FLO

 1997 Microchip Technology Inc. DS30444E - page 47

PIC16C9XX

7.2 Using Timer0 with an External Clock

When an external clock input is used for Timer0, it must meet certain requirements. The requirements ensure the external clock can be synchronized with the internal phase clock (T

OSC). Also, there is a delay in the actual

incrementing of Timer0 after synchronization.

7.2.1 EXTERNAL CLOCK SYNCHRONIZATION

When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks (Figure 7-5). Therefore, it is necessary for T0CKI to be high for at least 2Tosc (and a small RC delay of 20 ns) and low for at least 2Tosc (and a small RC delay of 20 ns). Refer to the electrical speciﬁcation of the desired device.

When a prescaler is used, the external clock input is divided by the asynchronous ripple-counter type pres-

caler so that the prescaler output is symmetrical. For the external clock to meet the sampling requirement, the ripple-counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at least 4Tosc (and a small RC delay of 40 ns) divided by the prescaler value. The only requirement on T0CKI high and low time is that they do not violate the minimum pulse width requirement of 10 ns. Refer to par ameters 40, 41 and 42 in the electrical speciﬁcation of the desired device.

7.2.2 TMR0 INCREMENT DELAY Since the prescaler output is synchronized with the

internal clocks, there is a small delay from the time the external clock edge occurs to the time the Timer0 module is actually incremented. Figure 7-5 shows the delay from the external clock edge to the timer incrementing.

FIGURE 7-5: TIMER0 TIMING WITH EXTERNAL CLOCK

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

External Clock Input or Prescaler output

(2)

External Clock/Prescaler Output after sampling

Increment Timer0 (Q4)

Timer0

T0 T0 + 1 T0 + 2

Small pulse misses sampling

Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).

Therefore, the error in measuring the interval between two edges on Timer0 input = ±4Tosc max. 2: External clock if no prescaler selected, Prescaler output otherwise. 3: The arrows indicate the points in time where sampling occurs.

(3)

(1)

PIC16C9XX

DS30444E - page 48  1997 Microchip Technology Inc.

7.3 Prescaler

An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer (Figure 7-6). For simplicity, this counter is being referred to as “prescaler” throughout this data sheet. Note that the prescaler may be used by either the Timer0 module or the WDT but not both. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the Watchdog Timer, and vice-versa.

The PSA and PS2:PS0 bits (OPTION<3:0>) determine the prescaler assignment and prescale ratio.

When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g. CLRF 1, MOVWF 1,

BSF 1,x....etc.) will clear the prescaler count. When

assigned to WDT, a CLRWDT instruction will clear the prescaler count along with the Watchdog Timer. The prescaler is not readable or writable.

Note: Writing to TMR0 when the prescaler is

assigned to Timer0 will clear the prescaler count, but will not change the prescaler assignment.

FIGURE 7-6: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

RA4/T0CKI

T0SE

M U

CLKOUT (=Fosc/4)

SYNC

Cycles

TMR0 reg

8-bit Prescaler

8 - to - 1MUX

M U

M U X

Watchdog

Timer

PSA

WDT

Time-out

PS2:PS0

Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION<5:0>).

PSA

WDT Enable bit

U X

Data Bus

Set ﬂag bit T0IF

on Overﬂow

PSA

T0CS

 1997 Microchip Technology Inc. DS30444E - page 49

PIC16C9XX

7.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software con-

trol, i.e., it can be changed “on the ﬂy” during program execution.

Note: To avoid an unintended device RESET, the

following instruction sequence (shown in Example 7-1) must be executed when changing the prescaler assignment from Timer0 to the WDT. This precaution must be followed even if the WDT is disabled.

EXAMPLE 7-1: CHANGING PRESCALER (TIMER0→WDT)

To change prescaler from the WDT to the Timer0 module use the precaution shown in Example 7-2.

EXAMPLE 7-2: CHANGING PRESCALER (WDT→TIMER0)

CLRWDT ;Clear WDT and prescaler BSF STATUS, RP0 ;Select Bank1 MOVLW b'xxxx0xxx' ;Select TMR0, new prescale value and MOVWF OPTION_REG ;clock source BCF STATUS, RP0 ;Select Bank0

TABLE 7-1: REGISTERS ASSOCIATED WITH TIMER0

1) BSF STATUS, RP0 ;Select Bank1

Lines 2 and 3 do NOT have to be included if the ﬁnal desired prescale value is other than 1:1. If 1:1 is ﬁnal desired value, then a temporary prescale value is set in lines 2 and 3 and the ﬁnal prescale value will be set in lines 10 and 11.

2) MOVLW b'xx0x0xxx' ;Select clock source and prescale value of

3) MOVWF OPTION_REG ;other than 1:1

4) BCF STATUS, RP0 ;Select Bank0

5) CLRF TMR0 ;Clear TMR0 and prescaler

6) BSF STATUS, RP1 ;Select Bank1

7) MOVLW b'xxxx1xxx' ;Select WDT, do not change prescale value

8) MOVWF OPTION_REG ;

9) CLRWDT ;Clears WDT and prescaler

10) MOVLW b'xxxx1xxx' ;Select new prescale value and WDT

11) MOVWF OPTION_REG ;

12) BCF STATUS, RP0 ;Select Bank0

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

Power-on

Reset

Value on all

other resets

01h, 101h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu 0Bh, 8Bh,

10Bh, 18Bh

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

81h, 181h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 85h TRISA — — PORTA Data Direction Control Register --11 1111 --11 1111

Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.

PIC16C9XX

DS30444E - page 50  1997 Microchip Technology Inc.

NOTES:

 1997 Microchip Technology Inc. DS30444E - page 51

PIC16C9XX

8.0 TIMER1 MODULE

Timer1 is a 16-bit timer/counter consisting of two 8-bit registers (TMR1H and TMR1L) which are readable and writable. The TMR1 Register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 Interrupt, if enabled, is generated on overﬂow which is latched in interrupt ﬂag bit TMR1IF (PIR1<0>). This interr upt can be enabled/disabled by setting/clearing TMR1 interrupt enable bit TMR1IE (PIE1<0>).

Timer1 can operate in one of two modes:

• As a timer

• As a counter The operating mode is determined by the clock select

bit, TMR1CS (T1CON<1>). In timer mode, Timer1 increments every instruction

cycle. In counter mode, it increments on every rising edge of the external clock input.

Timer1 can be turned on and off using the control bit TMR1ON (T1CON<0>).

Timer1 also has an internal “reset input”. This reset can be generated by the CCP module (Section 10.0). Figure 8-1 shows the Timer1 control register.

When the Timer1 oscillator is enabled (T1OSCEN is set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins become inputs.

FIGURE 8-1: T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON R = Readable bit

W = Writable bit U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7-6: Unimplemented: Read as '0' bit 5-4: T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits

11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value

bit 3: T1OSCEN: Timer1 Oscillator Enable Control bit

1 = Oscillator is enabled 0 = Oscillator is shut off Note: The oscillator inverter and feedback resistor are turned off to eliminate power drain

bit 2: T1SYNC

: Timer1 External Clock Input Synchronization Control bit

TMR1CS = 1 1 = Do not synchronize external clock input 0 = Synchronize external clock input

TMR1CS = 0 This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.

bit 1: TMR1CS: Timer1 Clock Source Select bit

1 = External clock from pin T1CKI (on the rising edge) 0 = Internal clock (Fosc/4)

bit 0: TMR1ON: Timer1 On bit

1 = Enables Timer1 0 = Stops Timer1

PIC16C9XX

DS30444E - page 52  1997 Microchip Technology Inc.

8.1 Timer1 Operation in Timer Mode

Timer mode is selected by clearing the TMR1CS (T1CON<1>) bit. In this mode, the input clock to the timer is Fosc/4. The synchronize control bit T1SYNC (T1CON<2>) has no effect since the internal clock is always in sync.

8.2 Timer1 Operation in Synchronized Counter Mode

Counter mode is selected by setting bit TMR1CS. In this mode the timer increments on every rising edge of clock input on pin RC1/T1OSI when bit T1OSCEN is set or pin RC0/T1OSO/T1CKI when bit T1OSCEN is cleared.

If T1SYNC

is cleared, then the external clock input is synchronized with internal phase clocks. The synchronization is done after the prescaler stage. The prescaler is an asynchronous ripple-counter.

In this conﬁguration, during SLEEP mode, Timer1 will not increment even if the external clock is present, since the synchronization circuit is shut off. The prescaler however will continue to increment.

8.2.1 EXTERNAL CLOCK INPUT TIMING FOR SYNCHRONIZED COUNTER MODE

When an external clock input is used for Timer1 in synchronized counter mode, it must meet certain requirements. The external clock requirement is due to internal phase clock (T osc) synchronization. Also, there is a delay in the actual incrementing of TMR1 after synchronization.

When the prescaler is 1:1, the external clock input is the same as the prescaler output. The synchronization of T1CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore, it is necessary for T1CKI to be high for at least 2Tosc (and a small RC delay of 20 ns) and low for at least 2Tosc (and a small RC delay of 20 ns). Refer to the appropriate electrical speciﬁcations, parameters 45, 46, and 47.

When a prescaler other than 1:1 is used, the external clock input is divided by the asynchronous ripple-counter type prescaler so that the prescaler output is symmetrical. In order for the external clock to meet the sampling requirement, the ripple-counter must be taken into account. Theref ore , it is necessary for T1CKI to have a period of at least 4Tosc (and a small RC delay of 40 ns) divided by the prescaler value. The only requirement on T1CKI high and low time is that the y do not violate the minimum pulse width requirements of 10 ns). Refer to the appropriate electrical speciﬁcations, parameters 40, 42, 45, 46, and 47.

FIGURE 8-2: TIMER1 BLOCK DIAGRAM

TMR1H

TMR1L

T1OSC

T1SYNC

TMR1CS

T1CKPS1:T1CKPS0

SLEEP input

T1OSCEN Enable

Oscillator

(1)

Fosc/4 Internal

Clock

TMR1ON

on/off

Prescaler

1, 2, 4, 8

Synchronize

det

Synchronized

clock input

RC0/T1OSO/T1CKI

RC1/T1OSI

Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.

Set ﬂag bit TMR1IF on Overﬂow

TMR1

 1997 Microchip Technology Inc. DS30444E - page 53

PIC16C9XX

8.3 Timer1 Operation in Asynchronous Counter Mode

If control bit T1SYNC (T1CON<2>) is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during SLEEP and can generate an interrupt on overﬂow which will wake-up the processor. However, special precautions in software are needed to read-from or write-to the Timer1 register pair (TMR1H:TMR1L) (Section 8.3.2).

In asynchronous counter mode, Timer1 cannot be used as a time-base for capture or compare operations.

8.3.1 EXTERNAL CLOCK INPUT TIMING WITH UNSYNCHRONIZED CLOCK

If control bit T1SYNC

is set, the timer will increment completely asynchronously. The input clock must meet certain minimum high time and low time requirements, as speciﬁed in timing parameters 45, 46, and 47.

8.3.2 READING AND WRITING TMR1 IN

ASYNCHRONOUS COUNTER MODE

Reading TMR1H or TMR1L while the timer is running, from an external asynchronous clock, will ensure a valid read (taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself poses certain problems since the timer may overﬂow between the reads.

For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers while the register is incrementing. This may produce an unpredictable value in the timer register.

Reading the 16-bit value requires some care. Example 8-1 is an example routine to read the 16-bit timer value. This is useful if the timer cannot be stopped.

EXAMPLE 8-1: READING A 16-BIT

FREE-RUNNING TIMER

; All interrupts are disabled MOVF TMR1H, W ;Read high byte MOVWF TMPH ; MOVF TMR1L, W ;Read low byte MOVWF TMPL ; MOVF TMR1H, W ;Read high byte SUBWF TMPH, W ;Sub 1st read ; with 2nd read BTFSC STATUS,Z ;Is result = 0 GOTO CONTINUE ;Good 16-bit read ; ; TMR1L may have rolled over between the read ; of the high and low bytes. Reading the high ; and low bytes now will read a good value. ; MOVF TMR1H, W ;Read high byte MOVWF TMPH ; MOVF TMR1L, W ;Read low byte MOVWF TMPL ; ; Re-enable the Interrupt (if required) CONTINUE ;Continue with your code

8.4 Timer1 Oscillator

A crystal oscillator circuit is built in between pins T1OSI (input) and T1OSO (ampliﬁer output). It is enabled by setting control bit T1OSCEN (T1CON<3>). The oscillator is a low power oscillator rated up to 200 kHz. It will continue to run during SLEEP. It is primarily intended for a 32 kHz crystal. Table 8-1 shows the capacitor selection for the Timer1 oscillator.

The Timer1 oscillator is identical to the LP oscillator. The user must provide a software time delay to ensure proper oscillator start-up.

TABLE 8-1: CAPACITOR SELECTION FOR

THE TIMER1 OSCILLATOR

Osc Type Freq C1 C2

LP 32 kHz 33 pF 33 pF

100 kHz 15 pF 15 pF 200 kHz 15 pF 15 pF

These values are for design guidance only.

Crystals Tested:

32.768 kHz Epson C-001R32.768K-A ± 20 PPM 100 kHz Epson C-2 100.00 KC-P ± 20 PPM 200 kHz STD XTL 200.000 kHz ± 20 PPM Note 1: Higher capacitance increases the stability

of oscillator but also increases the start-up time.

2: Since each resonator/crystal has its own

characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components.

PIC16C9XX

DS30444E - page 54  1997 Microchip Technology Inc.

8.5 Resetting Timer1 using the CCP Trigger Output

If the CCP1 module is conﬁgured in compare mode to generate a “special event tr igger" (CCP1M3:CCP1M0 = 1011), this signal will reset Timer1.

Timer1 must be conﬁgured for either timer or synchronized counter mode to take advantage of this f eature. If Timer1 is running in asynchronous counter mode, this reset operation may not work.

In the event that a write to Timer1 coincides with a special event trigger from CCP1, the write will take precedence.

In this mode of operation, the CCPR1H:CCPR1L registers pair effectively becomes the period register for Timer1.

Note: The special event trigger from the CCP1

module will not set interrupt ﬂag bit TMR1IF (PIR1<0>).

8.6 Resetting of Timer1 Register Pair (TMR1H:TMR1L)

TMR1H and TMR1L registers are not reset on a POR or any other reset except by the CCP1 special event trigger.

T1CON register is reset to 00h on a Power-on Reset. In any other reset, the register is unaffected.

8.7 Timer1 Prescaler

The prescaler counter is cleared on writes to the TMR1H or TMR1L registers.

TABLE 8-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

Power-on

Reset

Value on all other

resets

0Bh, 8Bh, 10Bh, 18Bh

INTCON GIE PEIE

T0IE INTE RBIE T0IF INTF RBIF

0000 000x 0000 000u

0Ch PIR1 LCDIF ADIF

(1)

— — SSPIF CCP1IF TMR2IF TMR1IF

00-- 0000 00-- 0000

8Ch PIE1

LCDIE ADIE

(1)

— — SSPIE CCP1IE TMR2IE TMR1IE

00-- 0000 00-- 0000

0Eh TMR1L Holding register for the Least Signiﬁcant Byte of the 16-bit TMR1 register

xxxx xxxx uuuu uuuu

0Fh TMR1H Holding register for the Most Signiﬁcant Byte of the 16-bit TMR1 register

xxxx xxxx uuuu uuuu

10h T1CON

— — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

--00 0000 --uu uuuu

Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by theTimer1 module. Note 1: Bits ADIE and ADIF are reserved on the PIC16C923, always maintain these bits clear.

 1997 Microchip Technology Inc. DS30444E - page 55

PIC16C9XX

9.0 TIMER2 MODULE

Timer2 is an 8-bit timer with a prescaler and a postscaler. It can be used as the PWM time-base for the PWM mode of the CCP module. The TMR2 register is readable and writable, and is cleared on any device reset.

The input clock (F

OSC/4) has a prescale option of 1:1,

1:4 or 1:16 (selected by control bits T2CKPS1:T2CKPS0 (T2CON<1:0>)).

The Timer2 module has an 8-bit period register, PR2. TMR2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is set during RESET.

The match output of TMR2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR2 interrupt (latched in ﬂag bit TMR2IF, (PIR1<1>)).

Timer2 can be shut off by clearing control bit TMR2ON (T2CON<2>) to minimize power consumption.

Figure 9-2 shows the Timer2 control register.

9.1 Timer2 Prescaler and Postscaler

The prescaler and postscaler counters are cleared when any of the following occurs:

• a write to the TMR2 register

• a write to the T2CON register

• any device reset (Power-on Reset, MCLR

Reset,

or Watchdog Timer Reset)

TMR2 will not clear when T2CON is written.

9.2 Output of TMR2

The output of TMR2 (bef ore the postscaler) is fed to the Synchronous Serial Port module which optionally uses it to generate shift clock.

FIGURE 9-1: TIMER2 BLOCK DIAGRAM

Comparator

TMR2

Sets ﬂag

TMR2 reg

output

(1)

Reset

Postscaler

Prescaler

PR2 reg

Fosc/4

1:1

1:16

1:1, 1:4, 1:16

bit TMR2IF

Note 1: TMR2 register output can be software selected

by the SSP Module as the source clock.

FIGURE 9-2: T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 R = Readable bit

W = Writable bit U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: Unimplemented: Read as '0' bit 6-3: TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits

0000 = 1:1 Postscale 0001 = 1:2 Postscale

•

• 1111 = 1:16 Postscale

bit 2: TMR2ON: Timer2 On bit

1 = Timer2 is on 0 = Timer2 is off

bit 1-0: T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits

00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16

PIC16C9XX

DS30444E - page 56  1997 Microchip Technology Inc.

TABLE 9-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

Power-on

Reset

Value on all other

resets

0Bh, 8Bh, 10Bh, 18Bh

INTCON GIE PEIE

T0IE INTE RBIE T0IF INTF RBIF

0000 000x 0000 000u

0Ch PIR1 LCDIF ADIF

(1)

— — SSPIF CCP1IF TMR2IF TMR1IF

00-- 0000 00-- 0000

8Ch PIE1

LCDIE ADIE

(1)

— — SSPIE CCP1IE TMR2IE TMR1IE

00-- 0000 00-- 0000

11h TMR2 Timer2 module’s register

0000 0000 0000 0000

12h T2CON

— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0

-000 0000 -000 0000

92h PR2 Timer2 Period Register

1111 1111 1111 1111

Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer2 module. Note 1: Bits ADIE and ADIF are reserved on the PIC16C923, always maintain these bits clear.

 1997 Microchip Technology Inc. DS30444E - page 57

PIC16C9XX

10.0 CAPTURE/COMPARE/PWM (CCP) MODULE

The CCP (Capture/Compare/PWM) module contains a 16-bit register which can operate as a 16-bit capture register, as a 16-bit compare register, or as a PWM master/slave duty cycle register. Table 10-1 shows the timer resources used by the CCP module.

Capture/Compare/PWM Register1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON register controls the operation of CCP1. All three are readable and writable.

Figure 10-1 shows the CCP1CON register.

For use of the CCP module, refer to the

Embedded

Control Handbook,

"Using the CCP Modules" (AN594).

T ABLE 10-1: CCP MODE - TIMER RESOURCE

CCP Mode Timer Resource

Capture

Compare

PWM

Timer1 Timer1 Timer2

FIGURE 10-1: CCP1CON REGISTER (ADDRESS 17h)

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 R = Readable bit

W =Writable bit U = Unimplemented bit,

read as ‘0’

- n =Value at POR reset

bit7 bit0

bit 7-6: Unimplemented: Read as '0' bit 5-4: CCP1X:CCP1Y: PWM Least Signiﬁcant bits

Capture Mode Unused Compare Mode Unused PWM Mode These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L.

bit 3-0: CCP1M3:CCP1M0: CCP1 Mode Select bits

0000 = Capture/Compare/PWM off (resets CCP1 module) 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, set output on match (bit CCP1IF is set) 1001 = Compare mode, clear output on match (bit CCP1IF is set) 1010 = Compare mode, generate software interrupt on match (bit CCP1IF is set, CCP1 pin is unaffected) 1011 = Compare mode, trigger special event (CCP1IF bit is set; CCP1 resets TMR1) 11xx = PWM mode

PIC16C9XX

DS30444E - page 58  1997 Microchip Technology Inc.

10.1 Capture Mode

In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an e v ent occurs on pin RC2/CCP1 (Figure 10-2). An event is deﬁned as:

• Every falling edge

• Every rising edge

• Every 4th rising edge

• Every 16th rising edge An event is selected by control bits CCP1M3:CCP1M0

(CCP1CON<3:0>). When a capture is made, the interrupt request ﬂag bit CCP1IF (PIR1<2>) is set. It must be cleared in software. If another capture occurs before the value in register CCPR1 is read, the old captured value will be lost.

10.1.1 CCP PIN CONFIGURATION In capture mode, the RC2/CCP1 pin should be conﬁg-

ured as an input by setting the TRISC<2> bit.

FIGURE 10-2: CAPTURE MODE OPERATION

BLOCK DIAGRAM

10.1.2 TIMER1 MODE SELECTION Timer1 must be running in timer mode or synchronized

counter mode for the CCP module to use the capture feature. In asynchronous counter mode the capture operation may not work.

10.1.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture

interrupt may be generated. The user should keep enable bit CCP1IE (PIE1<2>) clear to avoid false interrupts and should clear ﬂag bit CCP1IF following any such change in operating mode.

10.1.4 CCP PRESCALER There are four prescaler settings, speciﬁed by bits

CCP1M3:CCP1M0. Whenever the CCP module is turned off, or the CCP module is not in Capture mode, the prescaler counter is cleared. This means that any reset will clear the prescaler counter.

Note: If the RC2/CCP1 pin is conﬁgured as an

output, a write to the port can cause a capture condition.

CCPR1H CCPR1L

TMR1H TMR1L

Set CCP1IF

PIR1<2>

Capture Enable

Q’s

CCP1CON<3:0>

RC2/CCP1

Prescaler

÷ 1, 4, 16

and

edge detect

CCP

Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will not be cleared, therefore the ﬁrst capture may be from a non-zero prescaler. Example 10-1 shows the recommended method for switching between capture prescalers. This example also clears the prescaler counter and will not generate the “false” interrupt.

EXAMPLE 10-1: CHANGING BETWEEN

CAPTURE PRESCALERS

CLRF CCP1CON ; Turn CCP module off MOVLW NEW_CAPT_PS ; Load the W reg with

; the new prescaler ; mode value and CCP ON

MOVWF CCP1CON ; Load CCP1CON with

; this value

10.2 Compare Mode

In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the RC2/CCP1 pin is:

• Driven High

• Driven Low

• Remains Unchanged The action on the pin is based on the value of control

bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the same time, a compare interrupt is also generated.

FIGURE 10-3: COMPARE MODE

OPERATION BLOCK DIAGRAM

10.2.1 CCP PIN CONFIGURATION The user must conﬁgure the RC2/CCP1 pin as an out-

put by clearing the TRISC<2> bit.

Note: Clearing the CCP1CON register will force

the RC2/CCP1 compare output latch to the default low level. This is not the data latch.

CCPR1H CCPR1L

TMR1H TMR1L

Comparator

Q S

Output

Logic

Special event trigger will reset Timer1, but not

Trigger

Set CCP1IF PIR1<2>

match

RC2/CCP1

TRISC<2>

CCP1CON<3:0>

Mode Select

Output Enable

set interrupt ﬂag bit TMR1IF (PIR1<0>).

 1997 Microchip Technology Inc. DS30444E - page 59

PIC16C9XX

10.2.1 TIMER1 MODE SELECTION

Timer1 must be running in Timer mode or Synchronized Counter mode if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work.

10.2.2 SOFTWARE INTERRUPT MODE

When Generate Software Interrupt is chosen, the CCP1 pin is not affected. Only a CCP interrupt is generated (if enabled).

10.2.3 SPECIAL EVENT TRIGGER

In this mode, an internal hardware trigger is generated which may be used to initiate an action.

The special event trigger output of CCP1 resets the TMR1 register pair and starts an A/D conversion. This allows the CCPR1H:CCPR1L register pair to effectively be a 16-bit programmable period register for Timer1.

10.3 PWM Mode

In Pulse Width Modulation (PWM) mode, the CCP1 pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the POR TC data latch, the TRISC<2> bit must be cleared to make the CCP1 pin an output.

Figure 10-4 shows a simpliﬁed block diagram of the CCP module in PWM mode.

For a step by step procedure on how to set up the CCP module for PWM operation, see Section 10.3.3.

Note: The "special event trigger" from the CCP1

module will not set interrupt ﬂag bit TMR1IF (PIR1<0>).

Note: Clearing the CCP1CON register will force

the CCP1 PWM output latch to the default low level. This is not the PORTC I/O data latch.

FIGURE 10-4: SIMPLIFIED PWM BLOCK

DIAGRAM

A PWM output (Figure 10-5) has a time-base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period).

FIGURE 10-5: PWM OUTPUT

10.3.1 PWM PERIOD The PWM period is speciﬁed by writing to the PR2 reg-

ister. The PWM period can be calculated using the following formula:

PWM period = [ (PR2) + 1 ] • 4 • T

OSC •

(TMR2 prescale value)

PWM frequency is deﬁned as 1 / [PWM period]. When TMR2 is equal to PR2, the following three events

occur on the next increment cycle:

• TMR2 is cleared

• The CCP1 pin is set (exception: if PWM duty cycle = 0%, the CCP1 pin will not be set)

• The PWM duty cycle is latched from CCPR1L into CCPR1H

CCPR1L

CCPR1H (Slave)

Comparator

TMR2

Comparator

PR2

(Note 1)

Duty cycle registers

CCP1CON<5:4>

Clear Timer, CCP1 pin and latch D.C.

TRISC<2>

RC1/CCP1

Note 1: 8-bit timer is concatenated with 2-bit internal Q clock

or 2 bits of the prescaler to create 10-bit time-base.

Period

Duty Cycle

TMR2 = PR2

TMR2 = Duty Cycle

TMR2 = PR2

PIC16C9XX

DS30444E - page 60  1997 Microchip Technology Inc.

10.3.2 PWM DUTY CYCLE The PWM duty cycle is speciﬁed by writing to the

CCPR1L register and to the CCP1CON<5:4> bits. Up to 10-bit resolution is available: the CCPR1L contains the eight MSbs and CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The following equation is used to calculate the PWM duty cycle in time:

PWM duty cycle = (CCPR1L:CCP1CON<5:4>) • Tosc • (TMR2 prescale value)

CCPR1L and CCP1CON<5:4> can be written to at any time, but the duty cycle value is not latched into CCPR1H until after a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPR1H is a read-only register.

The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation.

When the CCPR1H and 2-bit latch match TMR2 concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 prescaler, the CCP1 pin is cleared.

Maximum PWM resolution (bits) for a given PWM frequency:

Note: The Timer2 postscaler (Section 9.0) is not

used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output.

Note: If the PWM duty cycle value is longer than

the PWM period the CCP1 pin will not be cleared.

log(

PWM

log(2)

OSC

)

bits

EXAMPLE 10-2: PWM PERIOD AND DUTY

CYCLE CALCULATION

Desired PWM frequency is 31.25 kHz, Fosc = 8 MHz TMR2 prescale = 1

1/31.25 kHz = [ (PR2) + 1 ] • 4 • 1/8 MHz • 1 32 µs = [ (PR2) + 1 ] • 4 • 125 ns • 1 PR2 = 63

Find the maximum resolution of the duty cycle that can be used with a 31.25 kHz frequency and 8 MHz oscillator:

1/31.25 kHz = 2

PWM RESOLUTION

• 1/8 MHz • 1

32 µs = 2

PWM RESOLUTION

• 125 ns • 1

256 = 2

PWM RESOLUTION

log(256) = (PWM Resolution) • log(2)

8.0 = PWM Resolution

At most, an 8-bit resolution duty cycle can be obtained from a 31.25 kHz frequency and a 8 MHz oscillator, i.e., 0 ≤ CCPR1L:CCP1CON<5:4> ≤ 255. Any v alue greater than 255 will result in a 100% duty cycle.

In order to achieve higher resolution, the PWM frequency must be decreased. In order to achieve higher PWM frequency, the resolution must be decreased.

Table 10-2 lists example PWM frequencies and resolutions for Fosc = 8 MHz. TMR2 prescaler and PR2 values are also shown.

10.3.3 SET-UP FOR PWM OPERATION The following steps should be taken when conﬁguring

the CCP module for PWM operation:

1. Set the PWM period by writing to the PR2 register.

2. Set the PWM duty cycle by writing to the CCPR1L register and CCP1CON<5:4> bits.

3. Make the CCP1 pin an output by clearing the TRISC<2> bit.

4. Set the TMR2 prescale value and enable Timer2 by writing to T2CON.

5. Conﬁgure the CCP module for PWM operation.

TABLE 10-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 8 MHz

PWM Frequency 488 Hz 1.95 kHz 7.81 kHz 31.25 kHz 62.5 kHz 250 kHz

Timer Prescaler (1, 4, 16) 16 4 1 1 1 1 PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x07 Maximum Resolution (bits) 10 10 10 8 7 5

 1997 Microchip Technology Inc. DS30444E - page 61

PIC16C9XX

TABLE 10-3: REGISTERS ASSOCIATED WITH TIMER1, CAPTURE AND COMPARE

TABLE 10-4: REGISTERS ASSOCIATED WITH PWM AND TIMER2

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

Power-on

Reset

Value on all other

Resets

0Bh, 8Bh, 10Bh, 18Bh

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF

0000 000x 0000 000u

0Ch PIR1 LCDIF ADIF

(1)

— — SSPIF CCP1IF TMR2IF TMR1IF

00-- 0000 00-- 0000

8Ch PIE1 LCDIE ADIE

(1)

— — SSPIE CCP1IE TMR2IE TMR1IE

00-- 0000 00-- 0000

87h TRISC — — PORTC Data Direction Control Register --11 1111 --11 1111 0Eh TMR1L Holding register for the Least Signiﬁcant Byte of the 16-bit TMR1 register

xxxx xxxx uuuu uuuu

0Fh TMR1H Holding register for the Most Signiﬁcant Byte of the 16-bit TMR1 register

xxxx xxxx uuuu uuuu

10h T1CON

— — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

--00 0000 --uu uuuu

15h CCPR1L Capture/Compare/PWM1 (LSB)

xxxx xxxx uuuu uuuu

16h CCPR1H Capture/Compare/PWM1 (MSB)

xxxx xxxx uuuu uuuu

17h CCP1CON

— — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0

--00 0000 --00 0000

Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0’. Shaded cells are not used in these modes. Note 1: Bits ADIE and ADIF reserved on the PIC16C923, always maintain these bits clear.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

Power-on

Reset

Value on

all other

Resets

0Bh, 8Bh, 10Bh, 18Bh

INTCON GIE PEIE

T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1

LCDIF ADIF

(1)

— — SSPIF CCP1IF TMR2IF TMR1IF 00-- 0000 00-- 0000

8Ch PIE1

LCDIE ADIE

(1)

— — SSPIE CCP1IE TMR2IE TMR1IE 00-- 0000 00-- 0000

87h TRISC

— — PORTC Data Direction Control Register --11 1111 --11 1111 11h TMR2 Timer2 module’s register 0000 0000 0000 0000 92h PR2 Timer2 module’s Period register 1111 1111 1111 1111 12h T2CON

— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 15h CCPR1L Capture/Compare/PWM1 (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM1 (MSB) xxxx xxxx uuuu uuuu 17h CCP1CON

— — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0’. Shaded cells are not used in this mode.

Note 1: Bits ADIE and ADIF reserved on the PIC16C923, always maintain these bits clear.

PIC16C9XX

DS30444E - page 62  1997 Microchip Technology Inc.

NOTES:

 1997 Microchip Technology Inc. DS30444E - page 63

PIC16C9XX

11.0 SYNCHRONOUS SERIAL PORT (SSP) MODULE

The Synchronous Serial Port (SSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, dis-

play drivers, A/D converters, etc. The SSP module can operate in one of two modes:

• Serial Peripheral Interface (SPI)

• Inter-Integrated Circuit (I

Refer to Application Note AN578,

"Use of the SSP

Module in the I

C Multi-Master Environment."

FIGURE 11-1: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h)

R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0

SMP CKE D/A

P S R/W UA BF R = Readable bit

W =Writable bit U = Unimplemented bit,

read as ‘0’

- n =Value at POR reset

bit7 bit0

bit 7: SMP: SPI data input sample phase

SPI Master Mode 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Sla

ve Mode

SMP must be cleared when SPI is used in slave mode

bit 6: CKE: SPI Clock Edge Select (Figure 11-5, Figure 11-6, and Figure 11-7)

CKP = 0 1 = Data transmitted on rising edge of SCK 0 = Data transmitted on falling edge of SCK CKP = 1 1 = Data transmitted on falling edge of SCK 0 = Data transmitted on rising edge of SCK

bit 5: D/A

: Data/Address bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address

bit 4: P: Stop bit (I

C mode only. This bit is cleared when the SSP module is disabled, or when the Start bit was

detected last) 1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET) 0 = Stop bit was not detected last

bit 3: S: Start bit (I

C mode only. This bit is cleared when the SSP module is disabled, or when the Stop bit was

detected last) 1 = Indicates that a start bit has been detected last (this bit is '0' on RESET) 0 = Start bit was not detected last

bit 2: R/W

: Read/Write bit information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next start bit, stop bit, or A

CK bit. 1 = Read 0 = Write

bit 1: UA: Update Address (10-bit I

C mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated

bit 0: BF: Buffer Full Status bit

Receiv

e (SPI and I2C modes) 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty

ransmit (I2C mode only) 1 = Transmit in progress, SSPBUF is full 0 = Transmit complete, SSPBUF is empty

PIC16C9XX

DS30444E - page 64  1997 Microchip Technology Inc.

FIGURE 11-2: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 R = Readable bit

W =Writable bit U = Unimplemented bit,

read as ‘0’

- n =Value at POR reset

bit7 bit0

bit 7: WCOL: Write Collision Detect bit

1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision

bit 6: SSPOV: Receive Overﬂow Indicator bit

In SPI mode 1 = A new byte is received while the SSPBUF register is still holding the pre vious data. In case of ov erﬂow , the data in SSPSR is lost. Ov erﬂow can only occur in sla v e mode. The user must read the SSPBUF, even if only transmitting data, to avoid setting overﬂow. In master mode the overﬂow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 0 = No overﬂow

In I

C mode 1 = A byte is received while the SSPBUF register is still holding the pre vious byte. SSPO V is a "don’t care" in transmit mode. SSPOV must be cleared in software in either mode. 0 = No overﬂow

bit 5: SSPEN: Synchronous Serial Port Enable bit

In SPI mode 1 = Enables serial port and conﬁgures SCK, SDO, and SDI as serial port pins 0 = Disables serial port and conﬁgures these pins as I/O port pins

In I

C mode 1 = Enables the serial port and conﬁgures the SDA and SCL pins as serial port pins 0 = Disables serial port and conﬁgures these pins as I/O port pins In both modes, when enabled, these pins must be properly conﬁgured as input or output.

bit 4: CKP: Clock Polarity Select bit

In SPI mode 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level In I

C mode SCK release control 1 = Enable clock 0 = Holds clock low (clock stretch) (Used to ensure data setup time)

bit 3-0: SSPM3:SSPM0: Synchronous Serial Port Mode Select bits

0000 = SPI master mode, clock = F

OSC/4

0001 = SPI master mode, clock = F

OSC/16

0010 = SPI master mode, clock = F

OSC/64

0011 = SPI master mode, clock = TMR2 output/2 0100 = SPI slave mode, clock = SCK pin. SS

pin control enabled.

0101 = SPI slave mode, clock = SCK pin. SS

pin control disabled. SS can be used as I/O pin

0110 = I

C slave mode, 7-bit address

0111 = I

C slave mode, 10-bit address

1011 = I

C Firmware controlled master mode (slave idle)

1110 = I

C slave mode, 7-bit address with start and stop bit interrupts enabled

1111 = I

C slave mode, 10-bit address with start and stop bit interrupts enabled

 1997 Microchip Technology Inc. DS30444E - page 65

PIC16C9XX

11.1 SPI Mode

The SPI mode allows 8-bits of data to be synchronously transmitted and received simultaneously. To accomplish communication, typically three pins are used:

• Serial Data Out (SDO) RC5/SDO

• Serial Data In (SDI) RC4/SDI

• Serial Clock (SCK) RC3/SCK Additionally a fourth pin may be used when in a slave

mode of operation:

• Slave Select (SS

) RA5/AN4/SS (the AN4 function

is implemented on the PIC16C924 only)

When initializing the SPI, several options need to be speciﬁed. This is done by programming the appropriate control bits in the SSPCON register (SSPCON<5:0>) and SSPSTAT<7:6>. These control bits allow the following to be speciﬁed:

• Master Mode (SCK is the clock output)

• Slave Mode (SCK is the clock input)

• Clock Polarity (Idle state of SCK)

• Clock edge (output data on rising/falling edge of SCK)

• Clock Rate (Master mode only)

• Slave Select Mode (Slave mode only)

The SSP consists of a transmit/receive Shift Register (SSPSR) and a buffer register (SSPBUF). The SSPSR shifts the data in and out of the device, MSb ﬁrst. The SSPBUF holds the data that was written to the SSPSR, until the received data is ready. Once the 8-bits of data have been received, that b yte is mov ed to the SSPBUF register. Then the buffer full detect bit BF (SSPSTAT<0>) and interrupt ﬂag bit SSPIF (PIR1<3>) are set. This double buffering of the received data (SSPBUF) allows the next byte to start reception before reading the data that was just received. Any write to the SSPBUF register during transmission/reception of data will be ignored, and the write collision detect bit WCOL (SSPCON<7>) will be set. User software m ust clear the WCOL bit so that it can be determined if the following write(s) to the SSPBUF register completed successfully. When the application software is expecting to receive valid data, the SSPBUF should be read before the next byte of data to transfer is written to the SSPBUF. Buffer full bit BF (SSPSTAT<0>) indicates when SSPBUF has been loaded with the received data (transmission is complete). When the SSPBUF is read, bit BF is cleared. This data may be irrelevant if the SPI is only a transmitter. Generally the SSP Interrupt is used to determine when the transmission/reception has completed. The SSPB UF must be read and/or written. If the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. Example 11-1 shows the loading of the SSPBUF (SSPSR) for data transmission. The shaded instruction is only required if the received data is meaningful.

EXAMPLE 11-1: LOADING THE SSPBUF

(SSPSR) REGISTER

BCF STATUS, RP1 ;Select Bank1 BSF STATUS, RP0 ; LOOP BTFSS SSPSTAT, BF ;Has data been ;received ;(transmit ;complete)? GOTO LOOP ;No BCF STATUS, RP0 ;Select Bank0 MOVF SSPBUF, W ;W reg = contents ; of SSPBUF

MOVF TXDATA, W ;W reg = contents ; of TXDATA MOVWF SSPBUF ;New data to xmit

The block diagram of the SSP module, when in SPI mode (Figure 11-3), shows that the SSPSR is not directly readable or writable, and can only be accessed from addressing the SSPBUF register. Additionally, the SSP status register (SSPSTAT) indicates the var ious status conditions.

FIGURE 11-3: SSP BLOCK DIAGRAM

(SPI MODE)

MOVWF RXDATA ;Save in user RAM

Read Write

Internal

data bus

RC4/SDI/SDA

RC5/SDO

RA5/AN4/SS

RC3/SCK/

SSPSR reg

SSPBUF reg

SSPM3:SSPM0

bit0

shift

clock

Control Enable

Edge

Select

Clock Select

TMR2 output

Prescaler

4, 16, 64

TRISC<3>

Edge

Select

SCL

PIC16C9XX

DS30444E - page 66  1997 Microchip Technology Inc.

To enable the serial port, SSP Enable bit, SSPEN (SSPCON<5>) must be set. To reset or reconﬁgure SPI mode, clear bit SSPEN, re-initialize the SSPCON register, and then set bit SSPEN. This conﬁgures the SDI, SDO, SCK, and SS

pins as serial port pins. For the pins to behave as the serial port function, they must have their data direction bits (in the TRISC register) appropriately programmed. That is:

• SDI must have TRISC<4> set

• SDO must have TRISC<5> cleared

• SCK (Master mode) must have TRISC<3>

cleared

• SCK (Slave mode) must have TRISC<3> set

• SS

must have TRISA<5> set

Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. An example would be in master mode where you are only sending data (to a display driver), then both SDI and SS

could be used as general purpose outputs by clearing their corresponding TRIS register bits.

Figure 11-4 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their programmed clock edge, and latched on the opposite edge of the clock. Both processors should be programmed to same Clock Polarity (CKP), then both controllers would send and receive data at the same time. Whether the data is meaningful (or dummy data) depends on the application software. This leads to three scenarios for data transmission:

• Master sends data — Slave sends dummy data

• Master sends data — Slave sends data

• Master sends dummy data — Slave sends data

The master can initiate the data transfer at any time because it controls the SCK. The master deter mines when the slave (Processor 2) is to broadcast data by the ﬁrmware protocol.

In master mode the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is only going to receive, the SCK output could be disabled (programmed as an input). The SSPSR register will continue to shift in the signal present on the SDI pin at the programmed clock rate. As each byte is received, it will be loaded into the SSPBUF register as if a normal received byte (interrupts and status bits appropriately set). This could be useful in receiver applications as a “line activity monitor” mode.

In slave mode, the data is transmitted and received as the external clock pulses appear on SCK. When the last bit is latched the interrupt ﬂag bit SSPIF (PIR1<3>) is set.

The clock polarity is selected by appropriately programming bit CKP (SSPCON<4>). This then would give waveforms for SPI communication as shown in Figure 11-5, Figure 11-6, and Figure 11-7 where the MSB is transmitted ﬁrst. In master mode, the SPI clock rate (bit rate) is user programmable to be one of the f ollowing:

• F

OSC/4 (or TCY)

• F

OSC/16 (or 4 • TCY)

• F

OSC/64 (or 16 • TCY)

• Timer2 output/2 This allows a maximum bit clock frequency (at 8 MHz)

of 2 MHz. When in slave mode the external clock must meet the minimum high and low times.

In sleep mode, the slave can transmit and receive data and wake the device from sleep.

FIGURE 11-4: SPI MASTER/SLAVE CONNECTION

Serial Input Buffer

(SSPBUF)

Shift Register

(SSPSR)

MSb

LSb

SDO

SDI

PROCESSOR 1

SCK

SPI Master SSPM3:SSPM0 = 00xxb

Serial Input Buffer

(SSPBUF)

Shift Register

(SSPSR)

LSb

MSb

SDI

SDO

PROCESSOR 2

SCK

SPI Slave SSPM3:SSPM0 = 010xb

Serial Clock

 1997 Microchip Technology Inc. DS30444E - page 67

PIC16C9XX

The SS pin allows a synchronous slave mode. The SPI must be in slave mode (SSPCON<3:0> = 04h) and the TRISA<5> bit must be set for the synchronous slave mode to be enabled. When the SS

pin is low, tr ansmission and reception are enabled and the SDO pin is driven. When the SS

pin goes high, the SDO pin is no longer driven, even if in the middle of a transmitted byte, and becomes a ﬂoating output. External pull-up/ pull-down resistors may be desirable, depending on the application.

To emulate two-wire communication, the SDO pin can be connected to the SDI pin. When the SPI needs to operate as a receiver the SDO pin can be conﬁgured as an input. This disables transmissions from the SDO. The SDI can always be left as an input (SDI function) since it cannot create a bus conﬂict.

Note: When the SPI is in Slave Mode with SS pin

control enabled, (SSPCON<3:0> = 0100) the SPI module will reset if the SS

pin is set

to V

DD.

Note: If the SPI is used in Slave Mode with

CKE = '1', then the SS

pin control must be

enabled.

FIGURE 11-5: SPI MODE TIMING, MASTER MODE

FIGURE 11-6: SPI MODE TIMING (SLAVE MODE WITH CKE = 0)

SCK (CKP = 0,

SDI (SMP = 0)

SSPIF

bit7 bit6 bit5

bit4

bit3

bit2

bit1 bit0

SDI (SMP = 1)

SCK (CKP = 0,

SCK (CKP = 1,

SDO

bit7

bit7 bit0

bit0

CKE = 0)

CKE = 1)

CKE = 0)

CKE = 1)

SCK (CKP = 0)

SDI (SMP = 0)

SSPIF

bit7 bit6 bit5

bit4

bit3

bit2

bit1 bit0

SCK (CKP = 1)

SDO

bit7 bit0

SS (optional)

PIC16C9XX

DS30444E - page 68  1997 Microchip Technology Inc.

FIGURE 11-7: SPI MODE TIMING (SLAVE MODE WITH CKE = 1)

TABLE 11-1: REGISTERS ASSOCIATED WITH SPI OPERATION

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

Power-on

Reset

Value on all other resets

0Bh, 8Bh, 10Bh, 18Bh

INTCON GIE PEIE

T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1

LCDIF ADIF

(1)

— — SSPIF CCP1IF TMR2IF TMR1IF 00-- 0000 00-- 0000

8Ch PIE1 LCDIE ADIE

(1)

— — SSPIE CCP1IE TMR2IE TMR1IE 00-- 0000 00-- 0000 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 85h TRISA — — PORTA Data Direction Control Register --11 1111 --11 1111 87h TRISC — — PORTC Data Direction Control Register --11 1111 --11 1111 94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000

Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the SSP in SPI mode. Note 1: Bits ADIE and ADIF are reserved on the PIC16C923, always maintain these bits clear.

SCK (CKP = 0)

SDI (SMP = 0)

SSPIF

bit7

bit6 bit5

bit4

bit3

bit2

bit1 bit0

SCK (CKP = 1)

SDO

bit7 bit0

SS (not optional)

 1997 Microchip Technology Inc. DS30444E - page 69

PIC16C9XX

11.2 I2C Overview

This section provides an overview of the Inter-Integrated Circuit (I

C) bus, with Section 11.3 discussing

the operation of the SSP module in I

C mode.

The I

C bus is a two-wire serial interface de v eloped by the Philips Corporation. The original speciﬁcation, or standard mode, was for data transfers of up to 100 Kbps. An enhanced speciﬁcation, or fast mode is not supported. This device will communicate with fast mode devices if attached to the same bus.

The I

C interface employs a comprehensiv e protocol to ensure reliable transmission and reception of data. When transmitting data, one device is the “master” which initiates transfer on the bus and generates the clock signals to permit that transfer, while the other device(s) acts as the “slave.” All portions of the slave protocol are implemented in the SSP module’s hardware, except general call support, while portions of the master protocol need to be addressed in the PIC16CXXX software. Table 11-2 deﬁnes some of the I

C bus terminology. For additional information on the

C interface speciﬁcation, refer to the Philips docu-

ment “

The I2C bus and how to use it. ”

#939839340011,

which can be obtained from the Philips Corporation. In the I

C interface protocol each device has an address. When a master wishes to initiate a data transfer , it ﬁrst transmits the address of the device that it wishes to “talk” to. All devices “listen” to see if this is their address. Within this address, a bit speciﬁes if the master wishes to read-from/write-to the slave device. The master and slave are always in opposite modes (transmitter/receiver) of operation during a data transfer. That is they can be thought of as operating in either of these two relations:

• Master-transmitter and Slave-receiver

• Slave-transmitter and Master-receiver In both cases the master generates the clock signal.

The output stages of the clock (SCL) and data (SDA) lines must have an open-drain or open-collector in order to perform the wired-AND function of the bus. External pull-up resistors are used to ensure a high level when no de vice is pulling the line do wn. The number of devices that may be attached to the I

C bus is limited only by the maximum bus loading speciﬁcation of 400 pF.

11.2.1 INITIATING AND TERMINATING DATA

TRANSFER

During times of no data transfer (idle time), both the clock line (SCL) and the data line (SDA) are pulled high through the external pull-up resistors. The START and STOP conditions determine the start and stop of data transmission. The ST ART condition is deﬁned as a high to low transition of the SDA when the SCL is high. The STOP condition is deﬁned as a low to high transition of the SDA when the SCL is high. Figure 11-8 shows the START and STOP conditions. The master generates these conditions for starting and terminating data transfer . Due to the deﬁnition of the START and STOP conditions, when data is being transmitted, the SDA line can only change state when the SCL line is low.

FIGURE 11-8: START AND STOP

CONDITIONS

SDA

SCL

Start

Condition

Change

of Data

Allowed

Change

of Data

Allowed

Stop

Condition

TABLE 11-2: I2C BUS TERMINOLOGY

Term Description

Transmitter The device that sends the data to the bus. Receiver The device that receives the data from the bus. Master The device which initiates the transfer, generates the clock and terminates the transfer. Slave The device addressed by a master. Multi-master More than one master device in a system. These masters can attempt to control the bus at the

same time without corrupting the message.

Arbitration Procedure that ensures that only one of the master devices will control the bus. This ensure that

the transfer data does not get corrupted.

Synchronization Procedure where the clock signals of two or more devices are synchronized.

PIC16C9XX

DS30444E - page 70  1997 Microchip Technology Inc.

11.2.2 ADDRESSING I2C DEVICES There are two address formats. The simplest is the 7-bit

address format with a R/W

bit (Figure 11-9). The more

complex is the 10-bit address with a R/W

bit (Figure 11-10). For 10-bit address format, two bytes must be transmitted with the ﬁrst ﬁve bits specifying this to be a 10-bit address.

FIGURE 11-9: 7-BIT ADDRESS FORMAT

FIGURE 11-10: I

C 10-BIT ADDRESS

FORMAT

11.2.3 TRANSFER ACKNOWLEDGE All data must be transmitted per byte, with no limit to the

number of bytes transmitted per data transfer. After each byte, the slave-receiver generates an acknowledge bit (A

CK) (Figure 11-11). When a slave-receiver doesn’t acknowledge the slave address or received data, the master must abort the transfer. The slave must leave SDA high so that the master can generate the STOP condition (Figure 11-8).

R/W

ACK

Sent by

Slave

slave address

S R/W

Read/Write pulse

MSb LSb

Start Condition

ACK

Acknowledge

S 1 1 1 1 0 A9 A8 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK

sent by slave = 0 for write

S R/W ACK

- Start Condition

- Read/Write Pulse

- Acknowledge

FIGURE 11-11: SLAVE-RECEIVER

ACKNOWLEDGE

If the master is receiving the data (master-receiver), it generates an acknowledge signal for each received byte of data, except for the last byte. To signal the end of data to the slave-transmitter, the master does not generate an acknowledge (not acknowledge). The slave then releases the SDA line so the master can generate the STOP condition. The master can also generate the STOP condition during the acknowledge pulse for valid termination of data transfer.

If the slave needs to delay the transmission of the next byte, holding the SCL line low will f orce the master into a wait state. Data transfer continues when the slave releases the SCL line. This allo ws the slave to mo ve the received data or fetch the data it needs to transfer before allowing the clock to start. This wait state technique can also be implemented at the bit level, Figure 11-12. The slave will inherently stretch the cloc k, when it is a transmitter, b ut will not when it is a receiver . The slave will have to clear the SSPCON<4> bit to enable clock stretching when it is a receiver.

Data

Output by

Transmitter

Data

Output by

Receiver

SCL from

Master

Start

Condition

Clock Pulse for

Acknowledgment

not acknowledge

acknowledge

FIGURE 11-12: DATA TRANSFER WAIT STATE

1 2 7 8 9 1 2 3 • 8 9

SDA

SCL

Start

Condition

Address R/W

ACK Wait

State

Data ACK

MSB acknowledgment

signal from receiver

acknowledgment signal from receiver

byte complete interrupt with receiver

clock line held low while interrupts are serviced

Stop

Condition

 1997 Microchip Technology Inc. DS30444E - page 71

PIC16C9XX

Figure 11-13 and Figure 11-14 show Master-transmitter and Master-receiver data transfer sequences.

When a master does not wish to relinquish the bus (by generating a STOP condition), a repeated START condition (Sr) must be generated. This condition is identical to the start condition (SDA goes high-to-low while SCL

is high), but occurs after a data transfer acknowledge pulse (not the bus-free state). This allows a master to send “commands” to the slave and then receive the requested information or to address a different slave device. This sequence is shown in Figure 11-15.

FIGURE 11-13: MASTER-TRANSMITTER SEQUENCE

FIGURE 11-14: MASTER-RECEIVER SEQUENCE

FIGURE 11-15: COMBINED FORMAT

For 7-bit address:

Slave Address

First 7 bits

S R/W

A1Slave Address

Second byte

Data A Data P

A master transmitter addresses a slave receiver with a 10-bit address.

A/A

Slave AddressR/W A Data A Data A/A P

'0' (write) data transferred

(n bytes - acknowledge)

A master transmitter addresses a slave receiver with a 7-bit address. The transfer direction is not changed.

From master to slave

From slave to master

A = acknowledge (SDA low) A

= not acknowledge (SDA high) S = Start Condition P = Stop Condition

(write)

For 10-bit address:

For 7-bit address:

Slave Address

First 7 bits

S R/W

A1Slave Address

Second byte

A master transmitter addresses a slave receiver with a 10-bit address.

Slave AddressR/W

A Data A Data A P

'1' (read) data transferred

(n bytes - acknowledge)

A master reads a slave immediately after the ﬁrst byte.

From master to slave

From slave to master

A = acknowledge (SDA low) A

= not acknowledge (SDA high) S = Start Condition P = Stop Condition

(write)

For 10-bit address:

Slave Address

First 7 bits

Sr R/W A3 AData A PData

(read)

Combined format:

Combined format - A master addresses a slave with a 10-bit address, then transmits

Slave AddressR/W A Data A/A Sr P

(read) Sr = repeated

Transfer direction of data and acknowledgment bits depends on R/W

bits.

From master to slave From slave to master

A = acknowledge (SDA low) A

= not acknowledge (SDA high) S = Start Condition P = Stop Condition

Slave Address

First 7 bits

Sr R/W A

(write)

data to this slave and reads data from this slave.

Slave Address

Second byte

Data Sr Slave Address

First 7 bits

R/W

A Data A A PA A Data A/A Data

(read)

Slave Address R/W

A Data A/A

Start Condition

(write) Direction of transfer

may change at this point

(read or write)

(n bytes + acknowledge)

PIC16C9XX

DS30444E - page 72  1997 Microchip Technology Inc.

11.2.4 MULTI-MASTER The I

C protocol allows a system to have more than one master. This is called multi-master. When two or more masters try to transfer data at the same time, arbitration and synchronization occur.

11.2.4.1 ARBITRATION Arbitration takes place on the SDA line, while the SCL

line is high. The master which transmits a high when the other master transmits a low loses arbitration (Figure 11-16), and turns off its data output stage. A master which lost arbitration can generate clock pulses until the end of the data byte where it lost arbitration. When the master devices are addressing the same device, arbitration continues into the data.

FIGURE 11-16: MULTI-MASTER

ARBITRATION (TWO MASTERS)

Masters that also incorporate the slave function, and have lost arbitration must immediately switch over to slave-receiver mode . This is because the winning master-transmitter may be addressing it.

Arbitration is not allowed between:

• A repeated START condition

• A STOP condition and a data bit

• A repeated START condition and a STOP condi-

tion

Care needs to be taken to ensure that these conditions do not occur.

transmitter 1 loses arbitration

DATA 1 SDA

DATA 1

DATA 2

SDA

SCL

11.2.4.2 Clock Synchronization Clock synchronization occurs after the devices have

started arbitration. This is performed using a wired-AND connection to the SCL line. A high to low transition on the SCL line causes the concerned devices to start counting off their low period. Once a device clock has gone low, it will hold the SCL line low until its SCL high state is reached. The lo w to high transition of this clock may not change the state of the SCL line, if another device clock is still within its low period. The SCL line is held low by the device with the longest low period. Devices with shorter low periods enter a high wait-state, until the SCL line comes high. When the SCL line comes high, all devices start counting off their high periods. The ﬁrst device to complete its high period will pull the SCL line low. The SCL line high time is determined by the device with the shortest high period, Figure 11-17.

FIGURE 11-17: CLOCK SYNCHRONIZATION

CLK

SCL

wait

state

start counting

HIGH period

counter

reset

 1997 Microchip Technology Inc. DS30444E - page 73

PIC16C9XX

11.3 SSP I2C Operation

The SSP module in I2C mode fully implements all slave functions, except general call support, and provides interrupts on start and stop bits in hardware to facilitate ﬁrmware implementations of the master functions. The SSP module implements the standard mode speciﬁcations as well as 7-bit and 10-bit addressing. Two pins are used for data transfer . These are the RC3/SCK/SCL pin, which is the clock (SCL), and the RC4/SDI/SDA pin, which is the data (SDA). The user must conﬁgure these pins as inputs or outputs through the TRISC<4:3> bits. The SSP module functions are enabled by setting SSP Enable bit SSPEN (SSPCON<5>).

FIGURE 11-18: SSP BLOCK DIAGRAM

(I2C MODE)

The SSP module has ﬁve registers for I2C operation. These are the:

• SSP Control Register (SSPCON)

• SSP Status Register (SSPSTAT)

• Serial Receive/Transmit Buffer (SSPBUF)

• SSP Shift Register (SSPSR) - Not directly accessible

• SSP Address Register (SSPADD)

Read Write

SSPSR reg

Match detect

SSPADD reg

Start and

Stop bit detect

SSPBUF reg

Internal

data bus

Addr Match

Set, Reset S, P bits

(SSPSTAT reg)

RC3/SCK/SCL

RC4/

shift

clock

MSb

SDI/

LSb

SDA

The SSPCON register allows control of the I2C operation. Four mode selection bits (SSPCON<3:0>) allow one of the following I

C modes to be selected:

• I

C Slave mode (7-bit address)

• I

C Slave mode (10-bit address)

• I

C Slave mode (7-bit address), with start and

stop bit interrupts enabled

• I

C Slave mode (10-bit address), with start and

stop bit interrupts enabled

• I

C Firmware controlled Master Mode, slave is

idle

Selection of any I

C mode, with the SSPEN bit set, forces the SCL and SDA pins to be open drain, provided these pins are programmed to inputs by setting the appropriate TRISC bits.

The SSPSTAT register gives the status of the data transfer. This information includes detection of a ST ART or STOP bit, speciﬁes if the received byte was data or address if the next byte is the completion of 10-bit address, and if this will be a read or write data transfer. The SSPSTAT register is read only.

The SSPBUF is the register to which transfer data is written to or read from. The SSPSR register shifts the data in or out of the device. In receive operations, the SSPBUF and SSPSR create a doubled buffered receiver. This allows reception of the next byte to begin before reading the last byte of receiv ed data. When the complete byte is received, it is transferred to the SSPBUF register and ﬂag bit SSPIF is set. If another complete byte is received before the SSPBUF register is read, a receiver overﬂow has occurred and bit SSPOV (SSPCON<6>) is set and the byte in the SSPSR is lost.

The SSPADD register holds the slave address. In 10-bit mode, the user needs to write the high byte of the address (1111 0 A9 A8 0). Following the high byte address match, the low byte of the address needs to be loaded (A7:A0).

PIC16C9XX

DS30444E - page 74  1997 Microchip Technology Inc.

11.3.1 SLAVE MODE In slave mode, the SCL and SDA pins must be conﬁg-

ured as inputs (TRISC<4:3> set). The SSP module will override the input state with the output data when required (slave-transmitter).

When an address is matched or the data transfer after an address match is received, the hardware automatically will generate the acknowledge (A

CK) pulse, and then load the SSPBUF register with the received value currently in the SSPSR register.

There are certain conditions that will cause the SSP module not to give this A

CK pulse. These are if either

(or both): a) The buffer full bit BF (SSPSTAT<0>) was set

before the transfer was received.

b) The overﬂow bit SSPOV (SSPCON<6>) was set

before the transfer was received.

In this case, the SSPSR register value is not loaded into the SSPBUF, but bit SSPIF (PIR1<3>) is set. Table 11-3 shows what happens when a data transfer byte is received, given the status of bits BF and SSPOV. The shaded cells show the condition where user software did not properly clear the overﬂow condition. Flag bit BF is cleared by reading the SSPBUF register while bit SSPOV is cleared through software.

The SCL clock input must have a minimum high and low time for proper operation. The high and lo w times of the I

C speciﬁcation as well as the requirement of the SSP module is shown in timing parameter #100 and parameter #101.

11.3.1.1 ADDRESSING Once the SSP module has been enabled, it waits for a

START condition to occur. Following the START condition, the 8-bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock (SCL) line. The value of register SSPSR<7:1> is compared to the value of the SSPADD register. The

address is compared on the falling edge of the eighth clock (SCL) pulse. If the addresses match, and the BF and SSPOV bits are clear, the following events occur:

a) The SSPSR register value is loaded into the

SSPBUF register. b) The buffer full bit, BF is set. c) An A

CK pulse is generated.

d) SSP interrupt ﬂag bit, SSPIF (PIR1<3>) is set

(interrupt is generated if enabled) - on the falling

edge of the ninth SCL pulse. In 10-bit address mode, two address bytes need to be

received by the slav e (Figure 11-10). The ﬁv e Most Signiﬁcant bits (MSbs) of the ﬁrst address byte specify if this is a 10-bit address. Bit R/W

(SSPSTAT<2>) must specify a write so the slave device will receive the second address byte. For a 10-bit address the ﬁrst byte would equal ‘1111 0 A9 A8 0’, where A9 and A8 are the two MSbs of the address. The sequence of events for a 10-bit address is as follows, with steps 7- 9 for slave-transmitter:

1. Receive ﬁrst (high) byte of Address (bits SSPIF,

BF, and bit UA (SSPSTAT<1>) are set).

2. Update the SSPADD register with second (low)

byte of Address (clears bit UA and releases the SCL line).

3. Read the SSPBUF register (clears bit BF) and

clear ﬂag bit SSPIF.

4. Receive second (low) byte of Address (bits

SSPIF, BF, and UA are set).

5. Update the SSPADD register with the ﬁrst (high)

byte of Address, if match releases SCL line, this will clear bit UA.

6. Read the SSPBUF register (clears bit BF) and

clear ﬂag bit SSPIF.

7. Receive repeated START condition.

8. Receive ﬁrst (high) byte of Address (bits SSPIF

and BF are set).

9. Read the SSPBUF register (clears bit BF) and

clear ﬂag bit SSPIF.

TABLE 11-3: DATA TRANSFER RECEIVED BYTE ACTIONS

Status Bits as Data

Transfer is Received

SSPSR

→ SSPBUF

Generate A

Pulse

Set bit SSPIF

(SSP Interrupt occurs

if enabled)

BF SSPOV

0 0 Yes Yes Yes 1 0 No No Yes 1 1 No No Yes 0 1 No No Yes

 1997 Microchip Technology Inc. DS30444E - page 75

PIC16C9XX

11.3.1.2 RECEPTION When the R/W

bit of the address byte is clear and an

address match occurs, the R/W

bit of the SSPST AT register is cleared. The receiv ed address is loaded into the SSPBUF register.

When the address byte overﬂow condition exists, then no acknowledge (A

CK) pulse is given. An ov erﬂow condition is deﬁned as either bit BF (SSPSTAT<0>) is set or bit SSPOV (SSPCON<6>) is set.

An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF (PIR1<3>) must be cleared in software. The SSPSTAT register is used to determine the status of the byte.

FIGURE 11-19: I2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)

D3D4

D6D7

A7 A6 A5 A4

A3 A2 A1SDA

SCL

1 2

5 6

8 9

1 2 3

Bus Master terminates transfer

Bit SSPOV is set because the SSPBUF register is still full.

Cleared in software

SSPBUF register is read

Receiving Data

D3D4

D6D7

R/W=0

Receiving Address

SSPIF (PIR1<3>)

BF (SSPSTAT<0>)

SSPOV (SSPCON<6>)

ACK

ACK is not sent.

PIC16C9XX

DS30444E - page 76  1997 Microchip Technology Inc.

11.3.1.3 TRANSMISSION When the R/W

bit of the incoming address byte is set

and an address match occurs, the R/W

bit of the SSPSTAT register is set. The received address is loaded into the SSPBUF register. The A

CK pulse will be sent on the ninth bit, and pin RC3/SCK/SCL is held low . The transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register . Then pin RC3/SCK/SCL should be enabled by setting bit CKP (SSPCON<4>). The master must monitor the SCL pin prior to asserting another clock pulse. The slave devices may be holding off the master b y stretching the clock. The eight data bits are shifted out on the falling edge of the SCL input. This ensures that the SD A signal is valid during the SCL high time (Figure 11-20).

An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF must be cleared in software, and the SSPSTAT register is used to determine the status of the byte. Flag bit SSPIF is set on the f alling edge of the ninth clock pulse.

As a slave-transmitter, the A

CK pulse from the master-receiver is latched on the rising edge of the ninth SCL input pulse. If the SDA line was high (not A

CK),

then the data transfer is complete. When the A

CK is latched by the slave, the slave logic is reset and the slave then monitors for another occurrence of the START bit. If the SDA line was low (A

CK), the transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register. Then pin RC3/SCK/SCL should be enabled by setting bit CKP.

FIGURE 11-20: I2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)

SDA

SCL

SSPIF (PIR1<3>) BF (SSPSTAT<0>)

CKP (SSPCON<4>)

A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0

CKTransmitting DataR/W = 1Receiving Address

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

cleared in software

SSPBUF is written in software

From SSP interrupt

service routine

Set bit after writing to SSPBUF

Data in sampled

SCL held low while CPU

responds to SSPIF

(the SSPBUF must be written-to before the CKP bit can be set)

 1997 Microchip Technology Inc. DS30444E - page 77

PIC16C9XX

11.3.2 MASTER MODE Master mode of operation is supported, in ﬁrmware,

using interrupt generation on the detection of the START and STOP conditions. The STOP (P) and START (S) bits are cleared from a reset or when the SSP module is disabled. The ST OP and START bits will toggle based on the start and stop conditions. Control of the I

C bus may be taken when the P bit is set, or the

bus is idle with both the S and P bits clear. In master mode the SCL and SDA lines are manipu-

lated by clearing the corresponding TRISC<4:3> bit(s). The output level is always low, irrespective of the value(s) in PORTC<4:3>. So when transmitting data, a '1' data bit must have the TRISC<4> bit set (input) and a '0' data bit must have the TRISC<4> bit cleared (output). The same scenario is true for the SCL line with the TRISC<3> bit.

The following events will cause SSP Interr upt Flag bit, SSPIF, to be set (SSP Interrupt if enabled):

• START condition

• STOP condition

• Data transfer byte transmitted/received Master mode of operation can be done with either the

slave mode idle (SSPM3:SSPM0 = 1011) or with the slave active. When both master and slave modes are enabled, the software needs to differentiate the source(s) of the interrupt.

11.3.3 MULTI-MASTER MODE In multi-master mode, the interrupt generation on the

detection of the ST ART and ST OP conditions allows the determination of when the bus is free. The STOP (P) and START (S) bits are cleared from a reset or when the SSP module is disabled. The ST OP and START bits will toggle based on the start and stop conditions. Control of the I

C bus may be taken when bit P (SSPSTAT<4>) is set, or the bus is idle with both the S and P bits clear. When the bus is busy, enabling the SSP Interrupt will generate the interrupt when the STOP condition occurs.

In multi-master operation, the SDA line must be monitored to see if the signal level is the expected output level. This check only needs to be done when a high level is output. If a high le v el is expected and a lo w lev el is present, the device needs to release the SDA and SCL lines (set TRISC<4:3>). There are two stages where this arbitration can be lost, they are:

• Address Transfer

• Data Transfer When the slave logic is enabled, the sla ve continues to

receive. If arbitration was lost during the address transfer stage, communication to the device may be in progress. If addressed an A

CK pulse will be generated. If arbitration was lost during the data transfer stage, the device will need to re-transfer the data at a later time.

TABLE 11-4: REGISTERS ASSOCIATED WITH I2C OPERATION

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

Power-on

Reset

Value on all other resets

0Bh, 8Bh, 10Bh, 18Bh

INTCON GIE PEIE

T0IE INTE RBIE T0IF INTF RBIF

0000 000x 0000 000u

0Ch PIR1

LCDIF ADIF

(1)

— — SSPIF CCP1IF TMR2IF TMR1IF

00-- 0000 00-- 0000

8Ch PIE1

LCDIE ADIE

(1)

— — SSPIE CCP1IE TMR2IE TMR1IE

00-- 0000 00-- 0000

13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register

xxxx xxxx uuuu uuuu

93h SSPADD Synchronous Serial Port (I

C mode) Address Register

0000 0000 0000 0000

14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0

0000 0000 0000 0000

94h SSPSTAT SMP CKE D/A

P S R/W UA BF

0000 0000 0000 0000

87h TRISC

— — PORTC Data Direction Control Register

--11 1111 --11 1111

Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by SSP in I

C mode.

Note 1: Bits ADIE and ADIF are reserved on the PIC16C923, always maintain these bits clear.

PIC16C9XX

DS30444E - page 78  1997 Microchip Technology Inc.

FIGURE 11-21: OPERATION OF THE I2C MODULE IN IDLE_MODE, RCV_MODE OR XMIT_MODE

IDLE_MODE (7-bit): if (Addr_match) { Set interrupt;

if (R/W

= 1) { Send ACK = 0;

set XMIT_MODE; }

else if (R/W

= 0) set RCV_MODE;

}

RCV_MODE:

if ((SSPBUF=Full) OR (SSPOV = 1))

{ Set SSPOV;

Do not acknowledge;

}

else { transfer SSPSR → SSPBUF;

send A

CK = 0;

} Receive 8-bits in SSPSR; Set interrupt;

XMIT_MODE:

While ((SSPBUF = Empty) AND (CKP=0)) Hold SCL Low; Send byte; Set interrupt; if ( A

CK Received = 1) { End of transmission;

Go back to IDLE_MODE;

}

else if ( A

CK Received = 0) Go back to XMIT_MODE;

IDLE_MODE (10-Bit):

If (High_byte_addr_match AND (R/W

= 0))

{ PRIOR_ADDR_MATCH = FALSE;

Set interrupt; if ((SSPBUF = Full) OR ((SSPOV = 1))

{ Set SSPOV;

Do not acknowledge;

}

else { Set UA = 1;

Send A

CK = 0; While (SSPADD not updated) Hold SCL low; Clear UA = 0; Receive Low_addr_byte; Set interrupt; Set UA = 1; If (Low_byte_addr_match)

{ PRIOR_ADDR_MATCH = TRUE;

Send A

CK = 0; while (SSPADD not updated) Hold SCL low; Clear UA = 0;

Set RCV_MODE;

}

else if (High_byte_addr_match AND (R/W

= 1)

{ if (PRIOR_ADDR_MATCH)

{ send A

CK = 0;

set XMIT_MODE;

} else PRIOR_ADDR_MATCH = FALSE; }

 1997 Microchip Technology Inc. DS30444E - page 79

PIC16C9XX

FIGURE 12-1: ADCON0 REGISTER (ADDRESS 1Fh)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE

— ADON R =Readable bit

W =Writable bit U =Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7-6: ADCS1:ADCS0: A/D Conversion Clock Select bits

00 = F

OSC/2

01 = F

OSC/8

10 = F

OSC/32

11 = F

RC (clock derived from an RC oscillation)

bit 5-3: CHS2:CHS0: Analog Channel Select bits

000 = channel 0, (RA0/AN0) 001 = channel 1, (RA1/AN1) 010 = channel 2, (RA2/AN2) 011 = channel 3, (RA3/AN3) 100 = channel 4, (RA5/AN4)

bit 2: GO/DONE

: A/D Conversion Status bit

If ADON = 1 1 = A/D conversion in progress (setting this bit starts the A/D conversion) 0 = A/D conversion not in progress (This bit is automatically cleared b y hardware when the A/D conversion

is complete) bit 1: Reserved: Always maintain this bit clear bit 0: ADON: A/D On bit

1 = A/D converter module is operating

0 = A/D converter module is shutoff and consumes no operating current

12.0 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE

This section applies to the PIC16C924 only.

The analog-to-digital (A/D) converter module has ﬁve inputs.

The A/D allows conversion of an analog input signal to a corresponding 8-bit digital number (refer to Application Note AN546 for use of A/D Converter). The output of the sample and hold is the input into the converter, which generates the result via successive approximation. The analog reference voltage is software selectable to either the device’s A

VDD pin or the voltage lev el

on the RA3/AN3/V

REF pin. The A/D converter has a

unique feature of being able to operate while the de vice is in SLEEP mode.

To operate in sleep, the A/D conversion clock must be derived from the A/D’s internal RC oscillator.

The A/D module has three registers. These registers are:

• A/D Result Register (ADRES)

• A/D Control Register 0 (ADCON0)

• A/D Control Register 1 (ADCON1)

The ADCON0 register, shown in Figure 12-1, controls the operation of the A/D module. The ADCON1 register, shown in Figure 12-2, conﬁgures the functions of the port pins. The port pins can be conﬁgured as analog inputs (RA3 can also be a voltage reference) or as digital I/O.

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DS30444E - page 80  1997 Microchip Technology Inc.

FIGURE 12-2: ADCON1 REGISTER (ADDRESS 9Fh)

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — PCFG2 PCFG1 PCFG0 R =Readable bit

W =Writable bit U =Unimplemented

bit, read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7-3: Unimplemented: Read as '0' bit 2-0: PCFG2:PCFG0: A/D Port Conﬁguration Control bits

A = Analog input D = Digital I/O

PCFG2:PCFG0 RA0 RA1 RA2 RA5 RA3 V

REF

000 A A A A A AVDD 001 A A A A VREF RA3 010 A A A A A A

VDD

011 A A A A VREF RA3 100 A A D D A A

VDD

111 D D D D D —

The ADRES register contains the result of the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRES register, the GO/DONE bit (ADCON0<2>) is cleared, and A/D interrupt ﬂag bit ADIF is set. The block diagram of the A/D module is shown in Figure 12-3.

After the A/D module has been conﬁgured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as an input. To determine acquisition time, see Section 12.1. After this acquisition time has elapsed the A/D conversion can be started. The following steps should be followed for doing an A/D conversion:

1. Conﬁgure the A/D module:

• Conﬁgure analog pins / voltage reference /

and digital I/O (ADCON1)

• Select A/D input channel (ADCON0)

• Select A/D conversion clock (ADCON0)

• Turn on A/D module (ADCON0)

2. Conﬁgure A/D interrupt (if desired):

• Clear ADIF bit

• Set ADIE bit

• Set GIE bit

3. Wait the required acquisition time.

4. Start conversion:

• Set GO/DONE

bit (ADCON0)

5. Wait for A/D conversion to complete, by either:

• Polling for the GO/DONE

bit to be cleared

• Waiting for the A/D interrupt

6. Read A/D Result register (ADRES), clear bit ADIF if required.

7. For next conversion, go to step 1 or step 2 as required. The A/D conversion time per bit is deﬁned as T

AD. A minimum wait of 2TAD is

required before next acquisition starts.

 1997 Microchip Technology Inc. DS30444E - page 81

PIC16C9XX

FIGURE 12-3: A/D BLOCK DIAGRAM

(Input voltage)

VAIN

VREF

(Reference

voltage)

VDD

PCFG2:PCFG0

CHS2:CHS0

000 or 010 or 100

001 or 011

RA5/AN4

RA3/AN3/V

REF

RA2/AN2

RA1/AN1

RA0/AN0

100

011

010

001

000

A/D

Converter

PIC16C9XX

DS30444E - page 82  1997 Microchip Technology Inc.

12.1 A/D Acquisition Requirements

For the A/D converter to meet its speciﬁed accuracy, the charge holding capacitor (C

HOLD) must be allowed

to fully charge to the input channel voltage level. The analog input model is shown in Figure 12-4. The source impedance (R

S) and the internal sampling switch (RSS)

impedance directly affect the time required to charge the capacitor C

HOLD. The sampling s witch (RSS) imped-

ance varies over the device voltage (V

DD),

(Figure 12-4). The source impedance affects the offset voltage at the analog input (due to pin leakage current).

The maximum recommended impedance for analog sources is 10 kΩ . After the analog input channel is

selected (changed) this acquisition must be done before the conversion can be started.

To calculate the minimum acquisition time, Equation 12-1 may be used. This equation calculates the acquisition time to within 1/2 LSb error (512 steps for the A/D). The 1/2 LSb error is the maximum error allowed for the A/D to meet its speciﬁed accuracy.

EQUATION 12-1: A/D MINIMUM CHARGING

TIME

VHOLD = (VREF - (VREF/512)) • (1 - e

(-Tc/CHOLD(RIC + RSS + RS))

) Given: VHOLD = (VREF/512), for 1/2 LSb resolution The above equation reduces to: TC = -(51.2 pF)(1 kΩ - RSS + RS) ln(1/511)

Example 12-1 shows the calculation of the minimum required acquisition time (T

ACQ). This calculation is

based on the following system assumptions.

CHOLD = 51.2 pF

Rs = 10 k

Ω

1/2 LSb error V

DD = 5V → Rss = 7 kΩ

Temp (system max.) = 50°C V

HOLD = 0 @ t = 0

EXAMPLE 12-1: CALCULATING THE

MINIMUM REQUIRED SAMPLE TIME

TACQ = Ampliﬁer Settling Time +

Holding Capacitor Charging Time + Temperature Coefﬁcient

ACQ = 5 µs + Tc + [(Temp - 25°C)(0.05 µs/°C)]

C = -CHOLD (RIC + RSS + RS) ln(1/511)

-51.2 pF (1 kΩ + 7 kΩ + 10 kΩ) ln(0.0020)

-51.2 pF (18 kΩ) ln(0.0020)

-0.921 µs (-6.2364)

5.747 µs

ACQ = 5 µs + 5.747 µs + [(50°C - 25°C)(0.05 µs/°C)]

10.747 µs + 1.25 µs

11.997 µs

Note 1: The reference voltage (VREF) has no

effect on the equation, since it cancels itself out.

Note 2: The charge holding capacitor (C

HOLD) is

not discharged after each conversion.

Note 3: The maximum recommended impedance

for analog sources is 10 kΩ. This is required to meet the pin leakage speciﬁcation.

Note 4: After a conversion has completed, a

2.0 T

AD delay must complete before

acquisition can begin again. During this time the holding capacitor is not connected to the selected A/D input channel.

FIGURE 12-4: ANALOG INPUT MODEL

CPIN

RAx

5 pF

VT = 0.6V

T = 0.6V

I leakage

IC ≤ 1k

Sampling Switch

CHOLD = DAC capacitance

Sampling Switch

5V 4V 3V 2V

5 6 7 8 9 10 11

( kΩ )

VDD

= 51.2 pF

± 500 nA

Legend CPIN

VT I leakage

SS C

HOLD

= input capacitance = threshold voltage

= leakage current at the pin due to

= interconnect resistance = sampling switch = sample/hold capacitance (from DAC)

various junctions

 1997 Microchip Technology Inc. DS30444E - page 83

PIC16C9XX

12.2 Selecting the A/D Conversion Clock

The A/D conversion time per bit is deﬁned as TAD. The A/D conversion requires 9.5 T

AD per 8-bit conversion.

The source of the A/D conversion clock is software selected. The four possible options for T

AD are:

• 2T

OSC

• 8TOSC

• 32TOSC

• Internal RC oscillator

For correct A/D conversions, the A/D conversion clock (T

AD) must be selected to ensure a minimum TAD time

of 1.6 µs. Table 12-1 shows the resultant T

AD times derived from

the device operating frequencies and the A/D clock source selected.

12.3 Conﬁguring Analog Port Pins

The ADCON1 and TRISA registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital output level (V

OH or VOL) will be converted.

The A/D operation is independent of the state of the CHS2:CHS0 bits and the TRIS bits.

Note 1: When reading the port register, all pins

conﬁgured as analog inputs will read as cleared (a low level). Pins conﬁgured as digital inputs, will convert an analog input. Analog levels on a digitally conﬁgured input will not affect the conversion accuracy.

Note 2: Analog levels on any pin that is deﬁned as

a digital input (including the AN4:AN0 pins), may cause the input buffer to consume current that is out of the devices speciﬁcation.

TABLE 12-1: TAD vs. DEVICE OPERATING FREQUENCIES

A/D Clock Source (TAD) Device Frequency

Operation ADCS1:ADCS0 8 MHz 5 MHz 1.25 MHz 333.33 kHz

OSC 00 250 ns

(2)

400 ns

(2)

1.6 µs 6 µs

OSC 01 1 µs 1.6 µs 6.4 µs 24 µs

(3)

32TOSC 10 4 µs 6.4 µs 25.6 µs

(3)

96 µs

(3)

RC 11 2 - 6 µs

(1,4)

2 - 6 µs

(1,4)

2 - 6 µs

(1,4)

2 - 6 µs

(1)

Legend: Shaded cells are outside of recommended range. Note 1: The RC source has a typical T

AD time of 4 µs.

2: These values violate the minimum required T

AD time.

3: For faster conversion times, the selection of another clock source is recommended. 4: When derived frequency is greater than 1 MHz, the RC A/D conversion clock source is recommended for

sleep mode only

5: For extended voltage devices (LC), please refer to the electrical speciﬁcations section.

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DS30444E - page 84  1997 Microchip Technology Inc.

12.4 A/D Conversions

Example 12-2 show how to perform an A/D conv ersion. The RA pins are conﬁgured as analog inputs. The analog reference (V

REF) is the device VDD. The A/D inter-

rupt is enabled, and the A/D conversion clock is F

RC.

The conversion is performed on the RA0 pin (channel0).

Note: The GO/DONE bit should NOT be set in

the same instruction that turns on the A/D.

Clearing the GO/DONE bit during a conversion will abort the current conversion. The ADRES register will NOT be updated with the partially completed A/D conversion sample. That is, the ADRES register will continue to contain the value of the last completed conversion (or the last value written to the ADRES register). After the A/D conversion is aborted, a 2T

AD wait

is required before the next acquisition is started. After this 2T

AD wait, an acquisition is automatically started on

the selected channel.

EXAMPLE 12-2: DOING AN A/D CONVERSION

BCF STATUS, RP1 ; Select Bank1 BSF STATUS, RP0 ; CLRF ADCON1 ; Configure A/D inputs BSF PIE1, ADIE ; Enable A/D interrupts BCF STATUS, RP0 ; Select Bank0 MOVLW 0xC1 ; RC Clock, A/D is on, Channel 0 is selected MOVWF ADCON0 ; BCF PIR1, ADIF ; Clear A/D interrupt flag bit BSF INTCON, PEIE ; Enable peripheral interrupts BSF INTCON, GIE ; Enable all interrupts ; ; Ensure that the required acquisition time for the selected input channel has elapsed. ; Then the conversion may be started. ; BSF ADCON0, GO ; Start A/D Conversion : ; The ADIF bit will be set and the GO/DONE bit : ; is cleared upon completion of the A/D Conversion.

 1997 Microchip Technology Inc. DS30444E - page 85

PIC16C9XX

12.4.1 FASTER CONVERSION - LOWER RESOLUTION TRADE-OFF

Not all applications require a result with 8-bits of resolution, but may instead require a f aster conversion time . The A/D module allows users to make the trade-off of conversion speed to resolution. Regardless of the resolution required, the acquisition time is the same. To speed up the conversion, the clock source of the A/D module may be switched so that the T

AD time violates

the minimum speciﬁed time (see the applicable electrical speciﬁcation). Once the T

AD time violates the mini-

mum speciﬁed time, all the following A/D result bits are not valid (see A/D Conversion Timing in the Electrical Speciﬁcations section.) The clock sources may only be switched between the three oscillator versions (cannot be switched from/to RC). The equation to determine the time before the oscillator can be switched is as follows:

Conversion time = 2T

AD + N • TAD + (8 - N)(2TOSC)

Where: N = number of bits of resolution required.

Since the T

AD is based from the device oscillator, the

user must use some method (a timer, software loop, etc.) to determine when the A/D oscillator may be changed. Example 12-3 shows a comparison of time required for a conversion with 4-bits of resolution, versus the 8-bit resolution conversion. The example is for devices operating at 8 MHz (The A/D clock is programmed for 32T

OSC), and assumes that immediately

after 6T

AD, the A/D clock is programmed for 2TOSC.

The 2T

OSC violates the minimum TAD time, therefore

the last 4-bits will not be converted to correct values.

EXAMPLE 12-3: 4-BIT vs. 8-BIT CONVERSION TIMES

Freq. (MHz)

Resolution

4-bit 8-bit

TAD 8 1.6 µs 1.6 µs T

OSC 8 12.5 ns 125 ns

AD + N • TAD + (8 - N)(2TOSC) 8 10.6 µs 16 µs

PIC16C9XX

DS30444E - page 86  1997 Microchip Technology Inc.

12.5 A/D Operation During Sleep

The A/D module can operate during SLEEP mode. This requires that the A/D clock source be set to RC (ADCS1:ADCS0 = 11). When the RC clock source is selected, the A/D module waits one instruction cycle before starting the conversion. This allows the SLEEP instruction to be executed, which eliminates all digital switching noise from the conversion. When the conversion is completed the GO/DONE

bit will be cleared, and the result loaded into the ADRES register. If the A/D interrupt is enabled, the device will wake-up from SLEEP. If the A/D interrupt is not enabled, the A/D module will then be turned off, although the ADON bit will remain set.

When the A/D clock source is another clock option (not RC), a SLEEP instruction will cause the present conversion to be aborted and the A/D module to be turned off, though the ADON bit will remain set.

Turning off the A/D places the A/D module in its lowest current consumption state.

12.6 A/D Accuracy/Error

The absolute accuracy speciﬁed for the A/D converter includes the sum of all contributions for quantization error, integral error , diff erential error , full scale error, offset error, and monotonicity. It is deﬁned as the maximum deviation from an actual transition versus an ideal transition for any code. The absolute error of the A/D converter is speciﬁed at < ±1 LSb for V

DD = VREF (over

the device’s speciﬁed operating range). However, the accuracy of the A/D converter will degrade as V

diverges from VREF. For a given range of analog inputs, the output digital

code will be the same. This is due to the quantization of the analog input to a digital code. Quantization error is typically ± 1/2 LSb and is inherent in the analog to digital conversion process. The only way to reduce quantization error is to increase the resolution of the A/D converter.

Offset error measures the ﬁrst actual transition of a code versus the ﬁrst ideal transition of a code. Offset error shifts the entire transfer function. Offset error can be calibrated out of a system or introduced into a system through the interaction of the total leakage current and source impedance at the analog input.

Gain error measures the maximum deviation of the last actual transition and the last ideal transition adjusted for offset error. This error appears as a change in slope of the transfer function. The difference in gain error to full

Note: For the A/D module to operate in SLEEP,

the A/D clock source must be set to RC (ADCS1:ADCS0 = 11). To perform an A/D conversion in SLEEP, ensure the SLEEP instruction immediately follows the instruction that sets the GO/DONE

bit.

scale error is that full scale does not take offset error into account. Gain error can be calibrated out in software.

Linearity error refers to the uniformity of the code changes. Linearity errors cannot be calibrated out of the system. Integral non-linearity error measures the actual code transition versus the ideal code transition adjusted by the gain error for each code.

Differential non-linearity measures the maximum actual code width versus the ideal code width. This measure is unadjusted.

The maximum pin leakage current is ± 1 µA. In systems where the device frequency is low, use of

the A/D RC clock is preferred. At moderate to high frequencies, T

AD should be derived from the device oscil-

lator. T

AD must not violate the minimum and should be

≤ 8 µs for preferred operation. This is because T

AD,

when derived from T

OSC, is kept away from on-chip

phase clock transitions. This reduces, to a large extent, the effects of digital switching noise. This is not possible with the RC derived clock. The loss of accuracy due to digital switching noise can be signiﬁcant if many I/O pins are active.

In systems where the device will enter SLEEP mode after the start of the A/D conversion, the RC clock source selection is required. In this mode, the digital noise from the modules in SLEEP are stopped. This method gives high accuracy.

12.7 Effects of a RESET

A device reset forces all registers to their reset state. This forces the A/D module to be turned off, and any conversion is aborted.

The value that is in the ADRES register is not modiﬁed for a Power-on Reset. The ADRES register will contain unknown data after a Power-on Reset.

 1997 Microchip Technology Inc. DS30444E - page 87

PIC16C9XX

12.8 Use of the CCP Trigger

An A/D conversion can be started by the “special e v ent trigger” of the CCP1 module. This requires that the CCP1M3:CCP1M0 bits (CCP1CON<3:0>) be programmed as 1011 and that the A/D module is enabled (ADON bit is set). When the trigger occurs, the GO/DONE

bit will be set, starting the A/D conversion, and the Timer1 counter will be reset to zero. Timer1 is reset to automatically repeat the A/D acquisition period with minimal software overhead (moving the ADRES to the desired location). The appropriate analog input channel must be selected and the minimum acquisition done before the “special event trigger” sets the GO/DONE

bit (starts a conversion). If the A/D module is not enabled (ADON is cleared),

then the “special event trigger” will be ignored by the A/D module, but will still reset the Timer1 counter.

12.9 Connection Considerations

If the input voltage exceeds the rail v alues (VSS or VDD) by greater than 0.2V, then the accuracy of the conversion is out of speciﬁcation.

An external RC ﬁlter is sometimes added for anti-aliasing of the input signal. The R component should be selected to ensure that the total source impedance is kept under the 10 kΩ recommended speciﬁcation. Any external components connected (via hi-impedance) to an analog input pin (capacitor, zener diode , etc.) should have very little leakage current at the pin.

12.10 Transfer Function

The ideal transfer function of the A/D conv erter is as follows: the ﬁrst transition occurs when the analog input voltage (V

AIN) is Analog VREF / 256 (Figure 12-5).

FIGURE 12-5: A/D TRANSFER FUNCTION

Digital code output

FFh

FEh

04h 03h 02h 01h 00h

0.5 LSb

1 LSb

2 LSb

3 LSb

4 LSb

255 LSb

256 LSb

(full scale)

Analog input voltage

PIC16C9XX

DS30444E - page 88  1997 Microchip Technology Inc.

FIGURE 12-6: FLOWCHART OF A/D OPERATION

TABLE 12-2: SUMMARY OF A/D REGISTERS

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

Power-on

Reset

Value on all

other Resets

0Bh, 8Bh, 10Bh, 18Bh

INTCON GIE PEIE

T0IE INTE RBIE T0IF INTF RBIF

0000 000x 0000 000u

0Ch PIR1 LCDIF ADIF — — SSPIF CCP1IF TMR2IF TMR1IF

00-- 0000 00-- 0000

8Ch PIE1

LCDIE ADIE — — SSPIE CCP1IE TMR2IE TMR1IE

00-- 0000 00-- 0000

1Eh ADRES A/D Result Register

xxxx xxxx uuuu uuuu

1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE

(1)

ADON

0000 0000 0000 0000

9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0

---- -000 ---- -000

05h PORTA

— — RA5 RA4 RA3 RA2 RA1 RA0

--0x 0000 --0u 0000

85h TRISA

— — PORTA Data Direction Control Register

--11 1111 --11 1111

Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used for A/D conversion. Note 1: Bit1 of ADCON0 is reserved, always maintain this bit clear.

Acquire

ADON = 0

ADON = 0?

GO = 0?

A/D Clock

GO = 0

ADIF = 0

Abort Conversion

SLEEP

Power-down A/D

Wait 2 T

Wake-up

Yes

Finish Conversion

GO = 0

ADIF = 1

Device in

Yes

Finish Conversion

GO = 0

ADIF = 1

Wait 2 TAD

Stay in Sleep

Selected Channel

= RC?

SLEEP

Yes

Instruction?

Start of A/D

Conversion Delayed

1 Instruction Cycle

From Sleep?

Power-down A/D

Yes

Wait 2 TAD

Finish Conversion

GO = 0

ADIF = 1

SLEEP?

 1997 Microchip Technology Inc. DS30444E - page 89

PIC16C9XX

13.0 LCD MODULE

The LCD module generates the timing control to drive a static or multiplexed LCD panel, with support for up to 32 segments multiplexed with up to 4 commons . It also provides control of the LCD pixel data.

The interface to the module consists of 3 control registers (LCDCON, LCDSE, and LCDPS) used to deﬁne the timing requirements of the LCD panel and up to 16 LCD data registers (LCD00-LCD15) that represent the array of the pixel data. In normal operation, the control registers are conﬁgured to match the LCD panel being used. Primarily, the initialization information consists of selecting the number of commons required by the LCD panel, and then specifying the LCD Frame cloc k rate to be used by the panel.

Once the module is initialized for the LCD panel, the individual bits of the LCD data registers are cleared/set to represent a clear/dark pixel respectively.

Once the module is conﬁgured, the LCDEN (LCDCON<7>) bit is used to enable or disable the LCD module. The LCD panel can also operate during sleep by clearing the SLPEN (LCDCON<6>) bit.

Figure 13-4 through Figure 13-7 provides waveforms for Static, 1/2, 1/3, and 1/4 MUX drives.

FIGURE 13-1: LCDCON REGISTER (ADDRESS 10Fh)

R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

LCDEN SLPEN

— VGEN CS1 CS0 LMUX1 LMUX0 R =Readable bit

W =Writable bit U =Unimplemented bit, Read as ‘0’

-n =Value at POR reset

bit7 bit0

bit 7: LCDEN: Module drive enable bit

1 = LCD drive enabled 0 = LCD drive disabled

bit 6: SLPEN: LCD display sleep enable

1 = LCD module will stop operating during SLEEP

0 = LCD module will continue to display during SLEEP bit 5: Unimplemented: Read as '0' bit 4: VGEN: Voltage Generator Enable

1 = Internal LCD Voltage Generator Enabled, (powered-up)

0 = Internal LCD Voltage Generator powered-down, voltage is expected to be provided externally

bit 3-2: CS1:CS0: Clock Source Select bits

00 = Fosc/256

01 = T1CKI (Timer1)

1x = Internal RC oscillator

bit 1-0: LMUX1:LMUX0: Common Selection bits

Speciﬁes the number of commons and the bias method

LMUX1:LMUX0 MULTIPLEX BIAS Max # of Segments

00 01 10 11

Static (COM0) 1/2 (COM0, 1) 1/3 (COM0, 1, 2) 1/4 (COM0, 1, 2, 3)

Static 1/3 1/3 1/3

32 31 30 29

PIC16C9XX

DS30444E - page 90  1997 Microchip Technology Inc.

FIGURE 13-2: LCD MODULE BLOCK DIAGRAM

FIGURE 13-3: LCDPS REGISTER (ADDRESS 10Eh)

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — — LP3 LP2 LP1 LP0 R =Readable bit

W =Writable bit U =Unimplemented bit, Read as ‘0’

-n =Value at POR reset

bit7 bit0

bit 7-4: Unimplemented, read as '0' bit 3-0: LP3:LP0: Frame Clock Prescale Selection bits

COM3:COM0

32 x 4

Clock Source

Timing Control

Data Bus

Select and Divide

Internal RC osc

Fosc/4

T1CKI

RAM

128

MUX

SEG<31:0>

TO I/O PADS

LCDCON LCDPS LCDSE

LCD

LMUX1:LMUX0 Multiplex Frame Frequency =

00 Static Clock source / (128 * (LP3:LP0 + 1)) 01 1/2 Clock source / (128 * (LP3:LP0 + 1)) 10 1/3 Clock source / (96 * (LP3:LP0 + 1)) 11 1/4 Clock source / (128 * (LP3:LP0 + 1))

 1997 Microchip Technology Inc. DS30444E - page 91

PIC16C9XX

FIGURE 13-4: WAVEFORMS IN STATIC DRIVE

COM0

SEG0

COM0-SEG0

COM0-SEG1

SEG1

-V

1 Frame

COM0

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

PIC16C9XX

DS30444E - page 92  1997 Microchip Technology Inc.

FIGURE 13-5: WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE

-V

COM0

COM1

SEG0

SEG1

COM0-SEG0

COM0-SEG1

1 Frame

COM1

COM0

SEG0

SEG1

SEG2

SEG3

 1997 Microchip Technology Inc. DS30444E - page 93

PIC16C9XX

FIGURE 13-6: WAVEFORMS IN 1/3 MUX, 1/3 BIAS

-V

COM0

COM1

COM2

SEG0

SEG1

COM0-SEG0

COM0-SEG1

1 Frame

COM2

COM1 COM0

SEG0

SEG1

SEG2

PIC16C9XX

DS30444E - page 94  1997 Microchip Technology Inc.

FIGURE 13-7: WAVEFORMS IN 1/4 MUX, 1/3 BIAS

-V

COM0

COM1

COM2

COM3

SEG0

SEG1

COM0-SEG0

COM0-SEG1

COM3 COM2

COM1 COM0

1 Frame

SEG0

SEG1

 1997 Microchip Technology Inc. DS30444E - page 95

PIC16C9XX

13.1 LCD Timing

The LCD module has 3 possible clock source inputs and supports static, 1/2, 1/3, and 1/4 multiplexing.

13.1.1 TIMING CLOCK SOURCE SELECTION The clock sources for the LCD timing generation are:

• Internal RC oscillator

• Timer1 oscillator

• System clock divided by 256 The ﬁrst timing source is an internal RC oscillator which

runs at a nominal frequency of 14 kHz. This oscillator provides a lower speed clock which may be used to continue running the LCD while the processor is in sleep. The RC oscillator will power-down when it is not selected or when the LCD module is disabled.

The second source is the Timer1 external oscillator. This oscillator provides a lower speed clock which ma y be used to continue running the LCD while the processor is in sleep. It is assumed that the frequency provided on this oscillator will be 32 kHz. To use the Timer1 oscillator as a LCD module clock source, it is only necessary to set the T1OSCEN (T1CON<3>) bit.

The third source is the system clock divided by 256. This divider ratio is chosen to provide about 32 kHz output when the external oscillator is 8 MHz. The divider is not programmable. Instead the LCDPS register is used to set the LCD frame clock rate.

All of the clock sources are selected with bits CS1:CS0 (LCDCON<3:2>). Ref er to Figure 13-1 for details of the register programming.

FIGURE 13-8: LCD CLOCK GENERATION

CS1:CS0

TMR1 32 kHz

crystal oscillator

Internal RC oscillator

Nominal F

RC = 14 kHz

Static

1/2 1/3

1/4

÷4

÷32

LMUX1:LMUX0

4-bit Programmable

LCDPS<3:0>

÷1,2,3,4

Ring Counter

LMUX1:LMUX0

internal

data bus

COM2

÷256

÷2

FOSC

Prescaler

COM0

COM1

COM3

PIC16C9XX

DS30444E - page 96  1997 Microchip Technology Inc.

13.1.2 MULTIPLEX TIMING GENERATION The timing generation circuitry will generate 1 to 4 com-

mon clocks based on the display mode selected. The mode is speciﬁed by bits LMUX1:LMUX0 (LCDCON<1:0>). Table 13-1 shows the formulas for calculating the frame frequency.

TABLE 13-1: FRAME FREQUENCY

FORMULAS

Multiplex Frame Frequency =

Static Clock source / (128 * (LP3:LP0 + 1))

1/2 Clock source / (128 * (LP3:LP0 + 1)) 1/3 Clock source / (96 * (LP3:LP0 + 1)) 1/4 Clock source / (128 * (LP3:LP0 + 1))

TABLE 13-2: APPROX. FRAME FREQ IN Hz

USING TIMER1 @ 32.768 kHz OR Fosc @ 8 MHz

TABLE 13-3: APPROX. FRAME FREQ IN Hz

USING INTERNAL RC OSC @ 14 kHz

LP3:LP0 Static 1/2 1/3 1/4

2 85 85 114 85 3 64 64 85 64 4 51 51 68 51 5 43 43 57 43 6 37 37 49 37 7 32 32 43 32

LP3:LP0 Static 1/2 1/3 1/4

0 109 109 146 109 1 55 55 73 55 2 36 36 49 36 3 27 27 36 27

 1997 Microchip Technology Inc. DS30444E - page 97

PIC16C9XX

13.2 LCD Interrupts

The LCD timing generation provides an interrupt that deﬁnes the LCD frame timing. This interrupt can be used to coordinate the writing of the pixel data with the start of a new frame. Wr iting pixel data at the frame boundary allows a visually crisp transition of the image. This interrupt can also be used to synchronize external events to the LCD. For example, the interface to an external segment driver, such as a Microchip AY0438, can be synchronized for segment data update to the LCD frame.

A new frame is deﬁned to begin at the leading edge of the COM0 common signal. The interrupt will be set immediately after the LCD controller completes accessing all pixel data required for a frame. This will occur at a certain ﬁxed time before the frame boundary as shown in Figure 13-9. The LCD controller will begin to access data for the next frame within T

FWR after the

interrupt.

FIGURE 13-9: EXAMPLE WAVEFORMS IN 1/4 MUX DRIVE

COM0

COM1

COM2

COM3

V3 V2 V1 V0

Frame Boundary

1 Frame

LCD Interrupt occurs

Controller accesses next frame data

TFINT

TFWR

TFWR = TFRAME/(LMUX1:LMUX0 + 1) T

FINT = (TFWR /2 - (2TCY + 40 ns)) → min.

FWR /2 - (1TCY + 40 ns)) → max.

PIC16C9XX

DS30444E - page 98  1997 Microchip Technology Inc.

13.3 Pixel Control

13.3.1 LCDD (PIXEL DATA) REGISTERS The pixel registers contain bits which deﬁne the state of

each pixel. Each bit deﬁnes one unique pixel.

Table 13-4 shows the correlation of each bit in the LCDD registers to the respective common and segment signals.

Any LCD pixel location not being used for display can be used as general purpose RAM.

FIGURE 13-10:GENERIC LCDD REGISTER LAYOUT

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SEGs

COMc

SEGs

COMc

SEGs

COMc

SEGs

COMc

SEGs

COMc

SEGs COMc

SEGs

COMc

SEGs

COMc

R =Readable bit W =Writable bit U =Unimplemented bit, Read as ‘0’

-n =Value at POR reset

bit7 bit0

bit 7-0: SEGsCOMc: Pixel Data Bit for segment s and common c

1 = Pixel on (dark) 0 = Pixel off (clear)

 1997 Microchip Technology Inc. DS30444E - page 99

PIC16C9XX

13.4 Operation During Sleep

The LCD module can operate during sleep. The selection is controlled by bit SLPEN (LCDCON<6>). Setting the SLPEN bit allows the LCD module to go to sleep. Clearing the SLPEN bit allows the module to continue to operate during sleep.

If a SLEEP instruction is executed and SLPEN = '1', the LCD module will cease all functions and go into a very low current consumption mode. The module will stop operation immediately and drive the minimum LCD voltage on both segment and common lines. Figure 13-11 shows this operation. To ensure that the LCD completes the frame, the SLEEP instruction should be executed immediately after a LCD frame boundary.

The LCD interrupt can be used to determine the frame boundary. See Section 13.2 for the formulas to calculate the delay.

If a SLEEP instruction is executed and SLPEN = '0', the module will continue to display the current contents of the LCDD registers. To allow the module to continue operation while in sleep, the clock source must be either the internal RC oscillator or Timer1 external oscillator. While in sleep, the LCD data cannot be changed. The LCD module current consumption will not decrease in this mode, however the overall consumption of the device will be lower due to shutdown of the core and other peripheral functions.

Note: The internal RC oscillator or external

Timer1 oscillator must be used to operate the LCD module during sleep.

FIGURE 13-11:SLEEP ENTRY/EXIT WHEN SLPEN = 1 OR CS1:CS0 = 00

COM0

COM1

COM3

3/3V

1/3V 0/3V

3/3V

1/3V

2/3V

2/3V 1/3V 0/3V

2/3V

0/3V

3/3V 2/3V

1/3V 0/3V

SEG0

SLEEP instruction execution

Wake-up

interrupted

frame

PIC16C9XX

DS30444E - page 100  1997 Microchip Technology Inc.

13.4.1 SEGMENT ENABLES The LCDSE register is used to select the pin function

for groups of pins. The selection allows each group of pins to operate as either LCD drivers or digital only pins. To conﬁgure the pins as a digital por t, the corresponding bits in the LCDSE register must be cleared.

If the pin is a digital I/O the corresponding TRIS bit controls the data direction. Any bit set in the LCDSE register overrides any bit settings in the corresponding TRIS register.

Note 1: On a Power-on Reset these pins are con-

ﬁgured as LCD drivers.

Note 2: The LMUX1:LMUX0 takes precedence

over the LCDSE bit settings for pins RD7, RD6 and RD5.

EXAMPLE 13-1: STATIC MUX WITH 32

SEGMENTS

BCF STATUS,RP0 ;Select Bank 2 BSF STATUS,RP1 ; BCF LCDCON,LMUX1 ;Select Static MUX BCF LCDCON,LMUX0 ; MOVLW 0xFF ;Make PortD,E,F,G MOVWF LCDSE ;LCD pins . . . ;configure rest of LCD

EXAMPLE 13-2: 1/3 MUX WITH 13

SEGMENTS

BCF STATUS,RP0 ;Select Bank 2 BSF STATUS,RP1 ; BSF LCDCON,LMUX1 ;Select 1/3 MUX BCF LCDCON,LMUX0 ; MOVLW 0x87 ;Make PORTD<7:0> & MOVWF LCDSE ;PORTE<6:0> LCD pins . . . ;configure rest of LCD

FIGURE 13-12:LCDSE REGISTER (ADDRESS 10Dh)

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

SE29 SE27 SE20 SE16 SE12 SE9 SE5 SE0 R =Readable bit

W =Writable bit U =Unimplemented bit, Read as ‘0’

-n =Value at POR reset

bit7 bit0

bit 7: SE29: Pin function select RD7/COM1/SEG31 - RD5/COM3/SEG29

1 = pins have LCD drive function 0 = pins have digital Input function The LMUX1:LMUX0 setting takes precedence over the LCDSE register.

bit 6: SE27: Pin function select RG7/SEG28 and RE7/SEG27

1 = pins have LCD drive function 0 = pins have digital Input function

bit 5: SE20: Pin function select RG6/SEG26 - RG0/SEG20

1 = pins have LCD drive function 0 = pins have digital Input function

bit 4: SE16: Pin function select RF7/SEG19 - RF4/SEG16

1 = pins have LCD drive function 0 = pins have digital Input function

bit 3: SE12: Pin function select RF3/SEG15 - RF0/SEG12

1 = pins have LCD drive function 0 = pins have digital Input function

bit 2: SE9: Pin function select RE6/SEG11 - RE4/SEG09

1 = pins have LCD drive function 0 = pins have digital Input function

bit 1: SE5: Pin function select RE3/SEG08 - RE0/SEG05

1 = pins have LCD drive function 0 = pins have digital Input function

bit 0: SE0: Pin function select RD4/SEG04 - RD0/SEG00

1 = pins have LCD drive function

0 = pins have digital I/O function

Microchip Technology Inc PIC16C924-CL Datasheet

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