Microchip Technology Inc PIC16C73-JW, PIC16C73A-04ISO, PIC16C72-JW, PIC16C72A-04-SO, PIC16C72A-04-SP Datasheet



1997 Microchip Technology Inc. DS30390E-page 1

PIC16C7X

8-Bit CMOS Microcontrollers with A/D Converter

Devices included in this data sheet:

PIC16C7X Microcontroller Core Features:

• High-performance RISC CPU

• Only 35 single word instructions to learn

• All single cycle instructions except for program
branches which are two cycle

• Operating speed: DC - 20 MHz clock input

DC - 200 ns instruction cycle

• Up to 8K x 14 words of Program Memory,
up to 368 x 8 bytes of Data Memory (RAM)

• Interrupt capability

• Eight level deep hardware stack

• Direct, indirect, and relative addressing modes

• Power-on Reset (POR)

• Power-up Timer (PWRT) and
Oscillator Start-up Timer (OST)

• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation

• Programmable code-protection

• Power saving SLEEP mode

• Selectable oscillator options

• Low-power, high-speed CMOS EPROM
technology

• Fully static design

• PIC16C72 • PIC16C74A

• PIC16C73 • PIC16C76

• PIC16C73A • PIC16C77

• PIC16C74

• Wide operating voltage range: 2.5V to 6.0V

• High Sink/Source Current 25/25 mA

• Commercial, Industrial and Extended temperature
ranges

• Low-power consumption:

•

< 2 mA @ 5V, 4 MHz

•

15 µ A typical @ 3V, 32 kHz

•

< 1 µ A typical standby current

PIC16C7X Peripheral Features:

• Timer0: 8-bit timer/counter with 8-bit prescaler

• Timer1: 16-bit timer/counter with prescaler,
can be incremented during sleep via external
crystal/clock

• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler

• Capture, Compare, PWM module(s)

• Capture is 16-bit, max. resolution is 12.5 ns,
Compare is 16-bit, max. resolution is 200 ns,
PWM max. resolution is 10-bit

• 8-bit multichannel analog-to-digital converter

• Synchronous Serial Port (SSP) with
SPI



and I

2

C



• Universal Synchronous Asynchronous Receiver
Transmitter (USART/SCI)

• Parallel Slave Port (PSP) 8-bits wide, with
external RD

, WR and CS controls

• Brown-out detection circuitry for
Brown-out Reset (BOR)

PIC16C7X Features 72 73 73A 74 74A 76 77

Program Memory (EPROM) x 14 2K 4K 4K 4K 4K 8K 8K
Data Memory (Bytes) x 8 128 192 192 192 192 368 368
I/O Pins 22 22 22 33 33 22 33
Parallel Slave Port — — — Yes Yes — Yes
Capture/Compare/PWM Modules 1 222222
Timer Modules 3 333333
A/D Channels 5 558858
Serial Communication SPI/I

2

C SPI/I

2

C,

USART

SPI/I

2

C,

USART

SPI/I

2

C,

USART

SPI/I

2

C,

USART

SPI/I

2

C,

USART

SPI/I

2

C,

USART
In-Circuit Serial Programming Yes Yes Yes Yes Yes Yes Yes
Brown-out Reset Yes — Yes — Yes Yes Yes
Interrupt Sources 8 11 11 12 12 11 12

PIC16C7X

DS30390E-page 2



1997 Microchip Technology Inc.

Pin Diagrams

PIC16C72

MCLR/VPP

RA0/AN0
RA1/AN1
RA2/AN2

RA3/AN3/VREF

RA4/T0CKI

RA5/SS/AN4

V

SS

OSC1/CLKIN

OSC2/CLKOUT

RC0/T1OSO/T1CKI

RC1/T1OSI

RC2/CCP1

RC3/SCK/SCL

RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
VDD
VSS
RC7
RC6
RC5/SDO
RC4/SDI/SDA

• 1
2
3
4
5
6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

SDIP, SOIC, Windowed Side Brazed Ceramic

PIC16C72

MCLR/VPP

RA0/AN0
RA1/AN1
RA2/AN2

RA3/AN3/VREF

RA4/T0CKI

RA5/SS/AN4

V

SS

OSC1/CLKIN

OSC2/CLKOUT

RC0/T1OSO/T1CKI

RC1/T1OSI

RC2/CCP1

RC3/SCK/SCL

RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
VDD
VSS
RC7
RC6
RC5/SDO
RC4/SDI/SDA

• 1
2
3
4
5
6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

SSOP

PIC16C73

MCLR/VPP

RA0/AN0
RA1/AN1
RA2/AN2

RA3/AN3/VREF

RA4/T0CKI

RA5/SS/AN4

V

SS

OSC1/CLKIN

OSC2/CLKOUT

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2

RC2/CCP1

RC3/SCK/SCL

RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
VDD
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA

• 1
2
3
4
5
6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

PIC16C73A

SDIP, SOIC, Windowed Side Brazed Ceramic

PIC16C76

PDIP , Windowed CERDIP

RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
V

DD

VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2

MCLR/VPP

RA0/AN0
RA1/AN1

RA2/AN2

RA3/AN3/V

REF

RA4/T0CKI

RA5/SS

/AN4

RE0/RD

/AN5

RE1/WR/AN6

RE2/CS

/AN7

V

DD

VSS

OSC1/CLKIN

OSC2/CLKOUT

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2

RC2/CCP1

RC3/SCK/SCL

RD0/PSP0
RD1/PSP1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

PIC16C74
PIC16C74A
PIC16C77



1997 Microchip Technology Inc. DS30390E-page 3

PIC16C7X

Pin Diagrams (Cont.’d)

NC
RC0/T1OSO/T1CKI

OSC2/CLKOUT
OSC1/CLKIN
V

SS

VDD
RE2/CS/AN7
RE1/WR

/AN6

RE0/RD

/AN5

RA5/SS

/AN4

RA4/T0CKI

RC7/RX/DT

RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7

V

SS

VDD

RB0/INT

RB1
RB2
RB3

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

RD3/PSP3

RD2/PSP2

RD1/PSP1

RD0/PSP0

RC3/SCK/SCL

RC2/CCP1

RC1/T1OSI/CCP2

NC

1
2
3
4
5
6
7
8
9
10
11

33
32
31
30
29
28
27
26
25
24
23

4443424140393837363534

2221201918171615141312

PIC16C74

MQFP

RB3
RB2
RB1
RB0/INT
V

DD

VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT

RA4/T0CKI

RA5/SS

/AN4

RE0/RD

/AN5

RE1/WR

/AN6

RE2/CS/AN7

V

DD

VSS

OSC1/CLKIN

OSC2/CLKOUT

RC0/T1OSO/T1CKI

NC

RA3/AN3/VREF

RA2/AN2

RA1/AN1

RA0/AN0

MCLR

/VPP

NC

RB7

RB6

RB5

RB4

NC

7
8
9
10
11
12
13
14
15
16
17

39
38
37
36
35
34
33
32
31
30
29

NC

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

RD3/PSP3

RD2/PSP2

RD1/PSP1

RD0/PSP0

RC3/SCK/SCL

RC2/CCP1

65432

1

4443424140

2827262524232221201918

PIC16C74

NC
RC0/T1OSO/T1CKI

OSC2/CLKOUT
OSC1/CLKIN
V

SS

VDD
RE2/CS/AN7
RE1/WR

/AN6

RE0/RD

/AN5

RA5/SS

/AN4

RA4/T0CKI

RC7/RX/DT

RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7

V

SS

VDD

RB0/INT

RB1
RB2
RB3

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

RD3/PSP3

RD2/PSP2

RD1/PSP1

RD0/PSP0

RC3/SCK/SCL

RC2/CCP1

RC1/T1OSI/CCP2

NC

1
2
3
4
5
6
7
8
9
10
11

33
32
31
30
29
28
27
26
25
24
23

RA3/AN3/VREF

RA2/AN2

RA1/AN1

RA0/AN0

MCLR

/VPP

RB7

RB6

RB5

RB4

NC

NC

4443424140393837363534

2221201918171615141312

MQFP

PLCC

PIC16C74A

PIC16C74A

TQFP

PIC16C77

PIC16C77

RC1/T1OSI/CCP2

RA3/AN3/V

REF

RA2/AN2

RA1/AN1

RA0/AN0

MCLR

/VPP

RB7

RB6

RB5

RB4

NC

NC

PIC16C7X

DS30390E-page 4



1997 Microchip Technology Inc.

Table of Contents

1.0 General Description....................................................................................................................................................................... 5

2.0 PIC16C7X Device Varieties...........................................................................................................................................................7

3.0 Architectural Overview................................................................................................................................................................... 9

4.0 Memory Organization................................................................................................................................................................... 19

5.0 I/O Ports....................................................................................................................................................................................... 43

6.0 Overview of Timer Modules......................................................................................................................................................... 57

7.0 Timer0 Module............................................................................................................................................................................. 59

8.0 Timer1 Module............................................................................................................................................................................. 65

9.0 Timer2 Module............................................................................................................................................................................. 69

10.0 Capture/Compare/PWM Module(s).............................................................................................................................................. 71

11.0 Synchronous Serial Port (SSP) Module....................................................................................................................................... 77

12.0 Universal Synchronous Asynchronous Receiver Transmitter (USART)...................................................................................... 99

13.0 Analog-to-Digital Converter (A/D) Module ................................................................................................................................. 117

14.0 Special Features of the CPU ..................................................................................................................................................... 129

15.0 Instruction Set Summary............................................................................................................................................................ 147

16.0 Development Support................................................................................................................................................................ 163

17.0 Electrical Characteristics for PIC16C72..................................................................................................................................... 167

18.0 Electrical Characteristics for PIC16C73/74................................................................................................................................ 183

19.0 Electrical Characteristics for PIC16C73A/74A........................................................................................................................... 201

20.0 Electrical Characteristics for PIC16C76/77................................................................................................................................ 219

21.0 DC and AC Characteristics Graphs and Tables ........................................................................................................................ 241

22.0 Packaging Information............................................................................................................................................................... 251

Appendix A: ................................................................................................................................................................................... 263

Appendix B: Compatibility............................................................................................................................................................. 263

Appendix C: What’s New............................................................................................................................................................... 264

Appendix D: What’s Changed....................................................................................................................................................... 264

Appendix E: PIC16/17 Microcontrollers ....................................................................................................................................... 265

Pin Compatibility ................................................................................................................................................................................ 271

Index .................................................................................................................................................................................................. 273

List of Examples................................................................................................................................................................................. 279

List of Figures..................................................................................................................................................................................... 280

List of Tables...................................................................................................................................................................................... 283

Reader Response.............................................................................................................................................................................. 286

PIC16C7X Product Identification System........................................................................................................................................... 287

For register and module descriptions in this data sheet, device legends show which devices apply to those sections. As
an example, the legend below would mean that the following section applies only to the PIC16C72, PIC16C73A and
PIC16C74A devices.

Applicable Devices

72

73 73A 74 74A 76 77

To Our Valued Customers

We constantly strive to improve the quality of all our products and documentation. We have spent an exceptional
amount of time to ensure that these documents are correct. However, we realize that we may have missed a few
things. If you find any information that is missing or appears in error, please use the reader response form in the
back of this data sheet to inform us. We appreciate your assistance in making this a better document.



1997 Microchip Technology Inc. DS30390E-page 5

PIC16C7X

1.0 GENERAL DESCRIPTION

The PIC16C7X is a family of

low-cost, high-perfor­mance, CMOS, fully-static, 8-bit microcontrollers with
integrated analog-to-digital (A/D) converters, in the
PIC16CXX mid-range family.

All PIC16/17 microcontrollers employ an advanced
RISC architecture. The PIC16CXX microcontroller fam­ily has enhanced core features, eight-level deep stack,
and multiple internal and external interrupt sources.
The separate instruction and data buses of the Harvard
architecture allow a 14-bit wide instruction word with
the separate 8-bit wide data. The two stage instruction
pipeline allows all instructions to execute in a single
cycle, except for program branches which require two
cycles. A total of 35 instructions (reduced instruction
set) are available . Additionally, a large register set gives
some of the architectural innovations used to achie v e a
very high performance.

PIC16CXX microcontrollers typically achieve a 2:1
code compression and a 4:1 speed improvement over
other 8-bit microcontrollers in their class.

The PIC16C72 has 128 bytes of RAM and 22 I/O pins.
In addition several peripheral features are available
including: three timer/counters, one Capture/Compare/
PWM module and one serial port. The Synchronous
Serial Port can be configured as either a 3-wire Serial
Peripheral Interface (SPI) or the two-wire Inter-Inte­grated Circuit (I

2

C) bus. Also a 5-channel high-speed
8-bit A/D is provided. The 8-bit resolution is ideally
suited for applications requiring low-cost analog inter­face, e.g. thermostat control, pressure sensing, etc.

The PIC16C73/73A devices have 192 bytes of RAM,
while the PIC16C76 has 368 byes of RAM. Each de vice
has 22 I/O pins. In addition, several peripheral features
are available including: three timer/counters, two Cap­ture/Compare/PWM modules and two serial ports. The
Synchronous Serial Port can be configured as either a
3-wire Serial Peripheral Interface (SPI) or the two-wire
Inter-Integrated Circuit (I

2

C) bus. The Universal Syn­chronous Asynchronous Receiver Transmitter
(USART) is also known as the Serial Communications
Interface or SCI. Also a 5-channel high-speed 8-bit A/
D is provided.The 8-bit resolution is ideally suited for
applications requiring low-cost analog interface, e.g.
thermostat control, pressure sensing, etc.

The PIC16C74/74A devices have 192 bytes of RAM,
while the PIC16C77 has 368 bytes of RAM. Each
device has 33 I/O pins. In addition several peripheral
features are available including: three timer/counters,
two Capture/Compare/PWM modules and two serial
ports. The Synchronous Serial Port can be configured
as either a 3-wire Serial Peripheral Interface (SPI) or
the two-wire Inter-Integrated Circuit (I

2

C) bus. The Uni­versal Synchronous Asynchronous Receiver Transmit­ter (USART) is also known as the Serial
Communications Interface or SCI. An 8-bit Parallel
Slave Port is provided. Also an 8-channel high-speed

8-bit A/D is provided. The 8-bit resolution is ideally
suited for applications requiring low-cost analog inter­face, e.g. thermostat control, pressure sensing, etc.

The PIC16C7X family has special features to reduce
external components, thus reducing cost, enhancing
system reliability and reducing power consumption.
There are four oscillator options, of which the single pin
RC oscillator provides a low-cost solution, the LP oscil­lator minimizes power consumption, XT is a standard
crystal, and the HS is for High Speed crystals. The
SLEEP (power-down) feature provides a power saving
mode. The user can wake up the chip from SLEEP
through several external and internal interrupts and
resets.

A highly reliable Watchdog Timer with its own on-chip
RC oscillator provides protection against software lock­up.

A UV erasable CERDIP packaged version is ideal for
code development while the cost-effective One-Time­Programmable (OTP) version is suitable for production
in any volume.

The PIC16C7X family fits perfectly in applications rang­ing from security and remote sensors to appliance con­trol and automotive. The EPROM technology makes
customization of application programs (transmitter
codes, motor speeds, receiver frequencies, etc.)
extremely fast and convenient. The small footprint
packages make this microcontroller series perfect for
all applications with space limitations. Low cost, low
power, high performance, ease of use and I/O flexibility
make the PIC16C7X very versatile ev en in areas where
no microcontroller use has been considered before
(e.g. timer functions, serial communication, capture
and compare, PWM functions and coprocessor appli­cations).

1.1 F

amily and Upward Compatibility

Users familiar with the PIC16C5X microcontroller fam­ily will realize that this is an enhanced version of the
PIC16C5X architecture. Please refer to Appendix A for
a detailed list of enhancements. Code written for the
PIC16C5X can be easily ported to the PIC16CXX fam­ily of devices (Appendix B).

1.2 De

velopment Support

PIC16C7X devices are supported by the complete line
of Microchip Development tools.

Please refer to Section 16.0 for more details about
Microchip’s development tools.

PIC16C7X

DS30390E-page 6



1997 Microchip Technology Inc.

TABLE 1-1: PIC16C7XX FAMILY OF DEVCES

PIC16C710

PIC16C71 PIC16C711 PIC16C715 PIC16C72 PIC16CR72

(1)

Clock

Maximum Frequency
of Operation (MHz)

20 20 20 20 20 20

Memory

EPROM Program Memory
(x14 words)

512 1K 1K 2K 2K —

ROM Program Memory
(14K words)

—————2K

Data Memory (bytes) 36 36 68 128 128 128

Peripherals

Timer Module(s) TMR0 TMR0 TMR0 TMR0 TMR0,

TMR1,
TMR2

TMR0,
TMR1,
TMR2

Capture/Compare/
PWM Module(s)

————1 1

Serial Port(s)
(SPI/I

2

C, USART)

— — — — SPI/I

2

C SPI/I

2

C

Parallel Slave Port — — — — — —
A/D Converter (8-bit) Channels 4 4 4 4 5 5

Features

Interrupt Sources 4 4 4 4 8 8
I/O Pins 13 13 13 13 22 22
Voltage Range (Volts) 3.0-6.0 3.0-6.0 3.0-6.0 3.0-5.5 2.5-6.0 3.0-5.5
In-Circuit Serial Programming Yes Yes Yes Yes Yes Yes
Brown-out Reset Yes — Yes Yes Yes Yes
Packages 18-pin DIP,

SOIC;
20-pin SSOP

18-pin DIP,
SOIC

18-pin DIP,
SOIC;
20-pin SSOP

18-pin DIP,
SOIC;
20-pin SSOP

28-pin SDIP,
SOIC, SSOP

28-pin SDIP,
SOIC, SSOP

PIC16C73A

PIC16C74A PIC16C76 PIC16C77

Clock

Maximum Frequency of Oper­ation (MHz)

20 20 20 20

Memory

EPROM Program Memory
(x14 words)

4K 4K 8K 8K

Data Memory (bytes) 192 192 368 368

Peripherals

Timer Module(s) TMR0,

TMR1,
TMR2

TMR0,
TMR1,
TMR2

TMR0,
TMR1,
TMR2

TMR0,
TMR1,
TMR2

Capture/Compare/PWM Mod­ule(s)

2222

Serial Port(s) (SPI/I

2

C, US-

ART)

SPI/I

2

C, USART SPI/I

2

C, USART SPI/I

2

C, USART SPI/I

2

C, USART

Parallel Slave Port — Yes — Yes
A/D Converter (8-bit) Channels 5858

Features

Interrupt Sources 11 12 11 12
I/O Pins 22 33 22 33
Voltage Range (Volts) 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0
In-Circuit Serial Programming Yes Yes Yes Yes
Brown-out Reset Yes Yes Yes Yes
Packages 28-pin SDIP,

SOIC

40-pin DIP;
44-pin PLCC,
MQFP, TQFP

28-pin SDIP,
SOIC

40-pin DIP;
44-pin PLCC,
MQFP, TQFP

All PIC16/17 Family devices ha ve Pow er-on Reset, selectab le Watchdog Timer, selectab le code protect and high I/O current capabil­ity. All PIC16C7XX Family devices use serial programming with clock pin RB6 and data pin RB7.
Note 1: Please contact your local Microchip sales office for availability of these devices.



1997 Microchip Technology Inc. DS30390E-page 7

PIC16C7X

2.0 PIC16C7X DEVICE VARIETIES

A variety of frequency ranges and packaging options
are available . Depending on application and production
requirements, the proper device option can be selected
using the information in the PIC16C7X Product Identifi­cation System section at the end of this data sheet.
When placing orders, please use that page of the data
sheet to specify the correct part number.

For the PIC16C7X family, there are two device “types”
as indicated in the device number:

1. C , as in PIC16 C 74. These devices have

EPROM type memory and operate over the
standard voltage range.

2. LC , as in PIC16 LC 74. These devices have

EPROM type memory and operate over an
extended voltage range.

2.1 UV Erasab

le Devices

The UV erasable version, offered in CERDIP package
is optimal for prototype development and pilot
programs. This version can be erased and
reprogrammed to any of the oscillator modes.

Microchip's PICSTART



Plus and PRO MATE



II
programmers both support programming of the
PIC16C7X.

2.2 O

ne-Time-Programmable (OTP)

Devices

The availability of OTP devices is especially useful for
customers who need the flexibility for frequent code
updates and small volume applications.

The OTP devices, packaged in plastic packages, per­mit the user to program them once. In addition to the
program memory, the configuration bits must also be
programmed.

2.3 Q

uick-Turnaround-Production (QTP)

Devices

Microchip offers a QTP Programming Service for fac­tory production orders. This service is made available
for users who choose not to program a medium to high
quantity of units and whose code patterns have stabi­lized. The devices are identical to the OTP devices but
with all EPROM locations and configuration options
already programmed by the factory. Certain code and
prototype verification procedures apply before produc­tion shipments are available. Please contact your local
Microchip Technology sales office for more details.

2.4 Serializ

ed Quick-Turnaround

Production (SQTP

SM

)

Devices

Microchip offers a unique programming service where
a few user-defined locations in each device are pro­grammed with different serial numbers. The serial num­bers may be random, pseudo-random, or sequential.

Serial programming allows each device to have a
unique number which can serve as an entry-code,
password, or ID number.

PIC16C7X

DS30390E-page 8



1997 Microchip Technology Inc.

NOTES:



1997 Microchip Technology Inc. DS30390E-page 9

PIC16C7X

3.0 ARCHITECTURAL OVERVIEW

The high performance of the PIC16CXX family can be
attributed to a number of architectural features com­monly found in RISC microprocessors. To begin with,
the PIC16CXX uses a Harvard architecture, in which,
program and data are accessed from separate memo­ries using separate buses. This improves bandwidth
over traditional von Neumann architecture in which pro­gram and data are fetched from the same memory
using the same bus. Separating program and data
buses further allows instructions to be sized differently
than the 8-bit wide data word. Instruction opcodes are
14-bits wide making it possible to have all single word
instructions. A 14-bit wide program memory access
bus fetches a 14-bit instruction in a single cycle. A two­stage pipeline overlaps fetch and execution of instruc­tions (Example 3-1). Consequently, all instructions (35)
execute in a single cycle (200 ns @ 20 MHz) e xcept f or
program branches.

The table below lists program memory (EPROM) and
data memory (RAM) for each PIC16C7X device.

The PIC16CXX can directly or indirectly address its
register files or data memory. All special function regis­ters, including the program counter, are mapped in the
data memory. The PIC16CXX has an orthogonal (sym­metrical) instruction set that makes it possible to carry
out any operation on any register using any addressing
mode. This symmetrical nature and lack of ‘special
optimal situations’ make programming with the
PIC16CXX simple yet efficient. In addition, the learning
curve is reduced significantly.

Device

Program

Memory

Data Memory

PIC16C72 2K x 14 128 x 8
PIC16C73 4K x 14 192 x 8
PIC16C73A 4K x 14 192 x 8
PIC16C74 4K x 14 192 x 8
PIC16C74A 4K x 14 192 x 8
PIC16C76 8K x 14 368 x 8
PIC16C77 8K x 14 386 x 8

PIC16CXX devices contain an 8-bit ALU and working
register. The ALU is a general purpose arithmetic unit.
It performs arithmetic and Boolean functions between
the data in the working register and any register file.

The ALU is 8-bits wide and capable of addition, sub­traction, shift and logical operations. Unless otherwise
mentioned, arithmetic operations are two's comple­ment in nature. In two-operand instructions, typically
one operand is the working register (W register). The
other operand is a file register or an immediate con­stant. In single operand instructions, the operand is
either the W register or a file register.

The W register is an 8-bit working register used for ALU
operations. It is not an addressable register.

Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC), and
Zero (Z) bits in the STATUS register. The C and DC bits
operate as a borro

w bit and a digit borrow out bit,
respectively, in subtraction. See the SUBLW and SUBWF
instructions for examples.

PIC16C7X

DS30390E-page 10  1997 Microchip Technology Inc.

FIGURE 3-1: PIC16C72 BLOCK DIAGRAM

EPROM

Program

Memory

2K x 14

13

Data Bus

8

14

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

RAM

File

Registers

128 x 8

Direct Addr

7

RAM Addr

(1)

9

Addr MUX

Indirect

Addr

FSR reg

STATUS reg

MUX

ALU

W reg

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKIN
OSC2/CLKOUT

MCLR

VDD, VSS

Timer0

A/D

Synchronous

Serial Port

PORTA

PORTB

PORTC

RB0/INT

RB7:RB1

RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6
RC7

8

8

Brown-out

Reset

Note 1: Higher order bits are from the STATUS register.

CCP1

Timer1 Timer2

RA4/T0CKI
RA5/SS

/AN4

RA3/AN3/VREF

RA2/AN2

RA1/AN1

RA0/AN0

8

3

 1997 Microchip Technology Inc. DS30390E-page 11

PIC16C7X

FIGURE 3-2: PIC16C73/73A/76 BLOCK DIAGRAM

EPROM

Program

Memory

13

Data Bus

8

14

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

RAM

File

Registers

Direct Addr

7

RAM Addr

(1)

9

Addr MUX

Indirect

Addr

FSR reg

STATUS reg

MUX

ALU

W reg

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Instruction
Decode &

Control

Timing

Generation

OSC1/CLKIN
OSC2/CLKOUT

MCLR

VDD, VSS

USART

PORTA

PORTB

PORTC

RB0/INT

RB7:RB1

RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT

8

8

Brown-out

Reset

(2)

Note 1: Higher order bits are from the STATUS register.

2: Brown-out Reset is not available on the PIC16C73.

CCP1 CCP2

Synchronous

A/DTimer0 Timer1 Timer2

Serial Port

RA4/T0CKI
RA5/SS

/AN4

RA3/AN3/VREF

RA2/AN2

RA1/AN1

RA0/AN0

8

3

Device Program Memory Data Memory (RAM)

PIC16C73
PIC16C73A
PIC16C76

4K x 14
4K x 14
8K x 14

192 x 8
192 x 8
368 x 8

PIC16C7X

DS30390E-page 12  1997 Microchip Technology Inc.

FIGURE 3-3: PIC16C74/74A/77 BLOCK DIAGRAM

EPROM

Program

Memory

13

Data Bus

8

14

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

RAM

File

Registers

Direct Addr

7

RAM Addr

(1)

9

Addr MUX

Indirect

Addr

FSR reg

STATUS reg

MUX

ALU

W reg

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKIN
OSC2/CLKOUT

MCLR

VDD, VSS

PORTA

PORTB

PORTC

PORTD

PORTE

RA4/T0CKI
RA5/SS/AN4

RB0/INT

RB7:RB1

RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT

RD7/PSP7:RD0/PSP0

RE0/RD

/AN5

RE1/WR

/AN6

RE2/CS

/AN7

8

8

Brown-out

Reset

(2)

Note 1: Higher order bits are from the STATUS register.

2: Brown-out Reset is not available on the PIC16C74.

USART

CCP1 CCP2

Synchronous

A/DTimer0 Timer1 Timer2

Serial Port

RA3/AN3/VREF

RA2/AN2

RA1/AN1

RA0/AN0

Parallel Slave Port

8

3

Device Program Memory Data Memory (RAM)

PIC16C74
PIC16C74A
PIC16C77

4K x 14
4K x 14
8K x 14

192 x 8
192 x 8
368 x 8

 1997 Microchip Technology Inc. DS30390E-page 13

PIC16C7X

TABLE 3-1: PIC16C72 PINOUT DESCRIPTION

Pin Name

DIP

Pin#

SSOP

Pin#

SOIC

Pin#

I/O/P
Type

Buffer

Type

Description

OSC1/CLKIN 9 9 9 I

ST/CMOS

(3)

Oscillator crystal input/external clock source input.

OSC2/CLKOUT 10 10 10 O — Oscillator crystal output. Connects to crystal or resonator in

crystal oscillator mode. In RC mode, the OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and denotes
the instruction cycle rate.

MCLR

/VPP

1 1 1 I/P ST Master clear (reset) input or programming voltage input. This

pin is an active low reset to the device.

PORTA is a bi-directional I/O port.
RA0/AN0 2 2 2 I/O TTL RA0 can also be analog input0
RA1/AN1 3 3 3 I/O TTL RA1 can also be analog input1
RA2/AN2 4 4 4 I/O TTL RA2 can also be analog input2
RA3/AN3/VREF 5 5 5 I/O TTL RA3 can also be analog input3 or analog reference voltage
RA4/T0CKI 6 6 6 I/O ST RA4 can also be the clock input to the Timer0 module.

Output is open drain type.

RA5/SS/AN4 7 7 7 I/O TTL RA5 can also be analog input4 or the slave select for the

synchronous serial port.

PORTB is a bi-directional I/O port. PORTB can be software

programmed for internal weak pull-up on all inputs.
RB0/INT 21 21 21 I/O TTL/ST

(1)

RB0 can also be the external interrupt pin.
RB1 22 22 22 I/O TTL
RB2 23 23 23 I/O TTL
RB3 24 24 24 I/O TTL
RB4 25 25 25 I/O TTL Interrupt on change pin.
RB5 26 26 26 I/O TTL Interrupt on change pin.
RB6 27 27 27 I/O TTL/ST

(2)

Interrupt on change pin. Serial programming clock.
RB7 28 28 28 I/O TTL/ST

(2)

Interrupt on change pin. Serial programming data.

PORTC is a bi-directional I/O port.

RC0/T1OSO/T1CKI 11 11 11 I/O ST RC0 can also be the Timer1 oscillator output or Timer1

clock input.
RC1/T1OSI 12 12 12 I/O ST RC1 can also be the Timer1 oscillator input.
RC2/CCP1 13 13 13 I/O ST RC2 can also be the Capture1 input/Compare1 output/

PWM1 output.
RC3/SCK/SCL 14 14 14 I/O ST RC3 can also be the synchronous serial clock input/output

for both SPI and I

2

C modes.

RC4/SDI/SDA 15 15 15 I/O ST RC4 can also be the SPI Data In (SPI mode) or

data I/O (I2C mode).
RC5/SDO 16 16 16 I/O ST RC5 can also be the SPI Data Out (SPI mode).
RC6 17 17 17 I/O ST
RC7 18 18 18 I/O ST
VSS 8, 19 8, 19 8, 19 P — Ground reference for logic and I/O pins.
VDD 20 20 20 P — Positive supply for logic and I/O pins.
Legend: I = input O = output I/O = input/output P = power

— = Not used TTL = TTL input ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.

2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.

PIC16C7X

DS30390E-page 14  1997 Microchip Technology Inc.

TABLE 3-2: PIC16C73/73A/76 PINOUT DESCRIPTION

Pin Name

DIP

Pin#

SOIC

Pin#

I/O/P
Type

Buffer

Type

Description

OSC1/CLKIN 9 9 I

ST/CMOS

(3)

Oscillator crystal input/external clock source input.

OSC2/CLKOUT 10 10 O — Oscillator crystal output. Connects to crystal or resonator in

crystal oscillator mode. In RC mode, the OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and denotes
the instruction cycle rate.

MCLR

/VPP

1 1 I/P ST Master clear (reset) input or programming voltage input. This

pin is an active low reset to the device.

PORTA is a bi-directional I/O port.
RA0/AN0 2 2 I/O TTL RA0 can also be analog input0
RA1/AN1 3 3 I/O TTL RA1 can also be analog input1
RA2/AN2 4 4 I/O TTL RA2 can also be analog input2
RA3/AN3/VREF 5 5 I/O TTL RA3 can also be analog input3 or analog reference voltage
RA4/T0CKI 6 6 I/O ST RA4 can also be the clock input to the Timer0 module.

Output is open drain type.

RA5/SS/AN4 7 7 I/O TTL RA5 can also be analog input4 or the slave select for the

synchronous serial port.

PORTB is a bi-directional I/O port. PORTB can be software

programmed for internal weak pull-up on all inputs.
RB0/INT 21 21 I/O TTL/ST

(1)

RB0 can also be the external interrupt pin.
RB1 22 22 I/O TTL
RB2 23 23 I/O TTL
RB3 24 24 I/O TTL
RB4 25 25 I/O TTL Interrupt on change pin.
RB5 26 26 I/O TTL Interrupt on change pin.
RB6 27 27 I/O TTL/ST

(2)

Interrupt on change pin. Serial programming clock.
RB7 28 28 I/O TTL/ST

(2)

Interrupt on change pin. Serial programming data.

PORTC is a bi-directional I/O port.

RC0/T1OSO/T1CKI 11 11 I/O ST RC0 can also be the Timer1 oscillator output or Timer1

clock input.
RC1/T1OSI/CCP2 12 12 I/O ST RC1 can also be the Timer1 oscillator input or Capture2

input/Compare2 output/PWM2 output.
RC2/CCP1 13 13 I/O ST RC2 can also be the Capture1 input/Compare1 output/

PWM1 output.
RC3/SCK/SCL 14 14 I/O ST RC3 can also be the synchronous serial clock input/output

for both SPI and I

2

C modes.

RC4/SDI/SDA 15 15 I/O ST RC4 can also be the SPI Data In (SPI mode) or

data I/O (I2C mode).
RC5/SDO 16 16 I/O ST RC5 can also be the SPI Data Out (SPI mode).
RC6/TX/CK 17 17 I/O ST RC6 can also be the USART Asynchronous Transmit or

Synchronous Clock.
RC7/RX/DT 18 18 I/O ST RC7 can also be the USART Asynchronous Receive or

Synchronous Data.
VSS 8, 19 8, 19 P — Ground reference for logic and I/O pins.
VDD 20 20 P — Positive supply for logic and I/O pins.
Legend: I = input O = output I/O = input/output P = power

— = Not used TTL = TTL input ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.

2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.

 1997 Microchip Technology Inc. DS30390E-page 15

PIC16C7X

TABLE 3-3: PIC16C74/74A/77 PINOUT DESCRIPTION

Pin Name

DIP

Pin#

PLCC

Pin#

QFP
Pin#

I/O/P
Type

Buffer

Type

Description

OSC1/CLKIN 13 14 30 I ST/CMOS

(4)

Oscillator crystal input/external clock source input.

OSC2/CLKOUT 14 15 31 O — Oscillator crystal output. Connects to crystal or resonator in

crystal oscillator mode. In RC mode, OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and
denotes the instruction cycle rate.

MCLR/VPP 1 2 18 I/P ST Master clear (reset) input or programming voltage input.

This pin is an active low reset to the device.

PORTA is a bi-directional I/O port.
RA0/AN0 2 3 19 I/O TTL RA0 can also be analog input0
RA1/AN1 3 4 20 I/O TTL RA1 can also be analog input1
RA2/AN2 4 5 21 I/O TTL RA2 can also be analog input2
RA3/AN3/VREF 5 6 22 I/O TTL RA3 can also be analog input3 or analog reference

voltage

RA4/T0CKI 6 7 23 I/O ST RA4 can also be the clock input to the Timer0 timer/

counter. Output is open drain type.

RA5/SS/AN4 7 8 24 I/O TTL RA5 can also be analog input4 or the slave select for

the synchronous serial port.

PORTB is a bi-directional I/O port. PORTB can be softw are

programmed for internal weak pull-up on all inputs.
RB0/INT 33 36 8 I/O TTL/ST

(1)

RB0 can also be the external interrupt pin.
RB1 34 37 9 I/O TTL
RB2 35 38 10 I/O TTL
RB3 36 39 11 I/O TTL
RB4 37 41 14 I/O TTL Interrupt on change pin.
RB5 38 42 15 I/O TTL Interrupt on change pin.
RB6 39 43 16 I/O TTL/ST

(2)

Interrupt on change pin. Serial programming clock.
RB7 40 44 17 I/O TTL/ST

(2)

Interrupt on change pin. Serial programming data.
Legend: I = input O = output I/O = input/output P = power

— = Not used TTL = TTL input ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt.

2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel

Slave Port mode (for interfacing to a microprocessor bus).

4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.

PIC16C7X

DS30390E-page 16  1997 Microchip Technology Inc.

PORTC is a bi-directional I/O port.

RC0/T1OSO/T1CKI 15 16 32 I/O ST RC0 can also be the Timer1 oscillator output or a

Timer1 clock input.

RC1/T1OSI/CCP2 16 18 35 I/O ST RC1 can also be the Timer1 oscillator input or

Capture2 input/Compare2 output/PWM2 output.

RC2/CCP1 17 19 36 I/O ST RC2 can also be the Capture1 input/Compare1 output/

PWM1 output.

RC3/SCK/SCL 18 20 37 I/O ST RC3 can also be the synchronous serial clock input/

output for both SPI and I2C modes.

RC4/SDI/SDA 23 25 42 I/O ST RC4 can also be the SPI Data In (SPI mode) or

data I/O (I2C mode).

RC5/SDO 24 26 43 I/O ST RC5 can also be the SPI Data Out

(SPI mode).

RC6/TX/CK 25 27 44 I/O ST RC6 can also be the USART Asynchronous Transmit or

Synchronous Clock.

RC7/RX/DT 26 29 1 I/O ST RC7 can also be the USART Asynchronous Receive or

Synchronous Data.

PORTD is a bi-directional I/O port or parallel slave port
when interfacing to a microprocessor bus.

RD0/PSP0 19 21 38 I/O ST/TTL

(3)

RD1/PSP1 20 22 39 I/O ST/TTL

(3)

RD2/PSP2 21 23 40 I/O ST/TTL

(3)

RD3/PSP3 22 24 41 I/O ST/TTL

(3)

RD4/PSP4 27 30 2 I/O ST/TTL

(3)

RD5/PSP5 28 31 3 I/O ST/TTL

(3)

RD6/PSP6 29 32 4 I/O ST/TTL

(3)

RD7/PSP7 30 33 5 I/O ST/TTL

(3)

PORTE is a bi-directional I/O port.

RE0/RD/AN5 8 9 25 I/O ST/TTL

(3)

RE0 can also be read control for the parallel slave port,
or analog input5.

RE1/WR/AN6 9 10 26 I/O ST/TTL

(3)

RE1 can also be write control for the parallel slave port,
or analog input6.

RE2/CS/AN7 10 11 27 I/O ST/TTL

(3)

RE2 can also be select control for the parallel slave

port, or analog input7.
VSS 12,31 13,34 6,29 P — Ground reference for logic and I/O pins.
VDD 11,32 12,35 7,28 P — Positive supply for logic and I/O pins.
NC — 1,17,28,4012,13,

33,34

— These pins are not internally connected. These pins should

be left unconnected.

TABLE 3-3: PIC16C74/74A/77 PINOUT DESCRIPTION (Cont.’d)

Pin Name

DIP

Pin#

PLCC

Pin#

QFP
Pin#

I/O/P
Type

Buffer

Type

Description

Legend: I = input O = output I/O = input/output P = power

— = Not used TTL = TTL input ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt.

2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel

Slave Port mode (for interfacing to a microprocessor bus).

4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.

 1997 Microchip Technology Inc. DS30390E-page 17

PIC16C7X

3.1 Clocking Scheme/Instruction Cycle

The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks namely Q1, Q2, Q3 and Q4. Internally, the pro­gram counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instruc­tion is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
is shown in Figure 3-4.

3.2 Instruction Flow/Pipelining

An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instr uction fetch and execute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g. GOTO)
then two cycles are required to complete the instruction
(Example 3-1).

A fetch cycle begins with the program counter (PC)
incrementing in Q1.

In the execution cycle, the f etched instruction is latched
into the “Instruction Register" (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).

FIGURE 3-4: CLOCK/INSTRUCTION CYCLE

EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW

Q1

Q2 Q3 Q4

Q1

Q2 Q3 Q4

Q1

Q2 Q3 Q4

OSC1

Q1
Q2
Q3

Q4
PC

OSC2/CLKOUT

(RC mode)

PC PC+1 PC+2

Fetch INST (PC)

Execute INST (PC-1) Fetch INST (PC+1)

Execute INST (PC) Fetch INST (PC+2)

Execute INST (PC+1)

Internal
phase
clock

All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.

Tcy0 Tcy1 Tcy2 Tcy3 Tcy4 Tcy5

1. MOVLW 55h

Fetch 1 Execute 1

2. MOVWF PORTB

Fetch 2 Execute 2

3. CALL SUB_1

Fetch 3 Execute 3

4. BSF PORTA, BIT3 (Forced NOP)

Fetch 4 Flush

5. Instruction @ address SUB_1

Fetch SUB_1 Execute SUB_1

PIC16C7X

DS30390E-page 18  1997 Microchip Technology Inc.

NOTES:

 1997 Microchip Technology Inc. DS30390E-page 19

PIC16C7X

4.0 MEMORY ORGANIZATION

4.1 Program Memory Organization

The PIC16C7X family has a 13-bit program counter
capable of addressing an 8K x 14 program memory
space. The amount of program memory available to
each device is listed below:

For those devices with less than 8K program memory,
accessing a location above the physically implemented
address will cause a wraparound.

The reset vector is at 0000h and the interrupt vector is
at 0004h.

FIGURE 4-1: PIC16C72 PROGRAM

MEMORY MAP AND STACK

Applicable Devices

72 73 73A 74 74A 76 77

Device

Program

Memory

Address Range

PIC16C72 2K x 14 0000h-07FFh
PIC16C73 4K x 14 0000h-0FFFh
PIC16C73A 4K x 14 0000h-0FFFh
PIC16C74 4K x 14 0000h-0FFFh
PIC16C74A 4K x 14 0000h-0FFFh
PIC16C76 8K x 14 0000h-1FFFh
PIC16C77 8K x 14 0000h-1FFFh

PC<12:0>

13

0000h

0004h
0005h

07FFh

1FFFh

Stack Level 1

Stack Level 8

Reset V ector

Interrupt Vector

On-chip Program

Memory

CALL, RETURN
RETFIE, RETLW

0800h

User Memory

Space

FIGURE 4-2: PIC16C73/73A/74/74A

PROGRAM MEMORY MAP
AND STACK

PC<12:0>

13

0000h

0004h
0005h

07FFh
0800h

0FFFh
1000h

1FFFh

Stack Level 1

Stack Level 8

Reset V ector

Interrupt Vector

On-chip Program

On-chip Program
Memory (Page 1)

Memory (Page 0)

CALL, RETURN
RETFIE, RETLW

User Memory

Space

PIC16C7X

DS30390E-page 20  1997 Microchip Technology Inc.

FIGURE 4-3: PIC16C76/77 PROGRAM

MEMORY MAP AND STACK

PC<12:0>

13

0000h

0004h
0005h

Stack Level 1

Stack Level 8

Reset V ector

Interrupt Vector

CALL, RETURN
RETFIE, RETLW

1FFFh

Stack Level 2

Page 0

Page 1

Page 2

Page 3

07FFh
0800h

0FFFh
1000h

17FFh
1800h

User Memory

Space

On-Chip

On-Chip

On-Chip

On-Chip

4.2 Data Memory Organization

The data memory is partitioned into multiple banks
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1 and RP0 are the
bank select bits.

RP1:RP0 (STATUS<6:5>)
= 00 → Bank0
= 01 → Bank1
= 10 → Bank2
= 11 → Bank3

Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Regis­ters are General Purpose Registers, implemented as
static RAM. All implemented banks contain special
function registers. Some “high use” special function
registers from one bank may be mirrored in another
bank for code reduction and quicker access.

4.2.1 GENERAL PURPOSE REGISTER FILE
The register file can be accessed either directly , or indi-

rectly through the File Select Register FSR
(Section 4.5).

Applicable Devices

72 73 73A 74 74A 76 77

 1997 Microchip Technology Inc. DS30390E-page 21

PIC16C7X

FIGURE 4-4: PIC16C72 REGISTER FILE

MAP

INDF

(1)

TMR0

PCL

STATUS

FSR
PORTA
PORTB
PORTC

PCLATH
INTCON

PIR1

TMR1L
TMR1H
T1CON

TMR2

T2CON

SSPBUF

SSPCON

CCPR1L

CCPR1H

CCP1CON

ADRES

ADCON0

INDF

(1)

OPTION

PCL

STATUS

FSR
TRISA
TRISB

TRISC

PCLATH
INTCON

PIE1

PCON

PR2

SSPADD

SSPSTAT

ADCON1

00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah

0Bh
0Ch
0Dh
0Eh

0Fh

10h

11h
12h
13h
14h
15h
16h
17h
18h
19h

1Ah
1Bh
1Ch
1Dh
1Eh

1Fh

80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh

20h

A0h

General
Purpose
Register

General
Purpose
Register

7Fh

FFh

Bank 0 Bank 1

File

Address

BFh
C0h

Unimplemented data memory locations, read as

'0'.

Note 1: Not a physical register.

File

Address

FIGURE 4-5: PIC16C73/73A/74/74A

REGISTER FILE MAP

INDF

(1)

TMR0

PCL

STATUS

FSR
PORTA
PORTB
PORTC

PORTD

(2)

PORTE

(2)

PCLATH
INTCON

PIR1

PIR2
TMR1L
TMR1H
T1CON

TMR2

T2CON

SSPBUF

SSPCON

CCPR1L

CCPR1H

CCP1CON

RCSTA
TXREG

RCREG

CCPR2L

CCPR2H

CCP2CON

ADRES

ADCON0

INDF

(1)

OPTION

PCL

STATUS

FSR
TRISA
TRISB
TRISC

TRISD

(2)

TRISE

(2)

PCLATH

INTCON

PIE1
PIE2

PCON

PR2

SSPADD

SSPSTAT

TXSTA

SPBRG

ADCON1

00h
01h
02h
03h
04h
05h
06h
07h
08h

09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh

10h

11h
12h
13h
14h
15h
16h
17h
18h
19h

1Ah
1Bh
1Ch
1Dh
1Eh
1Fh

80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh

20h A0h

General
Purpose
Register

General
Purpose
Register

7Fh

FFh

Bank 0 Bank 1

File

Address

File

Address

Unimplemented data memory locations, read as

'0'.

Note 1: Not a physical register.

2: These registers are not physically imple-

mented on the PIC16C73/73A, read as '0'.

PIC16C7X

DS30390E-page 22  1997 Microchip Technology Inc.

FIGURE 4-6: PIC16C76/77 REGISTER FILE MAP

Indirect addr.

(*)

TMR0

PCL

STATUS

FSR

PORTA
PORTB
PORTC

PCLATH

INTCON

PIR1

TMR1L
TMR1H

T1CON

TMR2

T2CON

SSPBUF

SSPCON

CCPR1L

CCPR1H

CCP1CON

OPTION

PCL

STATUS

FSR
TRISA
TRISB
TRISC

PCLATH

INTCON

PIE1

PCON

PR2

SSPADD

SSPSTAT

00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh

80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh

20h

A0h

7Fh

FFh

Bank 0

Bank 1

Unimplemented data memory locations, read as '0'.

* Not a physical register.

Note 1: PORTD, PORTE, TRISD, and TRISE are unimplemented on the PIC16C76, read as '0'.

Note: The upper 16 bytes of data memory in banks 1, 2, and 3 are mapped in Bank 0. This may require

relocation of data memory usage in the user application code if upgrading to the PIC16C76/77.

File

Address

Indirect addr.

(*)

Indirect addr.

(*)

PCL

STATUS

FSR

PCLATH
INTCON

PCL

STATUS

FSR

PCLATH
INTCON

100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
11Fh

180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh

120h

1A0h

17Fh

1FFh

Bank 2

Bank 3

Indirect addr.

(*)

PORTD
PORTE

TRISD
TRISE

TMR0

OPTION

PIR2

PIE2

RCSTA

TXREG

RCREG

CCPR2L

CCPR2H

CCP2CON

ADRES

ADCON0

TXSTA

SPBRG

ADCON1

General
Purpose
Register

General
Purpose
Register

General
Purpose
Register

General
Purpose
Register

1EFh
1F0h

accesses

70h - 7Fh

EFh
F0h

accesses

70h-7Fh

16Fh
170h

accesses

70h-7Fh

General
Purpose
Register

General
Purpose
Register

TRISB

PORTB

96 Bytes

80 Bytes 80 Bytes 80 Bytes

16 Bytes

16 Bytes

(1)

(1)

(1)

(1)

 1997 Microchip Technology Inc. DS30390E-page 23

PIC16C7X

4.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by

the CPU and Peripheral Modules for controlling the
desired operation of the device. These registers are
implemented as static RAM.

The special function registers can be classified into two
sets (core and peripheral). Those registers associated
with the “core” functions are described in this section,
and those related to the operation of the peripheral fea­tures are described in the section of that peripheral fea­ture.

TABLE 4-1: PIC16C72 SPECIAL FUNCTION REGISTER SUMMARY

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Value on all

other resets

(3)

Bank 0

00h

(1)

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu
02h

(1)

PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
03h

(1)

STATUS IRP

(4)

RP1

(4)

RP0 TO PD ZDCC0001 1xxx 000q quuu

04h

(1)

FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
05h PORTA — — PORTA Data Latch when written: PORTA pins when read --0x 0000 --0u 0000
06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu
07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu
08h — Unimplemented — —
09h — Unimplemented — —
0Ah

(1,2)

PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
0Bh

(1)

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 — ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000
0Dh — Unimplemented — —
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
11h TMR2 Timer2 module’s register 0000 0000 0000 0000
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
15h CCPR1L Capture/Compare/PWM Register (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM Register (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
18h — Unimplemented — —
19h — Unimplemented — —
1Ah — Unimplemented — —
1Bh — Unimplemented — —
1Ch — Unimplemented — —
1Dh — Unimplemented — —
1Eh ADRES A/D Result Register xxxx xxxx uuuu uuuu
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 0000 00-0

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.

Shaded locations are unimplemented, read as ‘0’.

Note 1: These registers can be addressed from either bank.

2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose

contents are transferred to the upper byte of the program counter.
3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
4: The IRP and RP1 bits are reserved on the PIC16C72, always maintain these bits clear.

PIC16C7X

DS30390E-page 24  1997 Microchip Technology Inc.

Bank 1

80h

(1)

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
82h

(1)

PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
83h

(1)

STATUS IRP

(4)

RP1

(4)

RP0 TO PD ZDCC0001 1xxx 000q quuu

84h

(1)

FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111
86h TRISB PORTB Data Direction Register 1111 1111 1111 1111
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
88h — Unimplemented — —
89h — Unimplemented — —
8Ah

(1,2)

PCLATH — — — Write Buffer for the upper 5 bits of the PC ---0 0000 ---0 0000
8Bh

(1)

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
8Ch PIE1 — ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000
8Dh — Unimplemented — —
8Eh PCON — — — — — — POR BOR ---- --qq ---- --uu
8Fh — Unimplemented — —
90h — Unimplemented — —
91h — Unimplemented — —
92h PR2 Timer2 Period Register 1111 1111 1111 1111
93h SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000
94h SSPSTAT — — D/A P S R/W UA BF --00 0000 --00 0000
95h — Unimplemented — —
96h — Unimplemented — —
97h — Unimplemented — —
98h — Unimplemented — —
99h — Unimplemented — —
9Ah — Unimplemented — —
9Bh — Unimplemented — —
9Ch — Unimplemented — —
9Dh — Unimplemented — —
9Eh — Unimplemented — —
9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000

TABLE 4-1: PIC16C72 SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Value on all

other resets

(3)

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.

Shaded locations are unimplemented, read as ‘0’.

Note 1: These registers can be addressed from either bank.

2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose

contents are transferred to the upper byte of the program counter.
3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
4: The IRP and RP1 bits are reserved on the PIC16C72, always maintain these bits clear.

 1997 Microchip Technology Inc. DS30390E-page 25

PIC16C7X

TABLE 4-2: PIC16C73/73A/74/74A SPECIAL FUNCTION REGISTER SUMMARY

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Value on all
other resets

(2)

Bank 0

00h

(4)

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu
02h

(4)

PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
03h

(4)

STATUS IRP

(7)

RP1

(7)

RP0 TO PD ZDCC0001 1xxx 000q quuu

04h

(4)

FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
05h PORTA

— — PORTA Data Latch when written: PORTA pins when read --0x 0000 --0u 0000
06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu
07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu
08h

(5)

PORTD PORTD Data Latch when written: PORTD pins when read xxxx xxxx uuuu uuuu

09h

(5)

PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu

0Ah

(1,4)

PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000

0Bh

(4)

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 PSPIF

(3)

ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
0Dh PIR2 — — — – — — — CCP2IF ---- ---0 ---- ---0
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
11h TMR2 Timer2 module’s register 0000 0000 0000 0000
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x
19h TXREG USART Transmit Data Register 0000 0000 0000 0000
1Ah RCREG USART Receive Data Register 0000 0000 0000 0000
1Bh CCPR2L Capture/Compare/PWM Register2 (LSB) xxxx xxxx uuuu uuuu
1Ch CCPR2H Capture/Compare/PWM Register2 (MSB) xxxx xxxx uuuu uuuu
1Dh CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
1Eh ADRES A/D Result Register xxxx xxxx uuuu uuuu
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 0000 00-0

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.

Shaded locations are unimplemented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-

tents are transferred to the upper byte of the program counter.
2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A, always maintain these bits clear.
4: These registers can be addressed from either bank.
5: PORTD and PORTE are not physically implemented on the PIC16C73/73A, read as ‘0’.
6: Brown-out Reset is not implemented on the PIC16C73 or the PIC16C74, read as '0'.
7: The IRP and RP1 bits are reserved on the PIC16C73/73A/74/74A, always maintain these bits clear.

PIC16C7X

DS30390E-page 26  1997 Microchip Technology Inc.

Bank 1

80h

(4)

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
82h

(4)

PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
83h

(4)

STATUS IRP

(7)

RP1

(7)

RP0 TO PD ZDCC0001 1xxx 000q quuu

84h

(4)

FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111
86h TRISB PORTB Data Direction Register 1111 1111 1111 1111
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
88h

(5)

TRISD PORTD Data Direction Register 1111 1111 1111 1111
89h

(5)

TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111
8Ah

(1,4)

PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
8Bh

(4)

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
8Ch PIE1 PSPIE

(3)

ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
8Dh PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0
8Eh PCON — — — — — — POR BOR

(6)

---- --qq ---- --uu

8Fh — Unimplemented — —
90h — Unimplemented — —
91h — Unimplemented — —
92h PR2 Timer2 Period Register 1111 1111 1111 1111
93h SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000
94h SSPSTAT — — D/A P S R/W UA BF --00 0000 --00 0000
95h — Unimplemented — —
96h — Unimplemented — —
97h — Unimplemented — —
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
9Ah — Unimplemented — —
9Bh — Unimplemented — —
9Ch — Unimplemented — —
9Dh — Unimplemented — —
9Eh — Unimplemented — —
9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000

TABLE 4-2: PIC16C73/73A/74/74A SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,
BOR

Value on all

other resets

(2)

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.

Shaded locations are unimplemented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-

tents are transferred to the upper byte of the program counter.
2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A, always maintain these bits clear.
4: These registers can be addressed from either bank.
5: PORTD and PORTE are not physically implemented on the PIC16C73/73A, read as ‘0’.
6: Brown-out Reset is not implemented on the PIC16C73 or the PIC16C74, read as '0'.
7: The IRP and RP1 bits are reserved on the PIC16C73/73A/74/74A, always maintain these bits clear.

 1997 Microchip Technology Inc. DS30390E-page 27

PIC16C7X

TABLE 4-3: PIC16C76/77 SPECIAL FUNCTION REGISTER SUMMARY

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Value on all
other resets

(2)

Bank 0

00h

(4)

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu
02h

(4)

PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
03h

(4)

STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu
04h

(4)

FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
05h PORTA — — PORTA Data Latch when written: PORTA pins when read --0x 0000 --0u 0000
06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu
07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu
08h

(5)

PORTD PORTD Data Latch when written: PORTD pins when read xxxx xxxx uuuu uuuu
09h

(5)

PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu
0Ah

(1,4)

PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
0Bh

(4)

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF

(3)

ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
0Dh PIR2 — — — – — — — CCP2IF ---- ---0 ---- ---0
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
11h TMR2 Timer2 module’s register 0000 0000 0000 0000
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x
19h TXREG USART Transmit Data Register 0000 0000 0000 0000
1Ah RCREG USART Receive Data Register 0000 0000 0000 0000
1Bh CCPR2L Capture/Compare/PWM Register2 (LSB) xxxx xxxx uuuu uuuu
1Ch CCPR2H Capture/Compare/PWM Register2 (MSB) xxxx xxxx uuuu uuuu
1Dh CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
1Eh ADRES A/D Result Register xxxx xxxx uuuu uuuu
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 0000 00-0

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.

Shaded locations are unimplemented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-

tents are transferred to the upper byte of the program counter.
2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the PIC16C76, always maintain these bits clear.
4: These registers can be addressed from any bank.
5: PORTD and PORTE are not physically implemented on the PIC16C76, read as ‘0’.

PIC16C7X

DS30390E-page 28  1997 Microchip Technology Inc.

Bank 1

80h

(4)

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
82h

(4)

PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
83h

(4)

STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu
84h

(4)

FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111
86h TRISB PORTB Data Direction Register 1111 1111 1111 1111
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
88h

(5)

TRISD PORTD Data Direction Register 1111 1111 1111 1111
89h

(5)

TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111
8Ah

(1,4)

PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
8Bh

(4)

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
8Ch PIE1 PSPIE

(3)

ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
8Dh PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0
8Eh PCON — — — — — — POR BOR ---- --qq ---- --uu
8Fh — Unimplemented — —
90h — Unimplemented — —
91h — Unimplemented — —
92h PR2 Timer2 Period Register 1111 1111 1111 1111
93h SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000
94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
95h — Unimplemented — —
96h — Unimplemented — —
97h — Unimplemented — —
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
9Ah — Unimplemented — —
9Bh — Unimplemented — —
9Ch — Unimplemented — —
9Dh — Unimplemented — —
9Eh — Unimplemented — —
9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000

TABLE 4-3: PIC16C76/77 SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Value on all
other resets

(2)

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.

Shaded locations are unimplemented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-

tents are transferred to the upper byte of the program counter.
2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the PIC16C76, always maintain these bits clear.
4: These registers can be addressed from any bank.
5: PORTD and PORTE are not physically implemented on the PIC16C76, read as ‘0’.

 1997 Microchip Technology Inc. DS30390E-page 29

PIC16C7X

Bank 2

100h

(4)

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
101h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu
102h

(4)

PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
103h

(4)

STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu
104h

(4)

FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
105h — Unimplemented — —
106h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu
107h — Unimplemented — —
108h — Unimplemented — —
109h — Unimplemented — —
10Ah

(1,4)

PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
10Bh

(4)

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
10Ch-

10Fh

— Unimplemented — —

Bank 3

180h

(4)

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
181h OPTION RBPU

INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

182h

(4)

PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
183h

(4)

STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu
184h

(4)

FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
185h — Unimplemented — —
186h TRISB PORTB Data Direction Register 1111 1111 1111 1111
187h — Unimplemented — —
188h — Unimplemented — —
189h — Unimplemented — —
18Ah

(1,4)

PCLATH — — —

Write Buffer for the upper 5 bits of the Program Counter

---0 0000 ---0 0000

18Bh

(4)

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
18Ch-

18Fh

— Unimplemented — —

TABLE 4-3: PIC16C76/77 SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Value on all
other resets

(2)

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.

Shaded locations are unimplemented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-

tents are transferred to the upper byte of the program counter.
2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the PIC16C76, always maintain these bits clear.
4: These registers can be addressed from any bank.
5: PORTD and PORTE are not physically implemented on the PIC16C76, read as ‘0’.

PIC16C7X

DS30390E-page 30  1997 Microchip Technology Inc.

4.2.2.1 STATUS REGISTER

The ST ATUS register, shown in Figure 4-7, contains the
arithmetic status of the ALU, the RESET status and the
bank select bits for data memory.

The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the T

O and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.

Applicable Devices

72 73 73A 74 74A 76 77

For example, CLRF STATUS will clear the upper-three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu (where u = unchanged).

It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register because these instructions do not
affect the Z, C or DC bits from the STA TUS register. For
other instructions, not affecting any status bits, see the
"Instruction Set Summary."

Note 1: For those devices that do not use bits IRP

and RP1 (STATUS<7:6>), maintain these
bits clear to ensure upward compatibility
with future products.

Note 2: The C and DC bits operate as a borro

w
and digit borrow bit, respectively, in sub­traction. See the SUBLW and SUBWF
instructions for examples.

FIGURE 4-7: STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h)

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO PD Z DC C R = Readable bit

W = Writable bit
U = Unimplemented bit,
read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: IRP: Register Bank Select bit (used for indirect addressing)

1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)

bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)

11 = Bank 3 (180h - 1FFh)
10 = Bank 2 (100h - 17Fh)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)

Each bank is 128 bytes

bit 4: T

O: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred

bit 3: PD

: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction

bit 2: Z: Zero bit

1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero

bit 1: DC: Digit carry/borro

w bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result

bit 0: C: Carry/borro

w bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
Note: For borro

w the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of
the source register.