Microchip Technology Inc MCP3421 Datasheet

MCP3421

1 8 - Bi t A na l o g -t o - D ig i t a l C o n v er t e r

with I2C Interface and On-Board Reference

Features

• 18-bit ΔΣ ADC in a SOT-23-6 package

• Differential input operation

• Self calibration of Internal Offset and Gain per each conversion

• On-board Voltage Reference:

- Accuracy: 2.048V ± 0.05%

- Drift: 5 ppm/°C

• On-board Programmable Gain Amplifier (PGA):

- Gains of 1,2,4 or 8

• On-board Oscillator

• INL: 10 ppm of FSR (FSR = 4.096V/PGA)

• Programmable Data Rate Options:

- 3.75 SPS (18 bits)

- 15 SPS (16 bits)

- 60 SPS (14 bits)

- 240 SPS (12 bits)

• One-Shot or Continuous Conversion Options

• Low current consumption:

- 145 µA typical

= 3V, Continuous Conversion)

- 39 µA typical

= 3V, One-Shot Conversion with 1 SPS)

• Supports I2C Serial Interface:

- Standard, Fast and High Speed Modes

• Single Supply Operation: 2.7V to 5.5V

• Extended Temperature Range: -40°C to 125°C

Typical Applications

Description

The MCP3421 is a single channel low-noise, high accuracy ΔΣ A/D converter with differential inputs and up to 18 bits of resolution in a small SOT-23-6 package. The on-board precision 2.048V reference voltage enables an input range of ±2.048V differentially (Δ voltage = 4.096V). The device uses a two-wire I compatible serial interface and operates from a single

2.7V to 5.5V power supply.

The MCP3421 device performs conversion at rates of

3.75, 15, 60, or 240 samples per second (SPS) depending on the user controllable configuration bit settings using the two-wire I device has an on-board programmable gain amplifier (PGA). The user can select the PGA gain of x1, x2, x4, or x8 before the analog-to-digital conversion takes place. This allows the MCP3421 device to convert a smaller input signal with high resolution. The device has two conversion modes: (a) Continuous mode and (b) One-Shot mode. In One-Shot mode, the device enters a low current standby mode automatically after one conversion. This reduces current consumption greatly during idle periods.

The MCP3421 device can be used for various high accuracy analog-to-digital data conversion applications where design simplicity, low power, and small footprint are major considerations.

C serial interface. This

Block Diagram

• Portable Instrumentation

• Weigh Scales and Fuel Gauges

• Temperature Sensing with RTD, Thermistor, and Thermocouple

• Bridge Sensing for Pressure, Strain, and Force.

Package Types

Top View

SDA

SOT-23-6

VIN+

SCL

Gain = 1, 2, 4, or 8

VIN+

PGA

VIN-

Voltage Reference

(2.048V)

REF

ΔΣ ADC

Converter

C Interface

SCL

SDA

Clock

Oscillator

MCP3421

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings†

VDD...................................................................................7.0V

All inputs and outputs w.r.t V

Differential Input Voltage ...................................... |V

Output Short Circuit Current ................................. Continuous

Current at Input Pins ....................................................±2 mA

Current at Output and Supply Pins ............................±10 mA

Storage Temperature.....................................-65°C to +150°C

Ambient Temp. with power applied ...............-55°C to +125°C

ESD protection on all pins ................ ≥ 6kV HBM, ≥ 400V MM

Maximum Junction Temperature (T

............... –0.3V to VDD+0.3V

) ..........................+150°C

- VSS|

†Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability

ELECTRICAL CHARACTERISTICS

Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +85°C, VDD = +5.0V, VSS = 0V,

+ = VIN- = V

Parameters Sym Min Typ Max Units Conditions

Analog Inputs

Differential Input Range — ±2.048/PGA — V V

Common-Mode Voltage Range (absolute)

Differential Input Impedance

(Note 2)

Common Mode input Impedance

System Performance

Resolution and No Missing

(Note 8)

Codes

Data Rate

Output Noise — 1.5 — µV

Note 1: Any input voltage below or greater than this voltage causes leakage current through the ESD diodes at the input pins.

2: This input impedance is due to 3.2 pF internal input sampling capacitor. 3: The total conversion speed includes auto-calibration of offset and gain. 4: INL is the difference between the endpoints line and the measured code at the center of the quantization band. 5: Includes all errors from on-board PGA and V 6: Full Scale Range (FSR) = 2 x 2.048/PGA = 4.096/PGA. 7: This parameter is ensured by characterization and not 100% tested. 8: This parameter is ensured by design and not 100% tested.

/2. All ppm units use 2*V

REF

(Note 1)

IND

INC

(Note 3)

This parameter is ensured by characterization and not 100% tested.

DR 176 240 328 SPS S1,S0 = ‘00’, (12 bits mode)

as full-scale range.

REF

VSS-0.3 — VDD+0.3 V

(f) — 2.25/PGA — MΩ During normal mode operation

(f) — 25 — MΩ PGA = 1, 2, 4, 8

12 — — Bits DR = 240 SPS

14 — — Bits DR = 60 SPS

16 — — Bits DR = 15 SPS

18 — — Bits DR = 3.75 SPS

44 60 82 SPS S1,S0 = ‘01’, (14 bits mode)

11 15 20.5 SPS S1,S0 = ‘10’, (16 bits mode)

2.75 3.75 5.1 SPS S1,S0 = ‘11’, (18 bits mode)

REF

RMSTA

PGA = 1, V

= VIN+ - VIN-

= 25°C, DR = 3.75 SPS,

= 0

MCP3421

ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +85°C, VDD = +5.0V, VSS = 0V,

+ = VIN- = V

Parameters Sym Min Typ Max Units Conditions

Integral Nonlinearity

Internal Reference Voltage V

Gain Error

PGA Gain Error Match

Gain Error Drift

Offset Error V

Offset Drift vs. Temperature — 50 — nV/°C V

Common-Mode Rejection — 105 — dB at DC and PGA =1,

Gain vs. V

Power Supply Rejection at DC — 100 — dB T

Power Requirements

Voltage Range V

Supply Current during Conversion

Supply Current during Standby Mode

C Digital Inputs and Digital Outputs

High level input voltage V

Low level input voltage V

Low level output voltage V

Hysteresis of Schmitt Trigger for inputs

(Note 7)

Supply Current when I line is active

Input Leakage Current I

Pin Capacitance and I

Pin capacitance C

C Bus Capacitance C

Thermal Characteristics

Specified Temperature Range T

Operating Temperature Range T

Storage Temperature Range T

Note 1: Any input voltage below or greater than this voltage causes leakage current through the ESD diodes at the input pins.

/2. All ppm units use 2*V

REF

(Note 4)

(Note 5)

INL — 10 35

REF

as full-scale range.

REF

— 2.048 — V

— 0.05 0.35 % PGA = 1, DR = 3.75 SPS

— 0.1 — % Between any 2 PGA gains

— 5 40 ppm/°C PGA=1, DR=3.75 SPS

— 15 40 µV Tested at PGA = 1

— 110 — dB at DC and PGA =8,

— 5 — ppm/V TA = +25°C, VDD = 2.7V to 5.5V,

2.7 — 5.5 V

— 155 190 µA V

DDA

— 145 — µA V

DDS

HYST

C bus

C Bus Capacitance

DDB

ILH

ILL

—0.1 0.5µA

0.7 V

—VDDV

— — 0.3V

—— 0.4VI

0.05V

——Vf

—— 10µA

—— 1 µAV

-1 — — µA VIL = GND

— — 10 pF

— — 400 pF

-40 — +85 °C

-40 — +125 °C

-65 — +150 °C

This parameter is ensured by characterization and not 100% tested.

REF

ppm of

FSR

DR = 3.75 SPS

(Note 6)

= 5.0V and DR = 3.75 SPS

DD DD = 5.0V

= +25°C

PGA = 1

= +25°C, VDD = 2.7V to 5.5V,

PGA = 1

= 5.0V

= 3.0V

= 3 mA, VDD = +5.0V

= 100 kHz

SCL

= 5.5V

MCP3421

2.0 TYPICAL PERFORMANCE CURVES

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise indicated, TA = -40°C to +85°C, VDD = +5.0V, VSS = 0V, VIN+ = VIN- = V

.005

.004

.003

.002

.001

.000

Integral Nonlinearity (% of FSR)

PGA = 4

PGA = 1

2.5 3 3.5 4 4.5 5 5.5

PGA = 8

PGA = 2

(V)

FIGURE 2-1: INL vs. Supply Voltage (V

0.003

PGA = 1

0.002

VDD = 5 V

0.001

(% of FSR)

Integral Nonlinearity

-60 -40 -20 0 20 40 60 80 100 120 140

Temperature (oC)

VDD = 2.7V

10.0

TA = +25°C V

= 5V

7.5

5.0

Noise (µV, rms)

2.5

0.0

-100 -75 -50 -25 0 25 50 75 100

Input Voltage (% of Full-Scale)

PGA = 8

FIGURE 2-4: Noise vs. Input Voltage.

3.0

2.0

1.0

0.0

-1.0

Total Error (mV)

-2.0

-3.0

-100 -75 -50 -25 0 25 50 75 100

Input Voltage (% of Full-Scale)

PGA = 1 PGA = 2 PGA = 4 PGA = 8

REF

PGA = 2

PGA = 4

/2.

PGA = 1

FIGURE 2-2: INL vs. Temperature.

-5

PGA = 1

-10

Offset Error (µV)

-15

-20

-60 -40 -20 0 20 40 60 80 100 120 140

PGA = 4

PGA = 2

Temperature (°C)

PGA = 8

VDD = 5V

FIGURE 2-3: Offset Error vs. Temperature.

FIGURE 2-5: Total Error vs. Input Voltage.

0.4

0.3

0.2

0.1

-0.1

-0.2

Gain Error (% of FSR)

-0.3

-0.4

-60 -40 -20 0 20 40 60 80 100 120 140

PGA = 1

PGA = 2

Temperature (°C)

VDD = 5.0V

PGA = 4

PGA = 8

FIGURE 2-6: Gain Error vs. Temperature.

MCP3421

Note: Unless otherwise indicated, TA = -40°C to +85°C, VDD = +5.0V, VSS = 0V, VIN+ = VIN- = V

220

200

180

(µA)

160

DDA

140

120

100

-60 -40 -20 0 20 40 60 80 100 120 140

FIGURE 2-7: I

600

500

400

(nA)

300

DDS

200

100

-60 -40 -20 0 20 40 60 80 100 120 140

VDD = 5V

Temperature (oC)

vs. Temperature.

DDA

VDD = 5V

Temperature (

VDD = 2.7V

VDD= 2.7V

VDD = 2.7V

Oscillator Drift (%)

VDD = 5.0V

-1

-60 -40 -20 0 20 40 60 80 100 120 140

Temperature (°C)

FIGURE 2-10: OSC Drift vs. Temperature.

-10

-20

-30

-40

-50

-60

-70

-80

Magnitude (dB)

-90

-100

-110

-120

0.1 1 10 100 1000 10000

0.1 1 10 100 1k 10k

Input Signal Frequency (Hz)

/2.

REF

Data Rate = 3.75 SPS

FIGURE 2-8: I

VDD = 5V

VDD = 4.5V

VDD = 3.3V

(

DDB

VDD = 2.7V

-60 -40 -20 0 20 40 60 80 100 120 140

FIGURE 2-9: I

vs. Temperature.

DDS

Temperature (

vs. Temperature.

DDB

FIGURE 2-11: Frequency Response.

MCP3421

3.0 PIN DESCRIPTIONS

TABLE 3-1: PIN FUNCTION TABLE

Pin No Sym Function

2VSSGround Pin

3SCL

4SDA

+ Non-Inverting Analog Input Pin

Serial Clock Input Pin of the I2C Interface

Bidirectional Serial Data Pin of the I2C Interface

Positive Supply Voltage Pin

- Inverting Analog Input Pin

3.1 Analog Inputs (VIN+, VIN-)

VIN+ and VIN- are differential signal input pins. The MCP3421 device accepts a fully differential analog input signal which is connected on the V

+ and VIN-

input pins. The differential voltage that is converted is defined by V

= (VIN+ - VIN-) where VIN+ is the voltage

applied at the VIN+ pin and VIN- is the voltage applied at the V

- pin. The input signal level is amplified by the

programmable gain amplifier (PGA) before the conversion. The differential input voltage should not exceed an absolute of (2* V measurement, where V

REF

/PGA) for accurate

REF

is the internal reference voltage (2.048V) and PGA is the PGA gain setting. The converter output code will saturate if the input range exceeds (2* V

REF

/PGA).

The absolute voltage range on each of the differential input pins is from V

-0.3V to VDD+0.3V. Any voltage

above or below this range will cause leakage currents through the Electrostatic Discharge (ESD) diodes at the input pins. This ESD current can cause unexpected performance of the device. The common mode of the analog inputs should be chosen such that both the differential analog input range and the absolute voltage range on each pin are within the specified operating range defined in Section 1.0 “Electrical

Characteristics” and Section 4.0 “Description of Device Operation”.

3.2 Supply Voltage (VDD, VSS)

VDD is the power supply pin for the device. This pin requires an appropriate bypass capacitor of about

0.1 µF (ceramic) to ground. An additional 10 µF capacitor (tantalum) in parallel is also recommended to further attenuate high frequency noise present in some application boards. The supply voltage (V must be maintained in the 2.7V to 5.5V range for specified operation.

is the ground pin and the current return path of the

device. The user must connect the V

pin to a ground

plane through a low impedance connection. If an analog ground path is available in the application PCB (printed circuit board), it is highly recommended that

the V

pin be tied to the analog ground path or

isolated within an analog ground plane of the circuit board.

3.3 Serial Clock Pin (SCL)

SCL is the serial clock pin of the I2C interface. The MCP3421 acts only as a slave and the SCL pin accepts only external serial clocks. The input data from the Master device is shifted into the SDA pin on the rising edges of the SCL clock and output from the MCP3421 occurs at the falling edges of the SCL clock. The SCL pin is an open-drain N-channel driver. Therefore, it needs a pull-up resistor from the V to the SCL pin. Refer to Section 5.3 “I2C Serial Communications” for more details of I

C Serial Interface

line

communication.

3.4 Serial Data Pin (SDA)

SDA is the serial data pin of the I2C interface. The SDA pin is used for input and output data. In read mode, the conversion result is read from the SDA pin (output). In write mode, the device configuration bits are written (input) though the SDA pin. The SDA pin is an opendrain N-channel driver. Therefore, it needs a pull-up resistor from the V start and stop conditions, the data on the SDA pin must be stable during the high period of the clock. The high or low state of the SDA pin can only change when the clock signal on the SCL pin is low. Refer to Section 5.3

C Serial Communications” for more details of I2C

“I

Serial Interface communication.

)

line to the SDA pin. Except for

MCP3421

4.0 DESCRIPTION OF DEVICE OPERATION

4.1 General Overview

The MCP3421 is a low-power, 18-Bit Delta-Sigma A/D converter with an I2C serial interface. The device contains an on-board voltage reference (2.048V), programmable gain amplifier (PGA), and internal oscillator. The user can select 12, 14, 16, or 18 bit conversion by setting the configuration register bits. The device can be operated in Continuous Conversion or One-Shot Conversion mode. In the Continuous Conversion mode, the device converts the inputs continuously. While in the One-Shot Conversion mode, the device converts the input one time and stays in the low-power standby mode until it receives another command for a new conversion. During the standby mode, the device consumes less than 0.1 µA typical.

4.2 Power-On-Reset (POR)

The device contains an internal Power-On-Reset (POR) circuit that monitors power supply voltage (VDD) during operation. This circuit ensures correct device start-up at system power-up and power-down events. The POR has built-in hysteresis and a timer to give a high degree of immunity to potential ripples and noises on the power supply. A 0.1 µF decoupling capacitor should be mounted as close as possible to the V for additional transient immunity.

The threshold voltage is set at 2.2V with a tolerance of approximately ±5%. If the supply voltage falls below this threshold, the device will be held in a reset condition. The typical hysteresis value is approximately 200 mV.

The POR circuit is shut-down during the low-power standby mode. Once a power-up event has occurred, the device requires additional delay time (approximately 300 µs) before a conversion can take place. During this time, all internal analog circuitries are settled before the first conversion occurs. Figure 4-1 illustrates the conditions for power-up and power-down events under typical start-up conditions.

When the device powers up, it automatically resets and sets the configuration bits to default settings. The default configuration bit conditions are a PGA gain of 1 V/V and a conversion speed of 240 SPS in Continuous Conversion mode. When the device receives an I

C General Call Reset command, it performs an internal reset similar to a Power-On-Reset event.

2.2V

2.0V

300 µS

Reset

Start-up

Normal Operation

Reset

Time

FIGURE 4-1: POR Operation.

4.3 Internal Voltage Reference

The device contains an on-board 2.048V voltage reference. This reference voltage is for internal use only and not directly measurable. The specifications of the reference voltage are part of the device’s gain and drift specifications. Therefore, there is no separate specification for the on-board reference.

4.4 Analog Input Channel

The differential analog input channel has a switched capacitor structure. The internal sampling capacitor (3.2 pF) is charged and discharged to process a conversion. The charging and discharging of the input sampling capacitor creates dynamic input currents at the V

+ and VIN- input pins, which is inversely

proportional to the internal sampling capacitor and internal frequency. The current is also a function of the differential input voltages. Care must be taken in setting the common-mode voltage and input voltage ranges so that the input limits do not exceed the ranges specified in Section 1.0 “Electrical Characteristics”.

4.5 Digital Output Code

The digital output code produced by the MCP3421 is a function of PGA gain, input signal, and internal reference voltage. In a fixed setting, the digital output code is proportional to the voltage difference between the two analog inputs.

The output data format is a binary two’s complement. With this code scheme, the MSB can be considered a sign indicator. When the MSB is a logic ‘0’, it indicates a positive value. When the MSB is a logic ‘1’, it indicates a negative value. The following is an example of the output code:

(a) for a negative full-scale input voltage: 100...000

(b) for a zero differential input voltage: 000...000

The MSB is always transmitted first through the serial port. The number of data bits for each conversion is 18, 16, 14, or 12 bits depending on the conversion mode selection.

MCP3421

The output codes will not roll-over if the input voltage exceeds the maximum input range. In this case, the code will be locked at 0111...11 for all voltages greater than +(V voltages less than -V of output codes of various input levels using 18 bit conversion mode. Ta bl e 4 -3 shows an example of minimum and maximum codes for each data rate option.

The output code is given by:

- 1 LSB) and 1000...00 for

REF

. Ta ble 4 - 2 shows an example

REF

EQUATION 4-1:

VIN+VIN-–()

Output Code Max Code 1+()

The LSB of the code is given by:

---------------------------------------

×=

2.048V

EQUATION 4-2:

LSB

Where:

N = the number of bits

2 2.048V

--------------------------=

TABLE 4-1: LSB SIZE OF VARIOUS BIT

CONVERSION MODES

Bit Resolutions LSB (V)

12 bits 1 mV

14 bits 250 µV

16 bits 62.5 µV

18 bits 15.625 µV

TABLE 4-2: EXAMPLE OF OUTPUT CODE

FOR 18 BITS

Input Voltage (V) Digital Code

≥ V

REF

- 1 LSB 011111111111111111

REF

2LSB 000000000000000010

1LSB 000000000000000001

0 000000000000000000

-1 LSB 111111111111111111

-2 LSB 111111111111111110

- V

REF

< -V

REF

011111111111111111

100000000000000000

TABLE 4-3: MINIMUM AND MAXIMUM

CODES

Number

of Bits

12 240 SPS -2048 2047

14 60 SPS -8192 8191

16 15 SPS -32768 32767

18 3.75 SPS -131072 131071

Note: Maximum n-bit code = 2

Data Rate

Minimum n-bit code = -1 x 2

Minimum

Code

n-1

- 1

Maximum

Code

n-1

4.6 Self-Calibration

The device performs a self-calibration of offset and gain for each conversion. This provides reliable conversion results from conversion-to-conversion over variations in temperature as well as power supply fluctuations.

4.7 Input Impedance

The MCP3421 uses a switched-capacitor input stage using a 3.2 pF sampling capacitor. This capacitor is switched (charged and discharged) at a rate of the sampling frequency that is generated by the on-board clock. The differential mode impedance varies with the PGA settings. The typical differential input impedance during a normal mode operation is given by:

ZIN(f) = 2.25 MΩ/PGA

Since the sampling capacitor is only switching to the input pins during a conversion process, the above input impedance is only valid during conversion periods. In a low power standby mode, the above impedance is not presented at the input pins. Therefore, only a leakage current due to ESD diode is presented at the input pins.

The conversion accuracy can be affected by the input signal source impedance when any external circuit is connected to the input pins. The source impedance adds to the internal impedance and directly affects the time required to charge the internal sampling capacitor. Therefore, a large input source impedance connected to the input pins can increase the system performance errors such as offset, gain, and integral nonlinearity (INL) errors. Ideally, the input source impedance should be zero. This can be achievable by using an operational amplifier with a closed-loop output impedance of tens of ohms.

4.8 Aliasing and Anti-aliasing Filter

Aliasing occurs when the input signal contains timevarying signal components with frequency greater than half the sample rate. In the aliasing conditions, the device can output unexpected output codes. For applications that are operating in electrical noise environments, the time-varying signal noise or high frequency interference components can be easily added to the input signals and cause aliasing. Although the MCP3421 device has an internal first order sinc filter, its’ filter response may not give enough attenuation to all aliasing signal components. To avoid the aliasing, an external anti-aliasing filter, which can be accomplished with a simple RC low-pass filter, is typically used at the input pins. The low-pass filter cuts off the high frequency noise components and provides a band-limited input signal to the MCP3421 input pins.

MCP3421

+ 21 hidden pages

Microchip Technology Inc MCP3421 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

1.0 ELECTRICAL CHARACTERISTICS

FIGURE 2-4: Noise vs. Input Voltage.

FIGURE 2-2: INL vs. Temperature.

FIGURE 2-3: Offset Error vs. Temperature.

FIGURE 2-5: Total Error vs. Input Voltage.

FIGURE 2-6: Gain Error vs. Temperature.

FIGURE 2-10: OSC Drift vs. Temperature.

FIGURE 2-11: Frequency Response.

3.0 PIN DESCRIPTIONS

4.0 DESCRIPTION OF DEVICE OPERATION

FIGURE 4-1: POR Operation.