Microchip Technology Inc 93LC66XT-I-SN, 93LC66XT-SN, 93LC66X-I-SN, 93LC66X-SN, 93LC66T-I-SM Datasheet

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1997 Microchip Technology Inc. DS11168L-page 1

93LC46/56/66

FEATURES

• Single supply with programming operation down to 2.0V (Commercial only)

• Low power CMOS technology

- 1 mA active current typical

-5 µ A standby current (typical) at 3.0V

• ORG pin selectable memory conﬁguration

- 128 x 8 or 64 x 16-bit organization (93LC46)

- 256 x 8 or 128 x 16-bit organization(93LC56)

- 512 x 8 or 256 x 16-bit organization(93LC66)

• Self-timed ERASE and WRITE cycles (including auto-erase)

• Automatic ERAL before WRAL

• Power on/off data protection circuitry

• Industry standard 3-wire serial I/O

• Device status signal during ERASE/WRITE cycles

• Sequential READ function

• 10,000,000 ERASE/WRITE cycles guaranteed on 93LC56 and 93LC66

• 1,000,000 E/W cycles guaranteed on 93LC46

• Data retention > 200 years

• 8-pin PDIP/SOIC and 14-pin SOIC package (SOIC in JEDEC and EIAJ standards)

• Temperature ranges supported

BLOCK DIAGRAM

DESCRIPTION

The Microchip Technology Inc. 93LC46/56/66 are 1K, 2K, and 4K low-voltage serial Electrically Erasable PROMs. The device memory is conﬁgured as x8 or x16 bits, depending on the ORG pin setup. Advanced CMOS technology makes these devices ideal for low-power, nonvolatile memory applications. The 93LC46/56/66 is available in standard 8-pin DIP and 8/ 14-pin surface mount SOIC packages. The 93LC46X/ 56X/66X are only offered in an “SN” package.

PACKA GE TYPES

- Commercial (C): 0 ° C to +70 ° C

- Industrial (I): -40 ° C to +85 ° C

MEMORY

ARRAY

ADDRESS DECODER

CC VSS

DATA REGISTER

MODE

DECODE

LOGIC

CLOCK

GENERATOR

OUTPUT BUFFER

CLK

ADDRESS COUNTER

DIP

SOIC

93LC46

93LC56

93LC66

93LC46

93LC56

93LC66

93LC46X

93LC56X

93LC66X

93LC56

93LC66

SOIC

CLK

ORG V

CLK

ORG V

CLK

NU ORG

NC CS

CLK

Vcc NU

ORG

3 4

6 5

1 2 3 4

8 7 6 5

1 2 3 4

8 7 6 5

1 2 3 4

14 13 12 11

5 6 7

9 8

1K/2K/4K 2.0V Microwire

Serial EEPROM

93LC46/56/66

DS11168L-page 2

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1997 Microchip Technology Inc.

1.0 ELECTRICAL CHARACTERISTICS

1.1 Maxim

um Ratings*

Vcc...................................................................................7.0V

All inputs and outputs w.r.t. V

...............-0.6V to Vcc +1.0V

Storage temperature..................................... -65˚C to +150˚C

Ambient temp. with power applied................. -65˚C to +125˚C

Soldering temperature of leads (10 seconds)............. +300˚C

ESD protection on all pins................................................4 kV

*Notice: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this speciﬁcation is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

PIN function Table

TABLE 1-1 DC AND AC ELECTRICAL CHARACTERISTICS

Name Function

CS Chip Select

CLK Serial Data Clock

DI Serial Data Input

DO Serial Data Output

Ground

ORG Memory Conﬁguration

NU Not Utilized NC No Connect

Power Supply

Commercial (C): Vcc = +2.0V to +6.0V (C): Tamb = 0˚C to +70˚C Industrial (I): Vcc = +2.5V to +6.0V (I): Tamb = -40˚C to +85˚C

Parameter Symbol Min. Max. Units Conditions

High level input voltage

IH1

2.0 Vcc +1 V V

≥

2.7V

IH2

0.7 Vcc Vcc +1 V V

< 2.7V

Low level input voltage

IL1

-0.3 0.8 V V

≥

2.7V

IL2

-0.3 0.2 Vcc V V

< 2.7V

Low level output voltage

OL1

— 0.4 V I

= 2.1 mA; Vcc = 4.5V

OL2

— 0.2 V I

=100 µ A; Vcc = Vcc Min.

High level output voltage

OH1

2.4 — V I

= -400 µ A; Vcc = 4.5V

OH2

Vcc-0.2 — V I

= -100 µ A; Vcc = Vcc Min.

Input leakage current I

-10 10

A V

= 0.1V to Vcc

Output leakage current I

-10 10

A V

OUT

= 0.1V to Vcc Pin capacitance (all inputs/outputs)

, C

OUT

— 7 pF V

OUT

= 0 V (Notes 1 & 3)

Tamb = +25 ° C, F

CLK

= 1 MHz

Operating current

read — 1

500

CLK

= 2 MHz; Vcc = 6.0V

CLK

= 1 MHz; Vcc = 3.0V

write — 3 mA F

CLK

= 2 MHz; Vcc = 6.0V (Note 3)

Standby current

CCS

— 100

µ A µ

CLK = CS = 0V; Vcc = 6.0V CLK = CS = 0V; Vcc = 3.0V

Clock frequency

CLK

— 2

MHz MHz

Vcc ≥ 4.5V Vcc < 4.5V

Clock high time T

CKH

250 — ns

Clock low time T

CKL

250 — ns

Chip select setup time T

CSS

50 — ns Relative to CLK

Chip select hold time T

CSH

0 — ns Relative to CLK

Chip select low time T

CSL

250 — ns

Data input setup time T

DIS

100 — ns Relative to CLK

Data input hold time T

DIH

100 — ns Relative to CLK

Data output delay time T

— 400 ns C

= 100 pF

Data output disable time T

— 100 ns C

= 100 pF (Note 3)

Status valid time T

— 500 ns C

= 100 pF

Program cycle time

— 10 ms ERASE/WRITE mode (Note 2)

— 15 ms ERAL mode

— 30 ms WRAL mode

Endurance

93LC46 93LC56/66

— —

10M

— —

cycles 25 ° C, Vcc = 5.0V, Block Mode (Note 4)

Note 1: This parameter is tested at Tamb = 25˚C and F

CLK

= 1 MHz. 2: Typical program cycle time is 4 ms per word. 3: This parameter is periodically sampled and not 100% tested. 4: This application is not tested but guaranteed by characterization. For endurance estimates in a speciﬁc applica-

tion, please consult the Total Endurance Model which can be obtained on our BBS or website.

93LC46/56/66

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1997 Microchip Technology Inc. DS11168L-page 3

2.0 PIN DESCRIPTION

2.1 Chip Select (CS)

A high level selects the de vice. A low le vel deselects the device and forces it into standb y mode. Howev er , a programming cycle which is already initiated and/or in progress will be completed, regardless of the CS input signal. If CS is brought low during a progr am cycle, the device will go into standby mode as soon as the programming cycle is completed.

CS must be low for 250 ns minimum (T

CSL

) between consecutive instructions. If CS is low, the internal control logic is held in a RESET status.

2.2 Serial Cloc

k (CLK)

The Serial Clock (CLK) is used to synchronize the communication between a master device and the 93LCXX. Opcodes, addresses, and data bits are clocked in on the positive edge of CLK. Data bits are also clock ed out on the positive edge of CLK.

CLK can be stopped anywhere in the transmission sequence (at high or low level) and can be continued anytime with respect to clock high time (T

CKH

) and

clock low time (T

CKL

). This gives the controlling master

freedom in preparing the opcode, address, and data. CLK is a “Don't Care” if CS is low (device deselected).

If CS is high, but the START condition has not been detected, any number of clock cycles can be received by the device without changing its status (i.e., waiting for a START condition).

CLK cycles are not required during the self-timed WRITE (i.e., auto ERASE/WRITE) cycle.

After detecting a START condition, the speciﬁed number of clock cycles (respectively low to high transitions of CLK) must be provided. These clock cycles are required to clock in all required opcodes, addresses, and data bits before an instruction is executed (Table 2-1 to Table 2-6). CLK and DI then become don't care inputs waiting for a new START condition to be detected.

2.3 Data In (DI)

Data In (DI) is used to clock in a START bit, opcode, address, and data synchronously with the CLK input.

2.4 Data Out (DO)

Data Out (DO) is used in the READ mode to output data synchronously with the CLK input (T

after the posi-

tive edge of CLK). This pin also provides READ Y/B USY status inf ormation

during ERASE and WRITE cycles. READY/B

USY status information is available on the DO pin if CS is brought high after being low for minimum chip select low time (T

CSL

) and an ERASE or WRITE operation has

been initiated. The status signal is not available on DO, if CS is held

low or high during the entire WRITE or ERASE cycle. In all other cases DO is in the HIGH-Z mode. If status is checked after the ERASE/WRITE cycle, a pull-up resistor on DO is required to read the READY signal.

2.5 Or

ganization (ORG)

When ORG is tied to V

, the (x8) memory organization is selected. When ORG is connected to Vcc or ﬂoated, the (x16) memory organization is selected. ORG can only be ﬂoated for clock speeds of 1 MHz or less for the (X16) memory organization. For clock speeds greater than 1 MHz, ORG must be tied to Vcc or V

Note: CS must go low between consecutive

instructions.

93LC46/56/66

DS11168L-page 4

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1997 Microchip Technology Inc.

TABLE 2-1 INSTRUCTION SET FOR 93LC46: ORG = 0 (X 8 ORGANIZATION)

TABLE 2-2 INSTRUCTION SET FOR 93LC46: ORG = 1 (X 16 ORGANIZATION)

TABLE 2-3 INSTRUCTION SET FOR 93LC56: ORG = 0 (X 8 ORGANIZATION)

TABLE 2-4 INSTRUCTION SET FOR 93LC56: ORG = 1 (X 16 ORGANIZATION)

TABLE 2-5 INSTRUCTION SET FOR 93LC66: ORG = 0 (X 8 ORGANIZATION)

TABLE 2-6 INSTRUCTION SET FOR 93LC66: ORG = 1 (X 16 ORGANIZATION)