Microchip Technology Inc 24C32AT-E-SM, 24C32AT-E-P, 24C32AT-SN, 24C32AT-SM, 24C32AT-P Datasheet
...
C
24C32A
2
32K 5.0V I
C
Serial EEPROM
FEATURES
• Voltage operating range: 4.5V to 5.5V
- Maximum write current 3 mA at 5.5V
- Standby current 1 µ A typical at 5.0V
• 2-wire serial interface bus, I
• 100 kHz and 400 kHz compatibility
• Self-timed ERASE and WRITE cycles
• Power on/off data protection circuitry
• Hardware write protect
• 1,000,000 Erase/Write cycles guaranteed
• 32-byte page or byte write modes available
• Schmitt trigger filtered inputs for noise suppression
• Output slope control to eliminate ground bounce
• 2 ms typical write cycle time, byte or page
• Up to eight devices may be connected to the
same bus for up to 256K bits total memory
• Electrostatic discharge protection > 4000V
• Data retention > 200 years
• 8-pin PDIP and SOIC packages
• Temperature ranges
- Commercial (C): 0˚C to 70˚C
- Industrial (I): -40˚C to +85˚C
- Automotive (E): -40˚C to +125˚C
2
compatible
DESCRIPTION
P ACKA GE TYPES
PDIP
1
A0
2
A1
3
A2
Vss
SOIC
A0
A1
A2
Vss
4
1
2
3
4
24C32A
24C32A
8
Vcc
7
WP
6
SCL
5
SDA
8
7
6
5
Vcc
WP
SCL
SDA
The Microchip T echnology Inc. 24C32A is a 4K x 8 (32K
bit) Serial Electrically Erasable PROM. It has been
developed for advanced, low power applications such
as personal communications or data acquisition. The
24C32A also has a page-write capability of up to 32
bytes of data. The 24C32A is capable of both random
and sequential reads up to the 32K boundary. Functional address lines allow up to eight 24C32A devices
on the same bus, for up to 256K bits address space.
Advanced CMOS technology and broad voltage range
make this device ideal for low-power/low-voltage, nonvolatile code and data applications. The 24C32A is
available in the standard 8-pin plastic DIP and both 150
mil and 200 mil SOIC packaging.
2
I
C is a trademark of Philips Corporation.
BLOCK DIAGRAM
WP
MEMORY
CONTROL
LOGIC
WP
CONTROL
LOGIC
I/O
SDA
VCC
VSS
A0..A2
I/O
SCL
XDEC
HV GENERATOR
EEPROM
ARRAY
PAGE LATCHES
YDEC
SENSE AMP
R/W CONTROL
1996 Microchip Technology Inc.
Preliminary
DS21163B-page 1
24C32A
µ
µ
1.0 ELECTRICAL
TABLE 1-1: PIN FUNCTION TABLE
CHARACTERISTICS
1.1 Maxim
CC
V
...................................................................................7.0V
All inputs and outputs w.r.t. V
Storage temperature.....................................-65˚C to +150˚C
Ambient temp. with power applied................-65˚C to +125˚C
Soldering temperature of leads (10 seconds).............+300˚C
ESD protection on all pins ..................................................≥ 4 kV
*Notice: Stresses above those listed under “Maximum Ratings”
may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-2: DC CHARACTERISTICS
Vcc = +4.5V to 5.5V
Commercial (C): Tamb = 0 ° C to +70 ° C
Industrial (I): Tamb = -40 ° C to +85 ° C
Automotive(E): Tamb = -40 ° C to +125 ° C
A0, A1, A2, SCL , SDA and WP
pins:
High level input voltage V
Low level input voltage V
Hysteresis of Schmitt Trigger
inputs
Low level output voltage V
Input leakage current I
Output leakage current I
Pin capacitance
(all inputs/outputs)
Operating current I
Standby current I
Note: This parameter is periodically sampled and not 100% tested.
um Ratings*
SS
............... -0.6V to V
Parameter Symbol Min Typ Max Units Conditions
C
CC
I
CC
CC
+1.0V
IH
IL
V
HYS
OL
LI
LO
, C
IN
OUT
CC
.7 V
— .3 Vcc V
.05
V
CC
— .40 V I
-10 10
-10 10
—10pFV
Write — 3 mA V
Read — 0.5 mA V
CCS
— 1 5 µ A SCL = SDA = V
Name Function
A0..A2 User Configurable Chip Selects
V
SS
Ground
SDA Serial Address/Data I/O
SCL Serial Clock
WP Write Protect Input
V
CC
+4.5V to 5.5V Power Supply
—V
— V (Note)
OL
= 3.0 mA
IN
AV
AV
= .1V to V
OUT
CC
Tamb = 25˚C, F
CC
CC
= .1V to V
= 5.0V (Note)
= 5.5V, SCL = 400 kHz
= 5.5V, SCL = 400 kHz
CC
CC
= 1 MHz
c
CC
= 5.5V
FIGURE 1-1: BUS TIMING START/STOP
SCL
SU:STA
T
SDA
DS21163B-page 2
START STOP
THD:STA
VHYS
Preliminary
TSU:STO
1996 Microchip Technology Inc.
TABLE 1-3: AC CHARACTERISTICS
≤
24C32A
Parameter Symbol
Units Remarks
Min Max
Vcc = 4.5-5.5
Clock frequency F
Clock high time T
Clock low time T
SDA and SCL rise time T
SDA and SCL fall time T
START condition hold time T
HD
CLK
HIGH
LOW
R
F
STA
:
— 100 kHz
4000 — ns
4700 — ns
— 1000 ns (Note 1)
— 300 ns (Note 1)
4000 — ns After this period the first clock
pulse is generated
SU
START condition setup time T
STA
:
4700 — ns Only relevant for repeated
START condition
Data input hold time T
Data input setup time T
STOP condition setup time T
HD
SU
SU
Output valid from clock T
Bus free time T
:
DAT
DAT
:
:
STO
AA
BUF
0—ns
250 — ns
4000 — ns
— 3500 ns (Note 2)
4700 — ns Time the bus must be free before
a new transmission can start
min to
Output fall time from V
V
IL
max
IH
Input filter spike suppression
OF
T
T
SP
— 250 ns (Note 1), C
— 50 ns (Note 3)
B
100 pF
(SDA and SCL pins)
Write cycle time T
WR
—5ms
Endurance — 1M — cycles 25 ° C, Vcc = 5.0V, Block Mode
(Note 4)
B
Note 1: Not 100% tested. C
= Total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined T
and V
SP
specifications are due to Schmitt trigger inputs which provide improved noise
HYS
and spike suppression. This eliminates the need for a Ti specification for standard operation.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our BBS or website.
FIGURE 1-2: BUS TIMING DATA
TF
TLOW
SCL
TSU:STA
T
SDA
IN
SDA
OUT
1996 Microchip Technology Inc.
TSP
TAA
HD:STA
THD:STA
THIGH
Preliminary
TR
TSU:STOTSU:DATTHD:DAT
TBUFTAA
DS21163B-page 3
24C32A
2.0 FUNCTIONAL DESCRIPTION
The 24C32A supports a Bi-directional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus must be controlled
by a master device which generates the Serial Clock
(SCL), controls the bus access, and generates the
STAR T and ST OP conditions, while the 24C32A works
as slave. Both master and slave can operate as transmitter or receiver but the master device determines
which mode is activated.
3.0 BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus is
not busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.1 Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2 Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a STAR T condition. All
commands must be preceded by a START condition.
3.3 Stop Data Transfer (C)
3.4 Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device.
3.5 Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge signal after the reception of
each byte. The master device must generate an extra
clock pulse which is associated with this acknowledge
bit.
Note: The 24C32A does not generate any
acknowledge bits if an internal programming cycle is in progress.
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable LOW during the HIGH period
of the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account. During reads, a master must signal an end of data to the
slave by NOT generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this case,
the slave (24C32A) will leave the data line HIGH to
enable the master to generate the STOP condition.
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A) (B) (D) (D) (C) (A)
SCL
SDA
START
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
DS21163B-page 4
Preliminary
1996 Microchip Technology Inc.
Loading...