Microchip Technology Inc 24C32AT-E-SM, 24C32AT-E-P, 24C32AT-SN, 24C32AT-SM, 24C32AT-P Datasheet



C 

24C32A

2

32K 5.0V I



C

Serial EEPROM

FEATURES

• Voltage operating range: 4.5V to 5.5V

- Maximum write current 3 mA at 5.5V

- Standby current 1 µ A typical at 5.0V

• 2-wire serial interface bus, I

• 100 kHz and 400 kHz compatibility

• Self-timed ERASE and WRITE cycles

• Power on/off data protection circuitry

• Hardware write protect

• 1,000,000 Erase/Write cycles guaranteed

• 32-byte page or byte write modes available

• Schmitt trigger filtered inputs for noise suppres­sion

• Output slope control to eliminate ground bounce

• 2 ms typical write cycle time, byte or page

• Up to eight devices may be connected to the
same bus for up to 256K bits total memory

• Electrostatic discharge protection > 4000V

• Data retention > 200 years

• 8-pin PDIP and SOIC packages

• Temperature ranges

- Commercial (C): 0˚C to 70˚C

- Industrial (I): -40˚C to +85˚C

- Automotive (E): -40˚C to +125˚C

2

compatible

DESCRIPTION

P ACKA GE TYPES

PDIP

1

A0

2

A1

3

A2

Vss

SOIC

A0
A1

A2

Vss

4

1
2

3

4

24C32A

24C32A

8

Vcc

7

WP

6

SCL

5

SDA

8
7

6

5

Vcc
WP

SCL

SDA

The Microchip T echnology Inc. 24C32A is a 4K x 8 (32K
bit) Serial Electrically Erasable PROM. It has been
developed for advanced, low power applications such
as personal communications or data acquisition. The
24C32A also has a page-write capability of up to 32
bytes of data. The 24C32A is capable of both random
and sequential reads up to the 32K boundary. Func­tional address lines allow up to eight 24C32A devices
on the same bus, for up to 256K bits address space.
Advanced CMOS technology and broad voltage range
make this device ideal for low-power/low-voltage, non­volatile code and data applications. The 24C32A is
available in the standard 8-pin plastic DIP and both 150
mil and 200 mil SOIC packaging.

2

I

C is a trademark of Philips Corporation.

BLOCK DIAGRAM

WP

MEMORY

CONTROL

LOGIC

WP

CONTROL

LOGIC

I/O

SDA

VCC

VSS

A0..A2

I/O

SCL

XDEC

HV GENERATOR

EEPROM

ARRAY

PAGE LATCHES

YDEC

SENSE AMP

R/W CONTROL

1996 Microchip Technology Inc.

Preliminary

DS21163B-page 1



24C32A

µ

µ

1.0 ELECTRICAL

TABLE 1-1: PIN FUNCTION TABLE

CHARACTERISTICS

1.1 Maxim

CC

V

...................................................................................7.0V

All inputs and outputs w.r.t. V

Storage temperature.....................................-65˚C to +150˚C

Ambient temp. with power applied................-65˚C to +125˚C

Soldering temperature of leads (10 seconds).............+300˚C

ESD protection on all pins ..................................................≥ 4 kV

*Notice: Stresses above those listed under “Maximum Ratings”

may cause permanent damage to the device. This is a stress rat­ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.

TABLE 1-2: DC CHARACTERISTICS

Vcc = +4.5V to 5.5V
Commercial (C): Tamb = 0 ° C to +70 ° C
Industrial (I): Tamb = -40 ° C to +85 ° C
Automotive(E): Tamb = -40 ° C to +125 ° C

A0, A1, A2, SCL , SDA and WP
pins:

High level input voltage V
Low level input voltage V
Hysteresis of Schmitt Trigger
inputs

Low level output voltage V
Input leakage current I
Output leakage current I
Pin capacitance
(all inputs/outputs)

Operating current I
Standby current I

Note: This parameter is periodically sampled and not 100% tested.

um Ratings*

SS

............... -0.6V to V

Parameter Symbol Min Typ Max Units Conditions

C

CC

I

CC

CC

+1.0V

IH
IL

V

HYS

OL
LI

LO

, C

IN

OUT

CC

.7 V

— .3 Vcc V

.05

V

CC

— .40 V I

-10 10

-10 10
—10pFV

Write — 3 mA V
Read — 0.5 mA V

CCS

— 1 5 µ A SCL = SDA = V

Name Function

A0..A2 User Configurable Chip Selects

V

SS

Ground
SDA Serial Address/Data I/O
SCL Serial Clock

WP Write Protect Input

V

CC

+4.5V to 5.5V Power Supply

—V
— V (Note)

OL

= 3.0 mA

IN

AV
AV

= .1V to V

OUT
CC

Tamb = 25˚C, F

CC
CC

= .1V to V

= 5.0V (Note)

= 5.5V, SCL = 400 kHz
= 5.5V, SCL = 400 kHz

CC

CC

= 1 MHz

c

CC

= 5.5V

FIGURE 1-1: BUS TIMING START/STOP

SCL

SU:STA

T

SDA

DS21163B-page 2

START STOP

THD:STA

VHYS

Preliminary

TSU:STO

1996 Microchip Technology Inc.

TABLE 1-3: AC CHARACTERISTICS



≤

24C32A

Parameter Symbol

Units Remarks

Min Max

Vcc = 4.5-5.5

Clock frequency F
Clock high time T
Clock low time T
SDA and SCL rise time T
SDA and SCL fall time T
START condition hold time T

HD

CLK
HIGH
LOW

R
F

STA

:

— 100 kHz
4000 — ns
4700 — ns

— 1000 ns (Note 1)

— 300 ns (Note 1)
4000 — ns After this period the first clock

pulse is generated

SU

START condition setup time T

STA

:

4700 — ns Only relevant for repeated

START condition
Data input hold time T
Data input setup time T
STOP condition setup time T

HD
SU
SU

Output valid from clock T
Bus free time T

:

DAT
DAT

:
:

STO

AA

BUF

0—ns

250 — ns

4000 — ns

— 3500 ns (Note 2)

4700 — ns Time the bus must be free before

a new transmission can start

min to

Output fall time from V
V

IL

max

IH

Input filter spike suppression

OF

T

T

SP

— 250 ns (Note 1), C

— 50 ns (Note 3)

B

100 pF

(SDA and SCL pins)
Write cycle time T

WR

—5ms

Endurance — 1M — cycles 25 ° C, Vcc = 5.0V, Block Mode

(Note 4)

B

Note 1: Not 100% tested. C

= Total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

3: The combined T

and V

SP

specifications are due to Schmitt trigger inputs which provide improved noise

HYS

and spike suppression. This eliminates the need for a Ti specification for standard operation.

4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-

cation, please consult the Total Endurance Model which can be obtained on our BBS or website.

FIGURE 1-2: BUS TIMING DATA

TF

TLOW

SCL

TSU:STA

T
SDA
IN

SDA
OUT

1996 Microchip Technology Inc.

TSP

TAA

HD:STA

THD:STA

THIGH

Preliminary

TR

TSU:STOTSU:DATTHD:DAT

TBUFTAA

DS21163B-page 3

24C32A



2.0 FUNCTIONAL DESCRIPTION

The 24C32A supports a Bi-directional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus must be controlled
by a master device which generates the Serial Clock
(SCL), controls the bus access, and generates the
STAR T and ST OP conditions, while the 24C32A works
as slave. Both master and slave can operate as trans­mitter or receiver but the master device determines
which mode is activated.

3.0 BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus is
not busy.

• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been
defined (Figure 3-1).

3.1 Bus not Busy (A)

Both data and clock lines remain HIGH.

3.2 Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a STAR T condition. All
commands must be preceded by a START condition.

3.3 Stop Data Transfer (C)

3.4 Data Valid (D)

The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.

Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device.

3.5 Acknowledge

Each receiving device, when addressed, is obliged to
generate an acknowledge signal after the reception of
each byte. The master device must generate an extra
clock pulse which is associated with this acknowledge
bit.

Note: The 24C32A does not generate any

acknowledge bits if an internal program­ming cycle is in progress.

A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable LOW during the HIGH period
of the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account. Dur­ing reads, a master must signal an end of data to the
slave by NOT generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this case,
the slave (24C32A) will leave the data line HIGH to
enable the master to generate the STOP condition.

A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.

FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A) (B) (D) (D) (C) (A)

SCL

SDA

START

CONDITION

ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

DS21163B-page 4

Preliminary

1996 Microchip Technology Inc.

24C32A

3.6 Device Addressing

A control byte is the first byte received following the
start condition from the master device. The control byte
consists of a 4-bit control code; for the 24C32A this is
set as 1010 binary for read and write (R/W

) operations.
The next three bits of the control byte are the device
select bits (A2, A1, A0). They are used by the master
device to select which of the eight devices are to be
accessed. These bits are in effect the three most signif­icant bits of the word address. The last bit of the control
byte defines the operation to be performed. When set
to a one a read operation is selected, and when set to
a zero a write operation is selected. The next two bytes
received define the address of the first data byte
(Figure 3-3). Because only A11...A0 are used, the
upper four address bits must be zeros. The most signif­icant bit of the most significant byte of the address is
transferred first.

FIGURE 3-2: CONTROL BYTE

ALLOCATION

START

SLAVE ADDRESS

READ/WRITE

R/W A

Following the start condition, the 24C32A monitors the
SDA bus checking the device type identifier being
transmitted. Upon receiving a 1010 code and appropri­ate device select bits, the slave device outputs an
acknowledge signal on the SDA line. Depending on the
state of the R/W

bit, the 24C32A will select a read or

write operation.

Operation

Control

Code

Device Select R/W

Read 1010 Device Address 1
Write 1010 Device Address 0

1 010A2A1A0

FIGURE 3-3: ADDRESS SEQUENCE BIT ASSIGNMENTS

CONTROL BYTE

1010

SLAVE

ADDRESS

A2A1A

0

DEVICE
SELECT

BUS

R/W

ADDRESS BYTE 1

0000

A11A10A

ADDRESS BYTE 0

A

9

8

A

•• ••••

7

A
0

 1996 Microchip Technology Inc. Preliminary DS21163B-page 5

24C32A

4.0 WRITE OPERATION

4.1 Byte Write

Following the start condition from the master, the con­trol code (four bits), the device select (three bits), and
the R/W
by the master transmitter. This indicates to the
addressed slave receiver that a byte with a word
address will follow after it has generated an acknowl­edge bit during the ninth clock cycle. Therefore, the next
byte transmitted by the master is the high-order byte of
the word address and will be written into the address
pointer of the 24C32A. The next byte is the least signif­icant address byte. After receiving another acknowl­edge signal from the 24C32A the master device will
transmit the data word to be written into the addressed
memory location.

The 24C32A acknowledges again and the master gen­erates a stop condition. This initiates the internal write
cycle, and during this time the 24C32A will not generate
acknowledge signals (Figure 4-1).

bit which is a logic low are clocked onto the bus

4.2 Page Write

The write control byte, word address and the first data
byte are transmitted to the 24C32A in the same way as
in a byte write. But instead of generating a stop condi­tion, the master transmits up to 32 bytes which are tem­porarily stored in the on-chip page buffer and will be
written into memory after the master has transmitted a
stop condition. After receipt of each word, the five lower
address pointer bits are internally incremented by one.
If the master should transmit more than 32 bytes prior
to generating the stop condition, the address counter
will roll over and the previously received data will be
overwritten. As with the byte write operation, once the
stop condition is received, an internal write cycle will
begin. (Figure 4-2).

FIGURE 4-1: BYTE WRITE

S

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

T
A
R
T

FIGURE 4-2: PAGE WRITE

S

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

T
A

CONTROL

R
T

BYTE

CONTROL

BYTE

ADDRESS

HIGH BYTE

0000

A
C
K

ADDRESS

HIGH BYTE

0000

A
C
K

A
C
K

A
C
K

ADDRESS

LOW BYTE

ADDRESS

LOW BYTE

DATA BYTE 0

A
C
K

S

DATA

A
C
K

DATA BYTE 31

T
O
P

A
C
K

S
T
O
P

A
C
K

DS21163B-page 6 Preliminary  1996 Microchip Technology Inc.

24C32A

5.0 ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com­mand has been issued from the master, the device ini­tiates the internally timed write cycle. Acknowledge
Polling (ACK) can be initiated immediately. This
involves the master sending a start condition followed
by the control byte for a write command (R/W
device is still busy with the write cycle, then NO ACK
will be returned. If the cycle is complete, then the device
will return the ACK and the master can then proceed
with the next read or write command. See Figure 5-1 for
flow diagram.

FIGURE 5-1: ACKNOWLEDGE POLLING

FLOW

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

YES

= 0). If the

NO

6.0 READ OPERATION

Read operations are initiated in the same way as write
operations with the exception that the R/W
slave address is set to one. There are three basic types
of read operations: current address read, random read,
and sequential read.

6.1 Current Address Read

The 24C32A contains an address counter that main­tains the address of the last word accessed, internally
incremented by one. Therefore, if the previous access
(either a read or write operation) was to address n (n is
any legal address), the next current address read oper­ation would access data from address n + 1. Upon
receipt of the slave address with R/W
24C32A issues an acknowledge and transmits the eight
bit data word. The master will not acknowledge the
transfer but does generate a stop condition and the
24C32A discontinues transmission (Figure 6-1).

6.2 Random Read

Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24C32A as part of a write operation (R/W
zero). After the word address is sent, the master gener­ates a start condition following the acknowledge. This
terminates the write operation, but not before the inter­nal address pointer is set. Then the master issues the
control byte again but with the R/W
24C32A will then issue an acknowledge and transmit
the 8-bit data word. The master will not acknowledge
the transfer but does generate a stop condition which
causes the 24C32A to discontinue transmission
(Figure 6-2).

bit set to a one. The

bit of the

bit set to one, the

bit set to

Next

Operation

FIGURE 6-1: CURRENT ADDRESS READ

S

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

 1996 Microchip Technology Inc. Preliminary DS21163B-page 7

T
A

CONTROL BYTE DATA BYTE

R
T

SP

A
C
K

S
T
O
P

N

O

A
C
K

24C32A

6.3 Contiguous Addressing Across Multiple Devices

The device select bits A2, A1, A0 can be used to
expand the contiguous address space for up to 256K
bits by adding up to eight 24C32A's on the same bus.
In this case, software can use A0 of the control byte
address bit A12, A1 as address bit A13, and A2 as
address bit A14.

as

6.4 Sequential Read

Sequential reads are initiated in the same way as a ran­dom read except that after the 24C32A transmits the
first data byte, the master issues an acknowledge as
opposed to the stop condition used in a random read.
This acknowledge directs the 24C32A to transmit the
next sequentially addressed 8-bit word (Figure 6-3).
Following the final byte transmitted to the master, the
master will NOT generate an acknowledge but will gen­erate a stop condition.

To provide sequential reads the 24C32A contains an
internal address pointer which is incremented by one at
the completion of each operation. This address pointer
allows the entire memory contents to be serially read
during one operation. The internal address pointer will
automatically roll over from address 0FFF to address
000 if the master acknowledges the byte received from
the array address 0FFF.

FIGURE 6-2: RANDOM READ

S

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

T
A

CONTROL

R
T

BYTE

0000

A
C
K

FIGURE 6-3: SEQUENTIAL READ

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE

DATA n DATA n + 1 DATA n + 2 DATA n + x

A
C
K

ADDRESS

HIGH BYTE

A
C
K

ADDRESS

LOW BYTE

A
C
K

S
T
A

CONTROL

R
T

A
C
K

A
C
K

BYTE

A
C
K

DATA
BYTE

A
C
K

S
T
O
P

N

O

A
C
K

S
T
O
P

N
O

A
C
K

DS21163B-page 8 Preliminary  1996 Microchip Technology Inc.

24C32A

7.0 PIN DESCRIPTIONS

7.1 A0, A1, A2 Chip Address Inputs

The A0..A2 inputs are used by the 24C32A for multiple
device operation and conform to the 2-wire bus stan­dard. The levels applied to these pins define the
address block occupied by the device in the address
map. A particular device is selected by transmitting the
corresponding bits (A2, A1, A0) in the control byte
(Figure 3-3).

7.2 SDA Serial Address/Data Input/Output

This is a Bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pullup
resistor to V
kHz)

For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL HIGH are
reserved for indicating the START and STOP condi­tions.

7.3 SCL Serial Clock

This input is used to synchronize the data transfer from
and to the device.

CC (typical 10KΩ for 100 kHz, 1KΩ for 400

8.0 NOISE PROTECTION

The SCL and SDA inputs have filter circuits which sup­press noise spikes to ensure proper device operation
even on a noisy bus. All I/O lines incorporate Schmitt
triggers for 400 kHz (Fast Mode) compatibility.

9.0 POWER MANAGEMENT

This design incorporates a power standby mode when
the device is not in use and automatically powers off
after the normal termination of any operation when a
stop bit is received and all internal functions are com­plete. This includes any error conditions, i.e., not receiv­ing an acknowledge or stop condition per the two-wire
bus specification. The device also incorporates V
monitor circuitry to prevent inadvertent writes (data cor­ruption) during low-voltage conditions. The V
circuitry is powered off when the device is in standby
mode in order to further reduce power consumption.

DD monitor

DD

7.4 WP

This pin must be connected to either VSS or VCC.
If tied to V

(read/write the entire memory 000-FFF).
If tied to V

entire memory will be write-protected. Read operations
are not affected.

SS, normal memory operation is enabled

CC, WRITE operations are inhibited. The

 1996 Microchip Technology Inc. Preliminary DS21163B-page 9

24C32A

NOTES:

DS21163B-page 10 Preliminary  1996 Microchip Technology Inc.

24C32A

24C32A Product Identification System

To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales offices.

24C32A - /P

Package: P = Plastic DIP (300 mil Body), 8-lead

SN = Plastic SOIC (150 mil Body, EIAJ standard)

SM = Plastic SOIC (207 mil Body, EIAJ standard)

Temperature Blank = 0°C to +70°C
Range: I = -40°C to +85°C

E = -40°C to +125°C

2

Device: 24C32A 32K I

24C32AT 32K I

C Serial EEPROM (100 kHz, 400 kHz)

2

C Serial EEPROM (Tape and Reel)

 1996 Microchip Technology Inc. Preliminary DS21163B-page 11

WORLDWIDE SALES & SERVICE

AMERICAS

Corporate Office

Microchip Technology Inc.
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: [phone] Fax: [phone]

Technical Support:
Web:

http://www.microchip.com

Atlanta

Microchip Technology Inc.
500 Sugar Mill Road, Suite 200B
Atlanta, GA 30350
Tel: [phone] Fax: [phone]

Boston

Microchip Technology Inc.
5 Mount Royal Avenue
Marlborough, MA 01752
Tel: [phone] Fax: [phone]

Chicago

Microchip Technology Inc.
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: [phone] Fax: [phone]

Dallas

Microchip Technology Inc.
14651 Dallas Parkway, Suite 816
Dallas, TX 75240-8809
Tel: [phone] Fax: [phone]

Dayton

Microchip Technology Inc.
Suite 150
Two Prestige Place
Miamisburg, OH 45342
Tel: [phone] Fax: [phone]

Los Angeles

Microchip Technology Inc.
18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: [phone] Fax: [phone]

New Y ork

Microchip Technmgy Inc.
150 Motor Parkway, Suite 416
Hauppauge, NY 11788
Tel: [phone] Fax: [phone]

San Jose

Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: [phone] Fax: [phone]

Toronto

Microchip Technology Inc.
5925 Airport Road, Suite 200
Mississauga, Ontario L4V 1W1, Canada
Tel: [phone] Fax: [phone]

602 786-7627

ASIA/PACIFIC

China

Microchip Technology
Unit 406 of Shanghai Golden Bridge Bldg.
2077 Yan’an Road West, Hongiao District
Shanghai, Peoples Republic of China
Tel: [phone]
Fax: [phone]

Hong Kong

Microchip Technology
RM 3801B, Tower Two
Metroplaza
223 Hing Fong Road
Kwai Fong, N.T. Hong Kong
Tel: [phone] Fax: [phone]

India

Microchip Technology
No. 6, Legacy, Convent Road
Bangalore 560 025 India
Tel: [phone] Fax: [phone]

Korea

Microchip Technology
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku,
Seoul, Korea
Tel: [phone] Fax: [phone]

Singapore

Microchip Technology
200 Middle Road
#10-03 Prime Centre
Singapore 188980
Tel: [phone] Fax: [phone]

Taiwan, R.O.C

Microchip Technology
10F-1C 207
Tung Hua North Road
Taipei, Taiwan, ROC
Tel: [phone] Fax: [phone]

EUROPE

United Kingdom

Arizona Microchip Technology Ltd.
Unit 6, The Courtyard
Meadow Bank, Furlong Road
Bourne End, Buckinghamshire SL8 5AJ
Tel: [phone] Fax: [phone]

France

Arizona Microchip Technology SARL
Zone Industrielle de la Bonde
2 Rue du Buisson aux Fraises
91300 Massy - France
Tel: [phone] Fax: [phone]

Germany

Arizona Microchip Technology GmbH
Gustav-Heinemann-Ring 125
D-81739 Muenchen, Germany
Tel: [phone] Fax: [phone]

Italy

Arizona Microchip Technology SRL
Centro Direzionale Colleone Pas Taurus 1
Viale Colleoni 1
20041 Agrate Brianza
Milan Italy
Tel: [phone] Fax: [phone]

JAPAN

Microchip Technology Intl. Inc.
Benex S-1 6F
3-18-20, Shin Yokohama
Kohoku-Ku, Y okohama
Kanagawa 222 Japan
Tel: [phone] Fax: [phone]

9/3/96

All rights reserved.  1996, Microchip Technology Incorporated, USA. 9/96

Printed on recycled paper.

Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No repre­sentation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement
of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not autho­rized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and
name are registered trademarks of Microchip Technology Inc. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.

DS21163B-page 12 Preliminary  1996 Microchip Technology Inc.