Microchip Technology Inc 24C04AT-I-SN, 24C04AT-I-SM, 24C04AT-SL, 24C04AT-P, 24C04A-I-SN Datasheet



1996 Microchip Technology Inc. DS11183D-page 1

24C01A/02A/04A

FEATURES

• Low power CMOS technology

• Hardware write protect

• Two wire serial interface bus, I

2

C 

compatible

• 5.0V only operation

• Self-timed write cycle (including auto-erase)

• Page-write buffer

• 1ms write cycle time for single byte

• 1,000,000 Erase/Write cycles guaranteed

• Data retention >200 years

• 8-pin DIP/SOIC packages

• Available for extended temperature ranges

DESCRIPTION

The Microchip Technology Inc. 24C01A/02A/04A is a
1K/2K/4K bit Electrically Erasable PROM. The device
is organized as shown, with a standard two wire serial
interface. Advanced CMOS technology allows a signif­icant reduction in power over NMOS serial devices. A
special feature in the 24C02A and 24C04A provides
hardware write protection for the upper half of the block.
The 24C01A and 24C02A have a page write capability
of two bytes and the 24C04A has a page length of eight
bytes. Up to eight 24C01A or 24C02A devices and up
to four 24C04A devices may be connected to the same
two wire bus.

This device offers fast (1ms) byte write and
extended (-40 ° C to 125 ° C) temperature operation. It
is recommended that all other applications use
Microchip’s 24LCXXB.

- Commercial (C): 0˚C to +70˚C

- Industrial (I): -40˚C to +85˚C

- Automotive (E): -40˚C to +125˚C

24C01A 24C02A 24C04A

Organization 128 x 8 258 x 8 2 x 256 x 8
Write Protect None 080-0FF 100-1FF
Page Write

Buffer

2 Bytes 2 Bytes 8 Bytes

PACKA GE TYPES

BLOCK DIAGRAM

NC

SS

CC

A0
A1

NC

A2

NC

V

1
2
3
4

5

6

7

14
13

12

NC
SCL

SDA
NC

9
8

11

10

WP

V

NC

* “TEST” pin in 24C01A

24C01A

24C02A

24C04A

24C01A

24C02A

24C04A

24C01A

24C02A

24C04A

A0
A1

A2

V

SS

1
2

3

4

8
7

6

5

V

CC

WP*

SCL

SDA

A0
A1

A2

V

SS

1
2

3

4

8
7

6

5

V

CC

WP*

SCL

SDA

DIP

8-lead
SOIC

14-lead
SOIC

Vcc
Vss

SDA

SCL

Data
Buffer
(FIFO)

Data Reg.

Vpp R/W

Amp

Memory

Array

A
d
d

r
e
s
s

P

o

i

n

t

e

r

A0 to
A7

Increment

A8

Slave Addr.

Control

Logic

A0 A1 A2 WP

1K/2K/4K 5.0V I

2

C



Serial EEPROMs

I

2

C is a trademark of Philips Corporation.

24C01A/02A/04A

DS11183D-page 2



1996 Microchip Technology Inc.

1.0 ELECTRICAL CHARA CTERISTICS

1.1 Maxim

um Ratings*

V

CC

...................................................................................7.0V

All inputs and outputs w.r.t. V

SS

............... -0.6V to V

CC

+1.0V

Storage temperature.....................................-65˚C to +150˚C

Ambient temp. with power applied................-65˚C to +125˚C

Soldering temperature of leads (10 seconds).............+300˚C

ESD protection on all pins................................................4 kV

*Notice: Stresses above those listed under “Maximum ratings”

may cause permanent damage to the device. This is a stress rat­ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.

TABLE 1-1: PIN FUNCTION TABLE

Name Function

A0 No Function for 24C04A only, Must

be connected to V

CC

or V

SS

A0, A1, A2 Chip Address Inputs

V

SS

Ground

SDA Serial Address/Data I/O

SCL Serial Clock

TEST (24C01A only) V

CC

or V

SS

WP Write Protect Input

V

CC

+5V Power Supply

TABLE 1-2: DC CHARACTERISTICS

FIGURE 1-1: BUS TIMING START/STOP

V

CC

= +5V ( ± 10%) Commercial (C): Tamb = 0 ° C to +70 ° C

Industrial (I): Tamb = -40 ° C to +85 ° C
Automotive (E): Tamb = -40 ° C to +125 ° C

Parameter Symbol Min. Max. Units Conditions

V

CC

detector threshold V

TH

2.8 4.5 V

SCL and SDA pins:

High level input voltage
Low level input voltage
Low level output voltage

V

IH

V

IL

V

OL

V

CC

x 0.7

-0.3

V

CC

+ 1

V

CC

x 0.3

0.4

V
V
VI

OL

= 3.2 mA (SDA only)

A1 & A2 pins:

High level input voltage
Low level input voltage

V

IH

V

IL

V

CC

- 0.5

-0.3

V

CC

+ 0.5

0.5

V
V

Input leakage current I

LI

—10

µ

AV

IN

= 0V to V

CC

Output leakage current I

LO

—10

µ

AV

OUT

= 0V to V

CC

Pin capacitance
(all inputs/outputs)

C

IN

,

C

OUT

— 7.0 pF V

IN

/V

OUT

= 0V (Note)

Tamb = +25˚C, f = 1 MHz

Operating current I

CC

Write — 3.5 mA F

CLK

= 100 kHz, program cycle time = 1 ms,

Vcc = 5V, Tamb = 0˚C to +70˚C

I

CC

Write — 4.25 mA F

CLK

= 100 kHz, program cycle time = 1 ms,

Vcc = 5V, Tamb = (I) and (E)

I

CC

Read

— 750

µ

AV

CC

= 5V, Tamb= (C), (I) and (E)

Standby current I

CCS

— 100

µ

A SDA=SCL=V

CC

=5V (no PROGRAM active)

Note: This parameter is periodically sampled and not 100% tested

TSU:STA

THD:STA

VHYS

TSU:STO

START STOP

SCL

SDA



1996 Microchip Technology Inc. DS11183D-page 3

24C01A/02A/04A

TABLE 1-3: AC CHARACTERISTICS

FIGURE 1-2: BUS TIMING DATA

Parameter Symbol Min. Typ Max. Units Remarks

Clock frequency F

CLK

— — 100 kHz

Clock high time T

HIGH

4000 — — ns

Clock low time T

LOW

4700 — — ns

SDA and SCL rise time T

R

— — 1000 ns

SDA and SCL fall time T

F

— — 300 ns

START condition hold time T

HD

:S

TA

4000 — — ns After this period the first

clock pulse is generated

START condition setup time T

SU

:S

TA

4700 — — ns Only relevant for repeated

START condition

Data input hold time T

HD

:D

AT

0—— ns

Data input setup time T

SU

:D

AT

250 — — ns

Data output delay time T

AA

300 — 3500

(Note 1)

STOP condition setup time T

SU

:S

TO

4700 — — ns

Bus free time T

BUF

4700 — — ns Time the bus must be free

before a new transmission
can start

Input filter time constant
(SDA and SCL pins)

T

I

— — 100 ns

Program cycle time T

WC

— .4 1 ms Byte mode

.4N N ms Page mode, N=# of bytes

Endurance — 1M — — cycles 25 ° C, Vcc = 5.0V, Block

Mode (Note 2)

Note 1: As transmitter the device must provide this internal minimum delay time to bridge the undefined region (min-

imum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

2: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-

cation, please consult the Total Endurance Model which can be obtained on our BBS or website.

TSU:STA

TF

TLOW

THIGH

TR

THD:DAT TSU:DAT

TSU:STO

THD:STA

TBUF

TAA

TAA

TSP

THD:STA

SCL

SDA

IN

SDA
OUT

24C01A/02A/04A

DS11183D-page 4  1996 Microchip Technology Inc.

2.0 FUNCTIONAL DESCRIPTION

The 24C01A/02A/04A supports a bidirectional two wire
bus and data transmission protocol. A device that
sends data onto the bus is defined as transmitter, and
a device receiving data as receiver. The bus has to be
controlled by a master device which generates the
serial clock (SCL), controls the bus access, and gener­ates the START and STOP conditions, while the
24C01A/02A/04A works as slave. Both master and
slave can operate as transmitter or receiver but the
master device determines which mode is activated.

Up to eight 24C01/24c02s can be connected to the bus,
selected by the A0, A1 and A2 chip address inputs. Up
to four 24C04As can be connected to the bus, selected
by A1 and A2 chip address inputs. A0 must be tied to
V

CC or VSS for the 24C04A. Other devices can be con-

nected to the bus but require different device codes
than the 24C01A/02A/04A (refer to section Slave
Address).

3.0 BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus is

not busy.

• During data transfer, the data line must remain

stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been
defined (Figure 3-1).

3.1 Bus not Busy (A)

Both data and clock lines remain HIGH.

3.2 Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a STAR T condition. All
commands must be preceded by a START condition.

3.3 Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.

3.4 Data Valid (D)

The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.

Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited.

3.5 Acknowledge

Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.

The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must leave the data line HIGH to enable
the master to generate the STOP condition.

Note: The 24C01A/02A/04A does not generate

any acknowledge bits if an internal pro­gramming cycle is in progress.

FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A) (B) (D) (D) (A)(C)

START

CONDITION

ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

SCL

SDA