Note: Chip Enable active low input activates the chip's control logic, Address buffer and Page buffer.
Output
Buffer
D0
D15/(D7)
P/N:PM0241
REV. 2.1, JUL. 18, 2001
2
MX23C1611
ABSOLUTE MAXIMUM RATINGS
ItemSymbolRatings
V oltage on any Pin Relativ e to VSSVIN-1.3V to VCC+2.0V (Note)
Ambient Operating TemperatureT opr-40°C to 85°C
Storage T emperatureTstg-65°C to 125°C
Note: Minimum DC v oltage on input or I/O pins is -0.5V.
During voltage transitions, inputs may undershoot VSS
to -1.3V for periods of up to 20ns. Maximum DC voltage
on input or I/O pins is VCC+0.5V. During voltage transitions, input may overshoot VCC to VCC+2.0V for periods of up to 20ns.
DC CHARACTERISTICS (Ta = 0°C ~ 70°C, VCC = 5V±10%)
ItemSymbolMIN.MAX.Conditions
Output High VoltageV OH2.4V-IOH = -1.0mA
Output Low VoltageVOL-0.4VIOL = 2.1mA
Input High VoltageVIH2.2VVCC+0.3V
Input Low VoltageVIL-0.3V0.2 x VCC
Input Leakage CurrentILI-5uA0V, VCC
Output Leakage CurrentILO-5uA0V , VCC
Operating CurrentICC1-60mAtRC = 100ns, all output open
Standby Current (TTL)ISTB1-1mACE = VIH
Standby Current (cmos)ISTB2-100uACE>VCC-0.2V
Input CapacitanceCIN-10pFTa = 25°C, f = 1MHZ
Output CapacitanceCOUT-10pFTa = 25°C, f = 1MHZ
AC CHARACTERISTICS (Ta = 0°C ~ 70°C, VCC = 5V±10%)
ItemSymbol 23C1611-10 23C1611-12
MIN.MAX.MIN.MAX.
Read Cycle TimetR C100ns-120nsAddress Access TimetAA-100ns-120ns
Chip Enable Access TimetACE-100ns-120ns
Page Mode Access TimetP A-50ns-60ns
Output Enable TimetOE-50ns-60ns
Output Hold After AddresstOH10ns-10nsOutput High Z DelaytHZ-20ns-20ns
Note:Output high-impedance delay (tHZ) is measured
from OE or CE going high, and this parameter guaranteed by design over the full voltage and temperature operating range - not tested.
P/N:PM0241
3
REV. 2.1, JUL. 18, 2001
AC T est Conditions
Input Pulse Levels0.4V~ 2.4V
Input Rise and Fall Times10ns
Input Timing Level1.5V
Output Timing Le v el0.8V and 2.0V
Output LoadSee Figure
TIMING DIAGRAM
RANDOM READ
MX23C1611
IOH (load)=-1mA
DOUT
IOL (load)=2.1mA
Note:
No output loading is present in tester load board.
Active loading is used and under software programming control.
Output loading capacitance includes load board's and all stray capacitance.
C<100pF
DATA
PAGE READ
(A-1),A0,A1,A2
ADD
CE
OE
A3-A19
ADDADDADD
tAA
2'nd ADD
tRC
tOH
VALID ADD
3'rd ADD
tACE
tOE
VALIDVALIDVALID
1'st ADD
tHZ
P/N:PM0241
tAA
DATA
Note: CE, OE are enable.
Page size is 8 words in 16-bit mode, 16 bytes in 8-bit mode.
VALID
tPA
VALID
4
VALID
REV. 2.1, JUL. 18, 2001
PACKAGE INFORMATION
42-PIN PLASTIC DIP(600 mil)
MX23C1611
P/N:PM0241
REV. 2.1, JUL. 18, 2001
5
44-PIN PLASTIC SOP
MX23C1611
P/N:PM0241
REV. 2.1, JUL. 18, 2001
6
48-PIN TSOP
MX23C1611
P/N:PM0241
REV. 2.1, JUL. 18, 2001
7
MX23C1611
Revision History
RevisionDescriptionPageDate
1.8tACE--->1000ns changes to tACE--->100nsP3JUL/20/1998