10. PARTS LOCATION..............................................................................................................45
11. IC DATA............................................................................................................................... 61
12. EXPLODED VIEW AND PARTS LIST................................................................................. 85
13. ELECTRICAL PARTS LIST................................................................................................. 97
SURR DIRECT
DISC 6.1 MTX 6.1
AV Surround Receiver
PS7500 /
PS8500 /
F1N
F1N
AV Surround Amplifi er
VOLUME
SURROUND
PEAK ANALOG
ATT
DIGITAL
DIGITAL
NIGHT
LCR
LFE
AAC
PCM
SL S SR
ENTER
DOWN
UP
PS7500 / PS8500
AUX 1 INPUT
AUDIOS-VIDEODIGITALVIDEO LR
SR7500 / SR8500
Please use this service manual with referring to the user guide ( D.F.U. ) without fail.
SR7500 / SR8500
PS7500 / PS8500
Part no. 90M10BW855012
2nd Issue 2004.11
MJI
Page 2
MARANTZ DESIGN AND SERVICE
Using superior design and selected high grade components,
Only original
MARANTZ
parts can insure that your
MARANTZ
MARANTZ
product will continue to perform to the specifi cations for which
company has created the ultimate in stereo sound.
it is famous.
Parts for your
MARANTZ
ORDERING PARTS :
equipment are generally available to our National Marantz Subsidiary or Agent.
Parts can be ordered either by mail or by Fax.. In both cases, the correct part number has to be specifi ed.
The following information must be supplied to eliminate delays in processing your order :
1. Complete address
2. Complete part numbers and quantities required
3. Description of parts
4. Model number for which part is required
5. Way of shipment
6. Signature : any order form or Fax. must be signed, otherwise such part order will be considered as null and void.
CAUTION : After servicing this appliance and prior to returning to customer, measure the resistance between either primary AC
cord connector pins ( with unit NOT connected to AC mains and its Power switch ON ), and the face or Front Panel of product and
controls and chassis bottom.
Any resistance measurement less than 1 Megohms should cause unit to be repaired or corrected before AC power is applied, and
verifi ed before it is return to the user/customer.
Ref. UL Standard No. 1492.
In case of diffi culties, do not hesitate to contact the Technical
Department at above mentioned address.
041015MJI
Page 3
1. TECHNICAL SPECIFICATIONS
FM TUNER SECTION [SR7500/SR8500]
Frequency Range.............................................87.5 - 108.0 MHz
The relation between the selected surround mode and the input signal
The surround mode is selected with the surround mode buttons on SR7500/SR8500/PS7500/PS8500 or the remote control
unit. However, the sound you hear is subject to the relationship between the selected surround mode and input signal. That
relationship is as follows;
Surround ModeInput SignalDecoding
AUTODolby Surr. EXDolby Digital EX
PURE DIRECTDolby D Surr. EXDolby Digital EX
EX/ESDolby D Surr. EXDolby Digital EX
DOLBYDolby D Surr. EXDolby Digital 5.1
(PLIIx movie)Dolby D (5.1ch)Dolby Digital 5.1
(PLIIx music)Dolby D (2ch)Pro Logic IIx
(PLIIx game)Dolby D (2ch Surr)Pro Logic IIx
DIGITAL , 2 SURROUNDL, R, S
PCML, R
PCM, HDCDL, R
ANALOG-
DIGITAL EXL, C, R, SL, SR, S, LFE
DIGITALL, C, R, SL, SR, LFE
DIGITAL , 2 SURROUNDL, R, S
*
*
: SR8500 only
: PS8500 only
2
Page 5
*
: SR8500 only
Output ChannelFront information display
Surround ModeInput SignalDecoding
L/R C
SL SBL
SubW
Signal format indicatorsChannel status
SR SBR
VirtualDolby Surr. EXVirtual
O
-- - -2 DIGITAL EXL, C, R, SL, SR, S, LFE
Dolby D (5.1ch)Virtual
O
-- - -2 DIGITALL, C, R, SL, SR, LFE
Dolby D (2ch)Virtual
O
-- - -2 DIGITALL, R
Dolby D (2ch Surr)Virtual
O
-- - -2 DIGITAL , 2 SURROUNDL, R, S
DTS-ESVirtual
O
----dts, ESL, C, R, SL, SR, LFE
DTS (5.1ch)Virtual
O
----dtsL, C, R, SL, SR, LFE
PCM (Audio)Virtual
O
----PCML, R
HDCD
*
Virtual
O
----PCM, HDCDL, R
AnalogVirtual
O
----ANALOG-
Multi Ch.Dolby Surr. EXMulti Channel Stereo
OOOOO2 DIGITAL EXL, C, R, SL, SR, S, LFE
StereoDolby D (5.1ch)Multi Channel Stereo
OOO-O2 DIGITALL, C, R, SL, SR, LFE
Dolby D (2ch)Multi Channel Stereo
OOOO-2
DIGITALL, R
Dolby D (2ch Surr)Multi Channel Stereo
OOOO-2
DIGITAL , 2 SURROUNDL, R, S
DTS-ESDTS-ES
OOOOO
dts, ESL, C, R, SL, SR, S, LFE
DTS (5.1ch)DTS 5.1
OOO-O
dtsL, C, R, SL, SR, LFE
PCM (Audio)Multi Channel Stereo
OOOO
-PCML, R
HDCD
*
Multi Channel Stereo
OOOO
-PCM, HDCDL, R
AnalogMulti Channel Stereo
OOOO
-ANALOG-
THXDolby Surr. EXTHX Surround EX + Dolby Digital
OOOOO2 DIGITAL EXL, C, R, SL, SR, S, LFE
Dolby D (5.1ch)THX + Dolby Digital
OOO-O2 DIGITALL, C, R, SL, SR, LFE
Dolby D (2ch)THX + Pro Logic IIx
OOOO-2
DIGITALL, R
Dolby D (2ch Surr)THX + Pro Logic IIx
OOOO-2
DIGITAL , 2 SURROUNDL, R, S
DTS-ESTHX + DTS-ES
OOOOO
dts, ESL, C, R, SL, SR, S, LFE
DTS 96/24THX + DTS
OOO-O
dts 96/24L, C, R, SL, SR, LFE
DTS (5.1ch)THX + DTS
OOO-O
dtsL, C, R, SL, SR, LFE
PCM (Audio)THX + Pro Logic IIx
OOOO
-PCML, R
HDCD
*
THX + Pro Logic IIx
OOOO
-PCM, HDCDL, R
AnalogTHX + Pro Logic
II
x
OOOO
-ANALOG-
: PS8500 only
*
Note:
• Dolby Digital (2 ch: Lt/Rt): signal with Dolby
Surround flag Speakers are full set.
• No sound outputs from the surround speaker,
center speaker and subwoofer if the DVD disc has
no surround data.
Abbreviations
L/R : Front speakers
C : Center speaker
SL/SR : Surround speakers
SBL/SBR : Surround Back speakers
SubW : Sub woofer speaker
DolbyDigital(2chSurr):
ドルビーサラウンド処理されたドルビーデ
ジタル2ch信号
: サブウーファー他のスピーカーのLarge/
*
Smallによってサブウーファー出力は異な
ります。
L/R: フロントスピーカー
C: センタースピーカー
SL/SR: サラウンドスピーカー
SBL/SBR: サラウンドバックスピーカー
SubW: サブウーファースピーカー
3
Page 6
2. TECHNICAL DESCRIPTION
THX® is an exclusive set of standards and
technologies established by the world-renowned
film production company, Lucasfilm Ltd. THX
resulted from George Lucas’ desire to reproduce
the movie soundtrack as faithfully as possible both
in the movie theater and in the home theater.
THX engineers developed patented technologies
to accurately translate the sound from a movie
theater environment into the home, correcting the
tonal and spatial errors that occur.
When the THX mode of the SR7500 is on, three
distinct THX technologies are automatically
added:
Re-Equalization-restores the correct tonal balance
for watching a movie in a home environment.
These sounds are otherwise mixed to be brighter
for a large movie theater. Re-EQ compensates for
this and prevents the soundtracks from being
overly bright and harsh when played in a home
theater.
Timbre Matching-filters the information going to
the surround speakers so they more closely match
the tonal characteristics of the sound coming from
the front speakers.
This ensures seamless panning between the front
and surround speakers.
Adaptive Decorrelation-slightly changes one
surround channel’s time and phase relationship
with respect to the other surround channel.
This expands the listening position and creates
with only two surround speakers the same
spacious surround experience as in a movie
theater with multiple surround speakers.
The Marantz SR7500 was required to pass a
rigorous series of quality and performance tests, in
addition to incorporating the technologies
explained above, in order to be THX certified by
Lucasfilm Ltd.
THX requirements cover every aspect of
performance including pre-amplifier and power
amplifier performance and operation, and
hundreds of other parameters in both the digital
and analog domain.
Movies which have been encoded in Dolby Digital,
DTS, Dolby Pro Logic, stereo and Mono will all
benefit from the THX mode when being viewed.
The THX mode should only be activated when
watching movies which were originally produced
for a movie theater environment.
This is because they were originally mixed for a
small room environment.
THX is a trademark or registered trademark of THX
Ltd. Surround EX is a jointly developed technology
of THX and Dolby Laboratories, Inc. and is a
trademark of Dolby Laboratories, Inc. Used under
authorization. All rights reserved.
THX Surround EX—Dolby DIgital Surround EX is a
joint development of Dolby Laboratories and THX
Ltd.
In a movie theater, film soundtracks that have been
encoded with Dolby Digital Surround EX
technology are able to reproduce an extra channel
which has been added during the mixing of the
program. This channel, called Surround Back,
places sounds behind the listener in addition to the
currently available front left, front center, front
right, surround right, surround left and subwoofer
channels. This additional channel provides the
opportunity for more detailed imaging behind the
listener and brings more depth, spacious
ambience and sound localization than ever before.
Movies that were created using the Dolby Digital
Surround EX technology, when released into the
home consumer market may exhibit wording to that
effect on the packaging. A list of movies created
using this technology can be found on the Dolby
web site at www.dolby.com. A list of available
DVD software titles encoded with this technology
an be found at www.thx.com.
Only receiver and controller products bearing the
THX Surround EX logo, when in the THX Surround
EX mode, faithfully reproduce this new technology
in the home. This product may also engage the
THX Surround EX mode during the playback of 5.1
channel material that is not Dolby Digital Surround
EX eocnded. In such case, the information
delivered to the Surround Back channel will be
program dependent and may or may not be very
pleasing depending on the particular soundtrack
and the tastes of the individual listener.
“SURROUND EX™” is a trademark of Dolby
Laboratories. Used under authorization.
4
Page 7
DTS was introduced in 1994 to provide 5.1
channels of discrete digital audio into home theater
systems.
DTS brings you premium quality discrete
multichannel digital sound to both movies and
music.
DTS is a multichannel sound system designed to
create full range digital sound reproduction.
The no compromise DTS digital process sets the
standard of quality for cinema sound by delivering
an exact copy of the studio master recordings to
neighborhood and home theaters.
Now, every moviegoer can hear the sound exactly
as the moviemaker intended.
DTS can be enjoyed in the home for either movies
or music on of DVD’s, LD’s, and CD’s.
“DTS” and “DTS Digital Surround” are registered
trademarks of Digital Theater Systems, Inc.
the subtlety and integrity of the original stereo
recording.
DTS-ES Extended Surround is a new multichannel
digital signal format developed by Digital Theater
Systems Inc. While offering high compatibility with
the conventional DTS Digital Surround format,
DTS-ES Extended Surround greatly improves the
360-degree surround impression and space
expression thanks to further expanded surround
signals. This format has been used professionally
in movie theaters since 1999.
In addition to the 5.1 surround channels (FL, FR,
C, SL, SR and LFE), DTS-ES Extended Surround
also offers the SB (Surround Back) channel for
surround playback with a total of 6.1 channels.
DTS-ES Extended Surround includes two signal
formats with different surround signal recording
methods, as DTS-ES Discrete 6.1 and DTS-ES
Matrix 6.1.
“DTS”, “DTS-ES and “Neo:6” are trademarks of
Digital Theater Systems, Inc.
The advantages of discrete multichannel systems
over matrix are well known.
But even in homes equipped for discrete
multichannel, there remains a need for high-quality
matrix decoding. This is because of the large
library of matrix surround motion pictures available
on disc and on VHS tape; and analog television
broadcasts.
The typical matrix decoder of today derives a
center channel and a mono surround channel from
two-channel matrix stereo material. It is better than
a simple matrix in that it includes steering logic to
improve separation, but because of its mono,
band-limited surround it can be disappointing to
users accustomed to discrete multichannel.
Neo:6 offers several important improvements as
follow,
• Neo:6 provides up to six full-band channels of
matrix decoding from stereo matrix material.
Users with 6.1 and 5.1 systems will derive six
and five separate channels, respectively,
corresponding to the standard home-theater
speaker layouts.
• Neo:6 technology allows various sound
elements within a channel or channels to be
steered separately, and in a way which follows
naturally from the original presentation.
The stereo CD is a 16-bit medium with sampling at
44.1 kHz. Professional audio has been 20- or 24bit for some time, and there is increasing interest in
higher sampling rates both for recording and for
delivery into the home. Greater bit depths provide
extended dynamic range. Higher sampling rates
allow wider frequency response and the use of
anti-alias and reconstruction filters with more
favorable aural characteristics.
DTS 96/24 allows for 5.1channel sound tracks to
be encoded at a rate of 96kHz/24bits on DVDVideo titles.
When DVD-video appeared, it became possible to
deliver 24-bit, 96 kHz audio into the home, but only
in two channels, and with serious limitations on
picture. This capability has had little use.
DVD-audio allows 96/24 in six channels, but a new
player is needed, and only analog outputs are
provided, necessitating the use of the D/A
converters and analog electronics provided in the
player.
5
Page 8
DTS 96/24 offers the following:
1. Sound quality transparent to the original 96/24
master.
2.Full backward compatibility with all existing
decoders. (Existing decoders will output a 48
kHz signal)
3.No new player required: DTS 96/24 can be
carried on DVD-video, or in the video zone of
DVD-audio, accessible to all DVD players.
4. 96/24 5.1-channel sound with full-quality fullmotion video, for music programs and motion
picture soundtracks on DVD-video.
“DTS” and “DTS 96/24” are trademarks of Digital
Theater Systems, Inc.
Dolby Digital identifies the use of Dolby Digital
audio coding for such consumer formats as DVD
and DTV. As with film sound, Dolby Digital can
provide up to five full-range channels for left,
center, and right screen channels, independent left
and right surround channels, and a sixth (“.1”)
channel for low-frequency effects.
Dolby Surround Pro Logic II is an improved matrix
decoding technology that provides better spatiality
and directionality on Dolby Surround program
material; provides a convincing three-dimensional
soundfield on conventional stereo music
recordings; and is ideally suited to bring the
surround experience to automotive sound. While
conventional surround programming is fully
compatible with Dolby Surround Pro Logic
decoders, soundtracks will be able to be encoded
specifically to take full advantage of Pro Logic
playback, including separate left and right
surround channels. (Such material is also
compatible with conventional Pro Logic decoders.)
About Dolby Pro Logic IIx
Dolby Pro Logic IIx technology delivers a natural
and immersing 7.1-channel listening experience to
the home theater environment. A product of
Dolby's expertise in surround sound and matrix
decoding technologies, Dolby Pro Logic II x is a
complete surround sound solution that maximizes
the entertainment experience from stereo as well
as 5.1-channel encoded sources.
Dolby Pro Logic IIx is fully compatible with Dolby
Surround Pro Logic technology and can optimally
decode the thousands of commercially available
Dolby Surround encoded video cassettes and
television programs with enhanced depth and
spatiality. It can also process any high-quality
stereo or Advanced Resolution 5.1-channel music
content into a seamless 6.1- or 7.1-channel
listening experience.
The Dolby Headphone technology provides a
surround sound listening experience over headphones.
When listening to multichannel content such as
DVD movies over headphones, the listening
experience is fundamentally different than
listening to speakers. Since the headphone
speaker drivers are covering the pinna of the ear,
the listening experience differs greatly from
traditional speaker playback. Dolby utilizes
patented headphone perspective curves to solve
this problem and provides a non-fatiguing,
immersive, home theater listening experience.
II
II
Dolby Headphone also delivers exceptional 3D
audio from stereo material.
Manufactured under license from Dolby
Laboratories. “Dolby”, “Pro Logic”, and the doubleD symbol are trademarks of Dolby Laboratories.
Dolby Digital EX creates six full-bandwidth output
channels from 5.1-channel sources. This is done
using a matrix decoder that derives three surround
channels from the two in the original recording.
For best results, Dolby Digital EX should be used
with movies soundtracks recorded with Dolby
Digital Surround EX.
6
Page 9
Circle Surround II (CS-II) is a powerful and
versatile multichannel technology. CS-II is
designed to enable up to 6.1 multichannel surround
sound playback from mono, stereo, CS encoded
sources and other matrix encoded sources. In all
cases the decoder extends it into 6 channels of
surround audio and a LFE/subwoofer signal. The
CS-II decoder creates a listening environment that
places the listener “inside” music performances
and dramatically improves both hi-fi audio
conventional surround-encoded video material.
CS-II provides composite stereo rear channels to
greatly improve separation and image positioning–
adding a heightened sense of realism to both audio
and A/V productions.
CS-II is packed with other useful feature like dialog
clarity (SRS Dialog) for movies and cinema-like
bass enrichment (TruBass). CS-II can enable the
dialog to become clearer and more discernable in
movies and it enables the bass frequencies
contained in the original programming to more
closely achieve low frequencies–overcoming the
low frequency limitations of the speakers by full
octave.
HDCD system manufactured under license from
Microsoft. This product is covered by one or more
of the following: In the United States 5,479,168
5,638,074 5,640,161 5,808,574 5,838,274
5,854,600 5,864,311 5,872,531 and in Australia
669,114 with other patents pending.
Circle Surround II , Dialog Clarity, TruBass, SRS
and symbol are trademarks of SRS Labs, Inc.
Circle Surround II, Dialog Clarity and TruBass
technology are incorporated under license from
SRS Labs, Inc.
(SR8500 only)
HDCD® (High Definition Compatible Digital ®) is a
patented process for delivering on Compact Disc
the full richness and details of the original
microphone feed.
HDCD encoded CDs sound better because they
are encoded with 20-bits of real musical
information as compared to 16-bits for all other
CDs.
HDCD overcomes the limitation of the 16-bit CD
format by using a sophisticated system to encode
the additional four bits onto the CD while remaining
completely compatible with the CD format.
When listening to HDCD recordings, you hear
more dynamic range, a focused 3-D sound stage,
and extremely natural vocal and musical timbre.
With HDCD, you get the body, depth and emotion
of the original performance not a flat, digital
imitation.
7
Page 10
3. POWER AMPLIFIER ADJUSTMENT
Idling Current Alignment
1. Each of the measurement points are provided with the
two test points. Set a digital Voltage meter to DC voltage
input, connect the meter to the test points at both contact points.
2. After the setup above, turn on the main switch.
ing to the digital voltmeter readings. The target setting
value is the following table for each channel.
Settings: Master Volume — Minimum
Speaker out — No Load
Top lid — OPEN
Channel Alignment Point Measurement Point
Front L VR41 CN41
Center VR61 CN61
Front R VR51 CN51
Surround L VR42 CN42
Surround R VR52 CN52
Surround Back L VR62 CN62
Surround Back R VR71 CN71
Microprocessor (IC36), DSP(IC20 )Version and FLD Segment Check Mode.
1. While the power is on, PURE DIRECT, MRAC and 7.1CH INPUT buttons simultaneously more than 3 seconds.
The FL display shows “SERVICE MODE” for 2 seconds
then shows the model name.
SERVI CEMODE
SR8500
2. Press ENTER button, The software version of the micro-
processor (IC36) is displayed in the format below.
V0408051U
Year
MonthDateDest.
(Dest. : Destination)
3. Press ENTER button again, The software Serial Number
that is wirtten in the factory is displayed.
Microprocessor (IC36), DSP(IC20 )ƷVersion
ໜ༔ǛᄩᛐƢǔȢȸȉưƢŵ
1.
ǻȃȈƷᩓเǛλǕLJƢŵ
7.1CH IN PUT
“SERVICE MODE”
ᆔӸƕᘙᅆƞǕLJƢŵ
ƷȜǿȳǛӷƴኖ3ᅺˌɥƠLJƢŵ
ƱᘙᅆƕЈLJƢŵƴኖ2ᅺࢸƴೞ
PURE DIRECTŴ MRAC
ᘙᅆӏƼ
SERVI CEMODE
SR8500
2. ENTER
ȳƕഏƷǑƏƴᘙᅆƞǕLJƢŵ
ȜǿȳǛƠLJƢŵȞǤdzȳᲢ
IC36
ᲣƷȐȸǸȧ
V0408051U
Year
3.
ENTER
Software Serial No.
MonthDateDest.
ȜǿȳǛƠLJƢŵئưƖᡂLjฎLjƷ
ƕᘙᅆƞǕLJƢ
FL
Ŵ
MZXXXXXXXXXXX
4. Press ENTER button again, The software Type Number
is displayed.
SOFTTYPEXX
(XX is displayed in Hex)
5. Press ENTER button again, The Code Group Type
Number is displayed.
CODETYPEXXXX
(XXXX is displayed in Hex)
6. Press ENTER button again, The left half, right half and
center of the label area in the FLD light on and off each
other.
7. Press ENTER button again, The segments of the character area in the FLD fl ick in checker pattern.
8. Press ENTER button again, All the FL segments turns
off.
9. Press ENTER button again. Every time ENTER button
is pressed, DSP code is indicated in turn from NO.1 to
NO.28.
MZXXXXXXXXXXX
4. ENTER
Soft ware Type
ȜǿȳǛƠLJƢŵȞǤdzȳᲢ
ƕᘙᅆƞǕLJƢŵ
IC36
ᲣƷ
SOFTT YPEXX
(XX: Hex
5. ENTER
ǕLJƢŵ
ȜǿȳǛƠLJƢŵ
Code Group Type
ƕᘙᅆƞ
CODET YP E X X XX
(XXXX: Hex
6. ENTER
Ўƕʩʝƴໜ༔ǛጮǓᡉƠLJƢŵ
7. ENTER
๒ƠLJƢŵ
8. ENTER
9. ENTER
DSP Code IDƕNO.1
Ƣŵ
ȜǿȳǛƠLJƢŵFLᘙᅆƷӫŴŴɶځᢿ
ȜǿȳǛƠLJƢŵFLƷ
ȜǿȳǛƠLJƢŵFLƕμෞ໊ƠLJƢŵ
ȜǿȳǛƠLJƢŵ
Ɣǒ
Character
ENTER
NO.28
ȜǿȳǛƢࡇƴ
LJưƴᘙᅆƞǕLJ
ᢿЎƕໜ
)
)
CD0101020101
SIGDev.TYPVer.No.
No. : DISP CODE ID Dev. : Device ID SIG. : CODE SIG ID
TYP. : CODE TYPE ID Ver. : Version
10. Press ENTER button again to quit this mode.
CD0101020101
SIGDev.TYPVer.No.
No. : DISP CODE ID Dev. : Device ID SIG. : CODE SIG ID
TYP. : CODE TYPE ID Ver. : Version
10ENTER
LJƢŵ
9
ȜǿȳǛƠLJƢŵǵȸȓǹȢȸȉƸᚐᨊƞǕ
Page 12
Note: Step4, 5 is to check if CPU software is capable of
DSP code. “Software Type No” is to show what “DSP
Code Group” CPU is capable of. And vice versa.
Step 9 is to manage the 40 codes for DSP.
• When the unit is once turned into Service Mode, the
unit keeps this mode until the main power is turned
off. (Turning into stand-by mode does not make it
quit from Service Mode.) When the unit quits from
Service Mode, Information in the memory is also
cleared and the unit returns to the status when it is
out from the factory.
Product Reset
To reset the back up memory of the unit into the default status, follow the procedure below.
1. Turn of the unit and press SPEAKERS A/B and MULTI
button simultaneously more than 1.5 seconds.
2. After “DEFAULT” is displayed on FLD, power is turned
off once and turned of again, EEPROM is cleared to
the default status, µ-com is reset and the unit returns to
the normal status. (Software Serial Number will not be
cleared.)
Note: When the unit is shipped from the factory, the proce-
dure above must be done to set the unit to initial sta-
Personal notes:
10
Page 13
5. SYSTEM ERROR
ီࠝ౨Јᘙᅆŵ
ီࠝ౨Јᘙᅆŵ
ီࠝ౨Јᘙᅆŵ
ီࠝ౨Јᘙᅆŵ
ီࠝ౨Јᘙᅆŵ
ီࠝ౨Јᘙᅆŵ
ӭီࠝ౨Јᘙᅆŵ
5. SYSTEM ERROR
When the microcomputer detects a trouble, the following information is displayed on the FLD.
• After the error contents indication, Surround Mode is
initialized and returned Factory mode.
• The contents of the ERROR indication are the followings.
1. Trouble in DSP
If communication with DSP is troubled more than 2
seconds.
CHECKDSPROM
Indication is keep and sound is mute.
2. Trouble in DSP Code
The trouble of DSP Code was found.
CHECKDSPROM
3. Trouble in EEP-ROM
If data from EEPROM does not match.
CHECKE2P
4. Trouble in EEP-ROM IF
If communication with EEPROM is troubled more than 2
seconds.
ᙌԼϋᢿưƷီࠝႆဃƴϼྸŴᘙᅆǛᘍƍLJƢŵɼƴӲ
Device
ƱƷᡫီࠝǛ౨ЈƠLJƢŵ
ERROR
ƷཞƴǓLJƢŵ
ERROR
1. DSP
DSP
ᘙᅆࢸŴ
ᘙᅆƷϋܾƸɦᚡưƢŵ
ီࠝ౨Јᘙᅆŵ
ƱƷᡫɥƷɧφӳǛኖ ᅺ౨ЈƠƨŵ
SurroundMode
ƸИ҄ƞǕئЈᒵ
CHECKDSPROM
ᘙᅆཞƸƦƷLJLJư᪦٣Ƹ /WVG ཞ
2. DSP Code
DSPCode
ီࠝ౨Јᘙᅆŵ
ƷီࠝǛ౨ЈƠƨŵ
CHECKDSPROM
3. EEP-ROM
EEPROMData
ီࠝ౨Јᘙᅆŵ
ƷɧૢӳǛ౨ЈƠƨŵ
CHECKE2P
4. EEP-ROM IF
EEPROM
ီࠝ౨Јᘙᅆŵ
ƱƷᡫɧφӳƕኖ ᅺˌɥဃơƨŵ
CHECKE2PI F
5. Trouble in RS-232C
If communication of Panja with RS232C is troubled more
than 2 seconds.
CHECK2 32C
6. Trouble in 5V Supply
If 5V supply to DATA DIR is troubled.
CHECKPOW5
7. Trouble in Protection
CPU turns off the speaker output.
PROTECT
CHECKE2PI F
5. RS-232C
Panja
ɥ౨ЈƠƨŵ
ီࠝ౨Јᘙᅆŵ
ᡫƴRSCƱƷᡫɧφӳǛኖ ᅺˌ
CHECK2 32C
6. 5V
ီࠝ౨Јᘙᅆŵ
DATADIR
ƷီࠝǛ౨ЈƠƨŵ
CHECKPOW5
7. Protection
Speaker
ӭီࠝ౨Јᘙᅆŵ
ƔǒǛЈщǛഥNJLJƢŵ
PROTECT
11
Page 14
6. UPDATE FIRMWARE
ƷǢȃȗȇȸȈ૾ඥ
6. UPDATE FIRMWARE
Software for CPU and DSP can be updated.
Have update application software. (“UpgradeDSP.exe” and
“H8Download.exe”)
There are two mode of download, regarding to the target of
software as bellow.
Mode 1: Update DSP’s software to Flash-ROM.
This mode is to update the software for DSP.
The target devise is Flash-ROM (IC20) on CUP11762Z
(DSP PCB).
The Unit needs to be set update condition, by three front
keys.
Mode 2: Update CPU’s software to internal Flash-ROM.
This mode is to update the software for DSP.
The target devise is internal fl ash ROM of CPU (IC36) on
CUP11762Z (DSP PCB).
The Unit needs to be set to writing condition, by pushing
internal switch from back-panel.
The following items are required for updating.
RS232C Dsub-9 pin cable (female to female/Straight type)
Windows PC (98, NT, ME, 2000) with RS-232C port.
Update software to CPU.
Update software to DSP.
Use RS232C Dsub-9 pin cable (female to female/Straight
type) to connect PC and the unit.
COM port on PC needs to be set by dialog box for each program. COM port can be set from COM1 to COM5.
1. Put the “CPU update” folder into anywhere on your PC’s
hard disc.
ƷǢȃȗȇȸȈ૾ඥ (Mode 2)
CPU
1. "CPU update" ȕǩȫȀǛ PC ƷȏȸȉȇǣǹǯƴdzȔȸƠ
LJƢŵ
2. Connect PC and the unit with the RS-232C cable.
Hole of rear panel
ȪǢȑȍȫƴƋǔᆭ
3. Insert a thin rot to the hole and push the switch (SW10)
inside to turn on the switch.
4. Turn on the power of the unit.
Note: When the unit is into boot mode, stand-by LED is
not lights up.
2. ஜೞƱ PC Ǜ RS-232C ưዓƠLJƢŵ
SW10
3. ኬƍొǛƍஜೞƷȪǢȑȍȫƴƋǔᆭƔǒǹǤȃȁ
(SW10) ǛƠLJƢŵ
4. ஜೞƷᩓเǛλǕLJƢŵ
දᚡ : ஜೞƸȖȸȈȢȸȉƴƳǓŴStand-by LED Ƹໜ໊Ơ
LJƤǜŵ
15
Page 18
5. Launch "H8Download.exe" on PC.
H8FW2505
H8FW2505
H8FW2505
5. PC Ɣǒ "H8Download.exe" ǛȀȖȫǯȪȃǯƠƯឪѣƠLJ
Ƣŵ
6. Click Set Ports, and select the COM Port No.
7. Click other fi les... button in the dialog box to specify the
fi le (SR8500_yymmdd.mot) to be uploading. yymmdd in
fi lename is release date of software.
6. Set Ports ǛǯȪȃǯƠŴCOM ȝȸȈဪӭǛᢠ৸ƠLJƢŵ
7. other fi les… ǛǯȪȃǯƠƯŴǢȃȗȇȸȈȕǡǤȫ
(SR8500_yymmdd.mot) Ǜᢠ৸ƠƖLJƢŵ
H8FW2505
SR8500_yymmdd.mot
16
SR8500_yymmdd.mot
Page 19
8. Click Connect button. If the connection with the H8 µ-P
is successfully made, a dialogue box saying "Success to
the H8 micro processor connection" appears. (If the connection fails, error message will appear.)
8. Connect ǛǯȪȃǯƠLJƢŵH8 u-P ƱᡫዓƴыƢǔ
Ʊ
"Success to the H8 micro processor connection" ƷȀǤ
ǢȭǰƕᘙᅆƞǕLJƢŵ ᡫƴڂƢǔƱǨȩȸȡȃǻȸ
ǸƕᘙᅆƞǕLJƢŵ
9. Click Send button to start update.
h82505_38400.inf
10. If the fi rmware is updated successfully, a dialog box saying "Finished the fi rmware program sending” appears.
9. Send ǛǯȪȃǯƠǢȃȗȇȸȈǛڼƠLJƢŵ
10. ǽȕȈǦǧǢƷǢȃȗȇȸȈƕыƢǔƱŴ"Finished the
fi rmware program sending" ƷȀǤǢȭǰȜȃǯǹƕᘙᅆ
ƞǕLJƢŵ
17
Page 20
11. Click Close button to close the application.
ȐȸǸȧȳƷᄩᛐ
h82505_38400.inf
11. Close ǛǯȪȃǯƠƯǢȗȪDZȸǷȧȳǛơLJƢŵ
12. Disconnect Mains power cord.
13. Turn off the internal switch that has been turned on at
step 3.
14. Turn on the unit.
Firmware Version Check
To check the versions of the fi rmware, see "Microprocessor
(CPU), DSP Version and FLD Segment Check Mode" in
"SERVICE MODE" section.
12. ஜೞƷᩓเǛЏǓLJƢŵ
13. 3 ƷǹǤȃȁᲢSW10ᲣǛƠƯȖȸȈȢȸȉǛᚐᨊƠ
LJƢŵ
14. ᩓเǛλǕLJƢŵ
ȐȸǸȧȳƷᄩᛐ
ǽȕȈǦǧǢƷȐȸǸȧȳǛᄩᛐƠLJƢŵᄩᛐ૾ඥƸ
"SERVICE MODE" ϋƷ"Microprocessor (CPU), DSP
Version and FLD Segment Check Mode"ǛӋༀƠƯƘƩƞƍŵ
18
Page 21
7. WIRING DIAGRAM
SR7500/SR8500 Only PS7500/PS8500 Only
STANDBY PCB
CN66
CN65
CN71
AUX1
CN12 6P
POWER 2.0mm
CN71
CN21
BN13
CN42
AUX1
CN34 15P/P17
CN46 4P
BN22 15P
VOLUME 2.0mm
SELECTOR PCB
CN63
BN52 7P
AUX1 2mm
AUX1 PCB
SR8500/PS8500 Only
CN47 6P
CN22 15P
BN47 6P
AUX1 2.0mm
A, F, K, L, N only
U only
1920
Page 22
8. BLOCK DIAGRAM
SR7500/SR8500 only
USB MODULE
SR8500/PS8500 only
DVI PART
SR8500/PS8500 only
2221
Page 23
9. SCHEMATIC DIAGRAM
INPUT PCB
FROM TUNER PCB (F VERSION)
FROM DSP PCB (OTHER VERSION)
In Input Even Data[23:0] corresponds to 24-bit pixel data for 1-pixel/clock input mode and to the
first 24-bit pixel data for 2-pixels/clock mode.
Input data is synchronized with Input data clock (IDCK).
Data can be latched on the rising of the falling edge of IDCK depending on whether EDGE is
high or low, respectively.
Refer to TFT Panel Data Mapping in this document and DSTN Panel Data Mapping
application note (SiI-AN-0007-A), which tabulates the relationship between the input data to
the transmitter and output data from the Receiver
DIO23-
DIO0
See
SiI 160
Pin
Diagram
In Input Odd Data[23:0] corresponds to the second 24-bit pixel data for 2-pixels/clock mode. Tie
all pins to low when not in use.
Input data is synchronized with Input data clock (IDCK).
Data can be latched on the rising of the falling edge of IDCK depending on whether EDGE is
high or low, respectively
Dual Link is not supported. Refer to TFT Panel Data Mapping in this document and DSTN
Panel Data Mapping application note (SiI-AN-0007-A), which tabulates the relationship
between the input data to the transmitter and output data from the Receiver
IDCK 80 In Input Data Clock. Input data and control signals can be valid either on the falling or the rising
edge of IDCK as selected by the EDGE pin.
DE 78 Out Input Data Enable. This signal qualifies the active data area. DE is always required by the
transmitter and must be high during active display time and low during blanking time.
HSYNC
VSYNC
76
77
InInHorizontal Sync input control signal.
Vertical Sync input control signal.
CTL1
CTL2
CTL3
84
83
82
In
In
In
General Input control signal 1.
General Input control signal 2.
General Input control signal 3.
Configuration Pins
Pin Name Pin # Type Description
EDGE 24 In Data/Control Latching Edge. A LOW level indicates that all input signals(DIE/DIO[23:0],
HSYNC, VSYNC, DE and CTL[3:1] are latched on the falling edge of IDCK, while a HIGH
level(3.3V) indicates that all input signals are latched on the rising edge of IDCK.
PIXS 25 In Pixel Select. A LOW level indicates one pixel (up to 24-bits) per clock mode using DIE[23:0].
A HIGH level (3.3V) indicates two pixels (up to 48-bits) per clock mode using DIE[23:0] for
the first pixel and DIO[23:0] for the second pixel.
Power Management Pins
Pin Name Pin # Type Description
PD 26 In Power Down (active LOW). A HIGH level indicates normal operation. A LOW level indicates
power down mode. During power down mode, all data (DIE/DIO[23:0]), data enable (DE), clock
(IDCK) and control signals (HSYNC, VSYNC, CTL[3:1]), input buffers are disabled, all output
buffers are tri-stated and all internal circuitry is powered down.
IC16 (DVI PCB) : SiI 160
Functional Description
The SiI 160 is a DVI 1.0 compliant PanelLink transmitter in a compact package. It provides 48 bits for data
to allow for panel support up to UXGA. Figure 2 shows the functional blocks of the chip.
IC16 (DVI PCB) : SiI 160
EXT_SWING
DIE[23:0]
DIO[23:0]
DE
24
24
DATA
HSYNC
VSYNC
Encoder
0
Swing
Control
Tx0+
Tx0
Tx0-
HSYNC
VSYNC
CTL1
CTL2
CTL3
EDGE
PIXS
IDCK
Capture
Logic
DATA
Data
Encoder
CTL1
DATA
CTL2
Encoder
CTL3
Jitter
Filter
Figure 2. Functional Block Diagram
PLL
Tx1+
1
Tx1
Tx1-
Tx2+
2
Tx2
Tx2-
TxC+
TxC
TxC-
6261
Page 43
IC16 (DVI PCB) : SiI 160
Differential Signal Data Pins
Pin Name Pin # Type Description
TX0+
TX0-
TX1+
TX1-
TX2+
TX2-
TXC+
TXC-
EXT_SWING 32 Analog Voltage Swing Adjust. A resistor should tie this pin to AVCC. This resistor determines the
40
Analog
39
Analog
43
Analog
42
Analog
46
Analog
45
Analog
3534Analog
Analog
TMDS Low Voltage Differential Signal input data pairs.
These pins are tri-stated when PD is asserted.
TMDS Low Voltage Differential Signal input clock pair.
These pins are tri-stated when PD is asserted.
amplitude of the voltage swing. A 510Ω resistor is recommended for remote display
applications. For notebook computers, 680Ω is recommended.
Reserved Pins
Pin Name Pin # Type Description
RSVD 20 In
RSVD 21 In
RSVD 22 In
RSVD 23 In
RSVD 27 In
RSVD 28 In
RSVD 29 In
RSVD 87 In
Reserved. Must be tied HIGH for normal operation.
Reserved. Must be tied LOW for normal operation.
Reserved. Must be tied HIGH for normal operation.
Reserved. Must be tied HIGH for normal operation.
Reserved. Must be tied HIGH for normal operation.
Reserved. Must be tied HIGH for normal operation.
Reserved. Must be tied HIGH for normal operation.
Reserved. Must be tied HIGH for normal operation.
Power and Ground Pins
Pin Name Pin # Type Description
VCC 8,30,56,88 Power Digital Core VCC, must be set to 3.3V.
GND 7,31,57,67,79,89 Ground Digital Core GND.
IVCC 17,66,81,98 Power Input VCC, must be set to 3.3V.
AVCC 36,38,44 Power Analog VCC must be set to 3.3V.
AGND 33,37,41,47 Ground Analog GND.
PVCC1 18 Power Primary PLL Analog VCC must be set to 3.3V.
PVCC2 85 Power Filter PLL Analog VCC must be set to 3.3V.
PGND1 19 Ground PLL Analog GND. PGND1 should not be directly
PGND2 86 Ground PLL Analog GND. PGND2 should not be directly
connected to PGND2 before being connected to the
GROUND plane. They should be connected
individually to the GROUND plane.
connected to PGND1 before being connected to the
GROUND plane. They should be connected
individually to the GROUND plane.
63
Page 44
IC11 IC12 (DVI PCB) : SiI 1161
unctional Description
he SiI 1161 is a DVI 1.0 compliant PanelLink receiver in a compact package. It provides 24 or 48 bits for data
utput, and allows for panel support up to UXGA. Figure 1 shows the functional blocks of the chip.
PIXS
HS_DJTR
OCK_INV
SCL
SDA
EXT_RES
Control Registers
-----------
Termination
and
Equalization
Control
RX2+
RX2-
RX1+
RX1-
RX0+
RX0-
RXC+
RXC-
PDO#
STAG_OUT#
ST
VCR
VCR
VCR
VCR
Data Recovery
CH2
Data Recovery
CH1
Data Recovery
CH0
PLL
SYNC2
SYNC1
SYNC0
Channel
SYNC
Decoder
Panel
Interface
Logic
QE[23:0]
QO[23:0]
ODCK
DE
HSYNC
VSYNC
SCDT
CTL[3:1]
Figure 1. Functional Block Diagram
he PanelLink TMDS core accepts as inputs the three TMDS differential data lines and the differential clock. The
ore senses the signals on the link and properly decodes them providing accurate pixel data. The core outputs
he necessary sync signals (HSYNC, VSYNC), clock (ODCK), and a DE signal that goes high when the active
egion of the video is present.
he SCDT signal is output when there is active video on the DVI link and the PLL in the TMDS has locked on to
he video. SCDT can be used to trigger external circuitry, indicating that an active video signal is present or used
o place the device in power down when no signal is present (by tying it to PDO#). The EXT_RES component is
sed for impedance matching.
64
Page 45
IC11 IC12 (DVI PCB) : SiI 1161
Pin Descriptions
Output Pins
Pin NamePin # Type Description
QE23-
QE0
QO23-
QO0
ODCK 44 Out Output Data Clock. This output can be inverted using the OCK_INV pin. A low level on PD# or
DE 46 Out Output Data Enable. This signal qualifies the active data area. A HIGH level signifies active
HSYNC
VSYNC
CTL1
CTL2
CTL3
See
SiI 1161
Pin
Diagram
See
SiI 1161
Pin
Diagram
48
47
40
41
42
Out Output Even Data[23:0] corresponds to 24-bit pixel data for one pixel per clock input mode
and to the first 24-bit pixel data for two pixels per clock mode.
Output data is synchronized with output data clock (ODCK).
Refer to the TFT Panel Data Mapping section, which tabulates the relationship between the
input data to the transmitter and output data from the receiver.
A low level on PD# or PDO# will put the output drivers into a high impedance (tri-state) mode.
A weak internal pull-down device brings each output to ground.
Out Output Odd Data[23:0] corresponds to the second 24-bit pixel data for two pixels per clock
mode. During one pixel per clock mode, these outputs are driven low.
Output data is synchronized with output data clock (ODCK).
Refer to the TFT Panel Data Mapping section, which tabulates the relationship between the
input data to the transmitter and output data from the receiver.
A low level on PD# or PDO# will put the output drivers into a high impedance (tri-state) mode.
A weak internal pull-down device brings each output to ground.
PDO# will put the output driver into a high impedance (tri-state) mode. A weak internal pulldown device brings the output to ground.
display time and a LOW level signifies blanking time. This output signal is synchronized with
the output data. A low level on PD# or PDO# will put the output driver into a high impedance
(tri-state) mode. A weak internal pull-down device brings the output to ground.
OutHorizontal Sync output control signal.
Vertical Sync output control signal.
General output control signal 1. This output is not powered down by PDO#.
General output control signal 2.
General output control signal 3.
A low level on PD# or PDO# will put the output drivers (except CTL1 by PDO#) into a high
impedance (tri-state) mode. A weak internal pull-down device brings each output to ground.
Differential Signal Data Pins
Pin NamePin # Type Description
RX0+
RX0-
RX1+
RX1-
RX2+
RX2-
RXC+
RXC-
EXT_RES 96 Analog
90
Analog Receiver Differential Data Pins. TMDS Low Voltage Differential Signal input data pairs.
91
85
86
80
81
93
Analog Receiver Differential Clock Pins. TMDS Low Voltage Differential Signal input clock pair.
94
Impedance Matching Control. An external 390: resistor must be connected between AVCC
and this pin.
65
Page 46
IC11 IC12 (DVI PCB) : SiI 1161
Configuration Pins
Pin Name Pin # Type Description
MODE 99 In Mode Select Pin. Used to select between drop-in strap-selected operation, or register-
OCK_INV 100 In ODCK Polarity. A LOW level selects normal ODCK output. A HIGH level selects inverted
SCL I2C Port Clock. When pins 99 and 7 are tied LOW, pin 100 functions as an I2C port input
PIXS 4 In Pixel Select. A LOW level indicates one pixel (up to 24-bits) per clock mode using QE[23:0].
STAG_OUT# 7 In Staggered Output. A HIGH level selects normal simultaneous outputs on all odd and even
I2C_MODE#
ST 3 In/
SDA I2C Port Data. When pins 99 and 7 are tied LOW, pin 3 functions as an I2C port data I/O
HS_DJTR 1 In HSYNC De-jitter. This pin enables/disables the HSYNC de-jitter function. To enable the
programmable operation. To activate register-programmable operation, tie both pin 99 and
pin 7 LOW. Refer to Selecting SiI 1161 (Programmable) Mode on page 31 for more details.
HIGH=161B (Compatible) Mode – strap selections are used to set part operation. Internal
registers controlling non strap-selectable functions are reset to their default values.
LOW=1161 (Programmable) Mode – I
2
C registers are used to program part operation.
ODCK output. All other output signals are unaffected by this pin. They will maintain the same
timing no matter the setting of OCK_INV pin
clock. The slave I
2
C function does not ever try to extend cycles by pulling this pin low, so the
pin remains input-only at all times. Refer to Selecting SiI 1161 (Programmable) Mode on
page 31 for more details. This pin accepts 3.3V signaling only; it is not 5V-tolerant.
A HIGH level indicates two pixels (up to 48-bits) per clock mode using QE[23:0] for first pixel
and QO[23:0] for second pixel.
data lines. A LOW level selects staggered output drive. This function is only available in two
pixels per clock mode.
2
This pin must be tied LOW to put the receiver into I
C mode. Refer to Selecting SiI 1161
(Programmable) Mode on page 31 for more details.
Output Drive. A HIGH level selects HIGH output drive strength. A LOW level selects LOW
Out
output drive strength.
signal. Refer to Selecting SiI 1161 (Programmable) Mode on page 31 for more details. This
pin accepts 3.3V signaling only; it is not 5V-tolerant.
HSYNC de-jitter function this pin should be HIGH. To disable the HSYNC de-jitter function this
pin should be LOW.
Power Management Pins
Pin Name Pin # Type Description
SCDT 8 Out Sync Detect. A HIGH level is outputted when DE is actively toggling indicating that the link is
PDO# 9 In Output Driver Power Down (active LOW). A HIGH level indicates normal operation. A LOW level
PD# 2 In Power Down (active LOW). A HIGH level indicates normal operation. A LOW level indicates
alive. A LOW level is outputted when DE is inactive, indicating the link is down. Can be
connected to PDO# to power down the outputs when DE is not detected. The SCDT output itself,
however, remains in the active mode at all times.
puts all the output drivers only (except SCDT and CTL1) into a high impedance (tri-state) mode.
A weak internal pull-down device brings each output to ground. PDO# is a sub-set of the PD#
description. The chip is not in power-down mode with this pin. SCDT and CTL1 are not tri-stated
by this pin.
power down mode. During power down mode, all the output drivers are put into a high
impedance (tri-state) mode. A weak internal pull-down device brings each output to ground.
Additionally, all analog logic is powered down, and all inputs are disabled. Driving PD# LOW
disables all internal logic and outputs, including SCDT and clock detect functions; it also resets all
internal programmable registers to their default states.
66
Page 47
IC11 IC12 (DVI PCB) : SiI 1161
K
<
Power and Ground Pins
Pin Name Pin # Type Description
VCC 6,38,67 Power Digital Core VCC, must be set to 3.3V.
GND 5,39,68 Ground Digital Core GND.
OVCC 18,29,43,57,78 Power Output VCC, must be set to 3.3V.
OGND 19,28,45,58,76 Ground Output GND.
AVCC 82,84,88,95 Power Analog VCC must be set to 3.3V.
AGND 79,83,87,89,92 Ground Analog GND.
PVCC 97 Power PLL Analog VCC must be set to 3.3V.
PGND 98 Ground PLL Analog GND.
Q121 (VIDEO CONVERTER PCB) : HN1K05FU
Equivalent Circuit
6 5 34
Q1
(Q1, Q2 common)
(top view)
Q2
21
Marking
Switching Time Test Circuit
(a) Test circuit (b) V
I
1.5 V
0
10 ms
V
IN
IN
D
L
50 9
R
V
OUT
DD
V
= 1.5 V
DD
D.U.
1%
V
: tr, tf< 5 ns
IN
(Z
= 50 W)
out
Common Source
Ta = 25°C
654
K
IN
V
V
(c) V
GS
OUT
DS
321
1.5 V
V
V
DS (ON)
DD
0
10%
90%
90%
10%
t
t
r
f
ton t
off
67
Page 48
IC38, IC39 (DSP PCB) : TC74VHC157
68
Page 49
T
T
T
A
A
A
T
T
T
A
A
A
IC94 (COMPONENT PCB) : NJM2586
■GENERAL DESCRIPTION ■PACKAGE O UTLINE
The NJM2586 is a wide band 3-input 1-output 3-circuit video
amplifier. It is suitable for Y, Pb, and Pr signal because frequency
range is 50MHz.The NJM2586 is suitable for AV receiver, STB,
and other high quality AV systems.
1 I/O UHS0, GPIO18 Mode Select Bit 0, General Purpose I/O
2 I/O UHS1, GPIO19 Mode Select Bit 1, General Purpose I/O
3INTREQControl Port Interrupt Request
4 I FA1, FSCDIN Host Address Bit One or SPI Serial Control Data Input
5 I/O GPIO20General Purpose I/O
6 I FA0, FSCCLK Host Parallel Address Bit Zero or Serial Control Port Clock
7 I/O FHS2,
FSCDIO,
FSCDOUT
8 I/O GPIO21General Purpose I/O
9FDAT7DSP AB Bidirectional Data Bus
10VDD62.5V Supply Voltage
11VSS62.5V Ground
12FHS0, FWR,
FDS
13 O FHS1, FRD,
FR/W
14FDAT6DSP AB Bidirectional Data Bus
15 I FCSHost Parallel Chip Select, Host Serial SPI Chip Select
16 O FINTREQControl Port Interrupt Request
17FDBCKReserved
18FDAT5DSP AB Bidirectional Data Bus
19FDAT4DSP AB Bidirectional Data Bus
20VDD72.5V Supply Voltage
21VSS72.5V Ground
22FDAT3DSP AB Bidirectional Data Bus
23FDBDAReserved
24FDAT2DSP AB Bidirectional Data Bus
25DBDADebug Data
26DBCKDebug Clock
27FDAT1DSP AB Bidirectional Data Bus
28TESTReserved
29FDAT0DSP AB Bidirectional Data Bus
30 I/O NV_WE,
GPIO11
122PLLVSSPLL Ground Voltage
123FILT2Phase Locked Loop Filter
124FILT1Phase-Locked Loop Filter
125PLLVDDPLL Supply Voltage
126 O CLKOUT,
XTALO
127 I CLKIN, XTALI External Clock Input/Crystal Oscillator Input
128CLKSELDSP Clock Select
129 I/O CS, GPIO9Host Parallel Chip Select, General Purpose I/O
130 I/O A0, GPIO13Host Parallel Address Bit 0, General Purpose I/O
131 I FSDATAN1PCM Audio Data Input One
132VDD42.5V Supply Voltage
133VSS42.5V Ground
134 I FSCLKN1,
STCCLK2
135SCSHost Serial SPI Chip Select
136 I SCDINSPI Serial Control Data Input
137VSS52.5V Ground
138VDD52.5V Supply Voltage
139 I/O A1, GPIO12Host Address Bit 1, General Purpose I/O
140 I/O SCDOUT,
SCDIO
141 I/O HINBSY,
GPIO8
142SCCLKSerial Control Port Clock
143 I/O UHS2,
CS_OUT,
GPIO17
144 I RESETMaster Reset Input
Digital Audio Output 4, General Purpose I/O
DSP C Bidirectional Data Bus, General Purpose I/O
DSP C Bidirectional Data Bus, General Purpose I/O
Digital Audio Output 3, S/PDIF Transmitter
PCM Audio Input Bit Clock
DSP C Bidirectional Data Bus, General Purpose I/O
DSP C Bidirectional Data Bus, General Purpose I/O
DSP C Bidirectional Data Bus, General Purpose I/O
Frame Clock Data Request Out
PCM Audio Data Input Number Two
Host Write Strobe, Host Data Strobe, General Purpose I/O
Host Parallel Output Enable, Host Parallel R/W, General
Purpose I/O
Crystal Oscillator Output
PCM Audio Input Bit Clock
Serial Control Port Data Input and Output
Input Host Message Status, General Purpose I/O
Mode Select Bit 2, External Serial Memory Chip Select,
General Purpose I/O
serial audio data line. The frequency of the left/right clock must be at the audio sample rate, Fs.
Serial Clock
Master Clock
several standard audio sample rates and the required master clock frequency.
Digital Power
ing Conditions for appropriate voltages.
Ground
Logic Power
ommended Operating Conditions for appropriate voltages.
Serial Audio Data Output
MCLK Divider
FILT+
REFGND
FILT+
Voltage Reference
VCOM
+
AINR
-
AINR
VA
GND
AINLAINL+
TST
M1
M0
) - The device enters a low power mode when low.
(
(
Input
(
Input
(
Input
(
) - Ground reference. Must be connected to analog ground.
Input
(
Input
(Input
AINL-
AINL+
AINR-
AINR+
-In Slave mode, LRCK and SCLK become input. (FIXED LOW)
(Input)
) - Determines which channel, Left or Right, is currently active on the
Input
) - Serial clock for the serial audio interface.
) - Clock source for the delta-sigma modulator and digital filters. Table 1 illustrates
)-Positive power supply for the digital section. Refer to the Recommended Operat-
)- Determines the required signal level for the digital input/output. Refer to the Rec-
(
Output
) - (FIXED LOW)
+
LP Filter
-
S/H
DAC
+
-
S/H
DAC
) - Output for two’s complement serial audio data.
Serial Outpu t Interface
Q
QLP Filter
Digital
Decimation
Filter
Digital
Decimation
Filter
High
Pass
Filter
High
Pass
Filter
RST
DIF
M/S
HPF
DIV
MODE0
MODE1
HPF
DIF
M0
M1
TST
AINL+
AINL-
VA
AINR+
AINR-
VCOM
REF_GND
FILT+
I
I
I
I
I
I
I
I
I
I
O
I
O
the indeterminate DC offsets introduced by the analog buffer stage and the analog modulator. The firstorder high pass filter response characteristics are detailed in the Digital Filter specifications table. The filter response scales linearly with sample rate.
Digital Interface Format
12
and serial data is defined by the Digital Interface Format selection. Refer to Figures 8 and 9.
Mode Selection
13,
14
(FIXED LOW)
Test Pin
15
Differential Left Channel Analog Input
16,
modulators via the AINL+/- pins. The full scale differential analog input level is specified in the Analog
17
Characteristics Specification table.
Analog Power
19
ating Conditions for appropriate voltages.
Differential Right Channel Analog Input
20,
modulators via the AINR+/- pins. The full scale differential analog input level is specified in the Analog
21
Characteristics Specification table.
Common Mode Voltage
22
the common mode voltage of the CS5361. VCOM is not buffered and the maximum current is 10 uA.
Reference Ground
23
to analog ground.
Positive Voltage Reference
24
Requires the capacitive decoupling to GND as shown in the Typical Connection Diagram.
(Input)
(
) -(FIXED LOW)
Input
-
This pin needs to be connected to GND.
(
)-Positive power supply for the analog section. Refer to the Recommended Oper-
Input
(
Input
High Pass Filter Enable
11
) -
(Input
(
(Output)
The device includes a high pass filter after the decimator to remove
) - The required relationship between the Left/Right clock, serial clock
Input
(
) - Signals are presented differentially to the delta-sigma
Input
(
) -Signals are presented differentially to the delta-sigma
Input
-
Nominally 2.5 volts; can be used to bias the analog input circuitry to
) - Ground reference for the internal sampling circuits and must be connected
Output
-
)
Positive reference voltage for the internal sampling circuits.
(
76
Page 57
IC81 (FRONT PCB) : NJU3430FG1
RST
SI
CS
CLK
RS
OSC1
OSC
2
VDD
V
V
SS
FDP
RESET
8bits
Shift
Reg.
Timing
CR
Gen.
OSC.
Instruction
Dec oder
State
Display
Reg.
Control
Line
Address
Address
Read
Address
Counter
Selector
Counter
No.SYMBOLI/OF U N C T I O N
MK RAM
16x2bit
CG RAM
35x8bit
CG ROM
8,400bit
DD RAM
16x8bit
Icon
Segment
Port
Timing
Driver
Driver
Driver
Driver
MK1~MK2
S
1~S35
P 1
T
1~T16
57VDD-Power Source: VDD=+3.0 to 5.5V
49VSS-GND: VSS=0V
48VFDP-
50OSC1I
51OSC2O
VFD Driving Power Sourse
V
DD-20V to V DD-45V
CR Oscillation Terminal
External R and C connect to these terminals.
(Target f
OSC=360kHz)
Serial Clock Input Terminal
54CLKI
The serial data input synchronizing the rise edge of this
terminal.
Chip Select Terminal
53CSI
When the CS terminal is "H" the serial data input is not
available.
55SII
Serial Data Input Terminal
The data input is MSB first.
Register Selection Signal Input Terminal
56RSI
RS="0" : Instruction Register
RS="1" : Data Register
LED
102 P21/TIOCB3I/O,I/OOIMIC_ENABLEMIC Enable
103 P22/TIOCC3I/O,I/OIIMIC_DETECT--MIC Input Detection
104 P23/TIOCD3I/O,I/OIISPKC_SW--Speaker C Switch
105 P24/TIOCA4I/O,I/OOISPKC_CONTC-Relay Control
106 P25/TIOCB4I/O,I/OOIKILLFLASHKill Flasher OUT
107 P26/TIOCA5I/O,I/O T_OUTORC_OUTLRC BUS OUT
108 P27/TIOCB5I/O,I/O T_OUTOM_RC_OUTLRC BUS MULT OUT
109 P17/TIOCB2/
TCLKD
110 P16/TIOCA2/
I/O,I/
IIM_RC_INLH Multi RC5 IN Detect Signal
O,I/O
I/O,I/O,IINTINT WAKEUP-Standby Mode Release
~IRQ1
111 P15/TIOCB1/
TCLKC
112 P14/TIOCA1/
I/O,I/
T_INIVSYNC-V-sync Det. & Change OSD
O,I/O
I/O,I/O,IINTI_P_DPWNL-Power Down Detect
~IRQ0
113 P13/TIOCD0/
TCLKB
114 P12/TIOCC0/
TCLKA
I/O,I/
O,I/O
I/O,I/
O,I/O
OO KILLIRHLKill to IR Input Signal
OIDC_OUT1LH DC Triger1
115 P11/TIOCB0I/O,I/OOIDC_OUT2LH DC Triger2
116 P10/TIOCA0I/O,I/OT_INIRC_IN-IR In for RC-5
117 VssIYESIVSS--GND
118 P2VccIYESIVCC--+5V'
119 P37/TxD4I/O,OSOOUSB_CSDAO--Serial Data IN from USB Module (USB_CSDAI)
This is not used.
79
Page 60
IC36 (DSP PCB): H8S/2505(HD64F2505)
Pin
Por t
mode = 7
I/OUseSTBY Name
Port Setting
Act.init
Note
120 P36/RxD4I/O,ISIIUSB_CSDAISerial Data OUT from USB Module (USB
CSDAO) This is not used.
121 P35/SCK1/
SCK4/SCL0/
I/O,I/O,I/
O,I/O,I
SCIUSB_CSCLSerial Clock from USB Module. This is not used.
~MRES
131 P73/TMO1I/O,OOI_CEFLLLFL Driver Chip Select
132 P72/TMO0I/O,OIIUSB_MUTEfor Audio Mute Control. This is not used.
133 P71/TMRI23/
TMCI23
134 P70/TMRI01/
I/O,O,OIIUSB_PLL_
for Clock Control. This is not used.
UNLOCK
I/O,O,OOICLK_SWTC74VHC157 SEL
TMCI01
135 PG4I/OOI_SCSLH DSP CHIP ENABLE
136 PG3I/OOI_RSTDSPLLDSP
137 PG2I/OOI_FCSLHDSP CHIP ENABLE
138 PG1/~IRQ7I/O,IINTIIRQ7--RDS Clock
139 PG0/~IRQ6I/O,IINTIUSB_CCEL-Chip Enable for SPI. This is not used.
140 PE0I/OOINC--open
141 PE1I/OOI_CEEXLH P-Exp(Video)Sel A
142 PE2I/OOIY_OSDHLY/C_OSD_IC_BYPASS
143 PE3I/OOICVBS_OSDHLCVBS_OSD_IC_BYPASS
144 PE4I/OOI_CEOSDLHVideo Circuit
80
Page 61
IC23 (DSP PCB) : CS4382
81
Page 62
IC23 (DSP PCB) : CS4382
82
Page 63
IC23 (DSP PCB) : CS4382
IC78 (VIDEO PCB) : LC74781
IC78 (VIDEO PCB) : LC74781
Pin Functions
Pin No.SymbolFunctionDescription
1V
2Xtal
3Xtal
4CTRL1Crystal oscillator input switching
5BLANKBlanking outputsync signal when MOD0 is high.) Outputs the crystal oscillator clock during reset (when the
6OSC
7OSC
8CHARACharacter outputexternal synchronization signal is present or not. Outputs a high level when the synchronization
9CSEnable input
10SCLKClock input
11SINData inputSerial data input. A pull-up resistor is built in (hysteresis input).
12V
13CV
14NCMust be either connected to ground or left open.
15CV
16V
17SYN
18SEP
19SEP
20SEP
21CTRL2NTSC/PAL-M switching inputPAL-N formats. A low level selects NTSC after a reset. The microprocessor command NTSC,
22CTRL3SEP
23RSTReset inputSystem reset input. A pull-up resistor is built in (hysteresis input).
24V
1GroundGround connection (digital system ground)
SS
IN
Crystal oscillator connection
OUT
Used to connect the crystal oscillator and capacitor used to generate the internal
synchronization signal, or to input an external clock (2fsc or 4fsc).
Switches between external clock input mode and crystal oscillator mode.
Low = crystal oscillator mode, high = external clock mode
Outputs the blank signal (the OR of the character and border signals). (Outputs a composite
RST pin is low), but can be set up to not output this signal by microprocessor command.
IN
LC oscillator connection
OUT
Connections for the coil and capacitor that form the oscillator that generates the character
output dot clock.
Outputs the character signal. (Functions as the external synchronization signal discrimination
signal output pin when MOD0 is high, and outputs the state of the judgment as to whether the
signal is present.) Outputs the dot clock (LC oscillator) during reset, but can be set up to not
output this signal by microprocessor command.
Serial data input enable input. Serial data input is enabled when low. A pull-up resistor is built in
(hysteresis input).
Serial data input clock input.
A pull-up resistor is built in (hysteresis input).
2Power supplyComposite video signal level adjustment power supply pin (analog system power supply).
DD
Video signal outputComposite video signal output
OUT
Video signal inputComposite video signal input
IN
1Power supplyPower supply (+5 V: digital system power supply)
DD
Video signal input for the built-in sync separator circuit (Used for either horizontal
Sync separator circuit inputsynchronization signal or composite sync signal input when the built-in sync separator circuit is
IN
Sync separator circuit bias voltage Built-in sync separator circuit bias voltage monitor pin
C
not used.)
Built-in sync separator circuit composite sync signal output. (When MOD1 is high, outputs a high
Composite sync signal outputlevel during internal synchronization and a low level during external synchronization.) (Outputs
OUT
Vertical synchronization Inputs a vertical synchronization signal created by integrating the SEP
IN
signal inputintegrator must be attached at the SEP
the SYN
input signal when the internal sync separator circuit is not used.)
IN
pin. This pin must be tied to VDD1 if unused.
OUT
pin output signal. An
OUT
The setting indicated by this pin takes priority in switching between the NTSC, PAL, PAL-M and
PAL, PAL-M, or PAL-N setting is valid. High = PAL-M format.
input control
IN
1Power supply (+5 V)Power supply (+5 V: digital system power supply)
DD
Controls whether or not the VSYNC signal is input to the SEP
high = VSYNC not input.
HGK1A090Y
00M10BW248010 PANELFRONT AL (BLACK)CKM1A159ZC23
00M10BW248210 PANELFRONT AL (SILVER)CKM1A159ZC40
00M10BW248130 PANELFRONT AL (GOLD)CKM1A159XC2
00M10BW248110 PANELFRONT AL (GOLD)CKM1A159ZC24
00M10BW248110 PANELFRONT AL (GOLD)CKM1A159ZC24
N1B00M10BW24801000M10BW248010 PANELFRONT AL (BLACK)CKM1A159ZC23
N1G00M10BW24811000M10BW248110 PANELFRONT AL (GOLD)CKM1A159ZC24
N1S00M10BW24821000M10BW248210 PANELFRONT AL (SILVER)CKM1A159ZC40
00M10BW002010 ARMDOOR ARM BLACKCKG1A046R4K92
00M10BW002210 ARMDOOR ARM SILVERCKG1A046R6G13
00M10BW002110 ARMDOOR ARM GOLDCKG1A046RFD4
00M10BW002110 ARMDOOR ARM GOLDCKG1A046RFD4
00M10BW002110 ARMDOOR ARM GOLDCKG1A046RFD4
N1B00M10BW00201000M10BW002010 ARMDOOR ARM BLACKCKG1A046R4K92
N1G00M10BW00211000M10BW002110 ARMDOOR ARM GOLDCKG1A046RFD4
N1S00M10BW00221000M10BW002210 ARMDOOR ARM SILVERCKG1A046R6G13
00M10BW851270 USER GUIDEUSER MANUAL
00M10BW851270 USER GUIDEUSER MANUAL
00M10BW851110 USER GUIDEUSER MANUAL
00M10BW851350 USER GUIDEUSER MANUAL
00M10BW851350 USER GUIDEUSER MANUAL
CQX1A967Z
CQX1A967Z
CQX1A968Z
CQX1A966Z
CQX1A966Z
NOTE : "nsp" PART IS LISTED FOR REFERENCE ONLY, MARANTZ WILL NOT SUPPLY THESE PARTS.
89
Page 68
SR7500 / PS7500
(
)
(
)
/
/
/
/
p
/
p
/
p
/
p
/
p
/
p
/
R
/
R
/
R
/
p
0
0
S
/
p
/
p
/
p
Y
/
p
/
p
/
p
/
p
/
p
/
p
p
p
L
/
p
/
p
/
p
/
p
7
/
p
/
p
/
p
/
p
/
p
7
/
p
/
p
/
p
7
P.C.B.
NAME
POS. NO.
VERS.
COLOR
N1B00M10BW85131000M10BW851310 USER GUIDEUSER MANUAL NCQX1A964Z
N1G00M10BW85131000M10BW851310 USER GUIDEUSER MANUAL NCQX1A964Z
N1S00M10BW85131000M10BW851310 USER GUIDEUSER MANUAL NCQX1A964Z
U1Bns
Regarding to all parts of parts code 00MFS20xxx2xx, replace
only with Wickmann-Werke GmbH, Type 372 non glass type
fuse.
NOTE ON SAFETY :
SymbolFire or electrical shock hazard. Only original
parts should be used to replaced any part marked with
symbol . Any other component substitution (other
than original type), may increase risk of fire or electrical
shock hazard.