14.EXPLANATION OF DSP......................................................................................................................... 39
15.ELECTRICAL PARTS LIST .................................................................................................................... 41
Compact disc player
Please use this service manual with referring to the user guide ( D.F.U. ) without fail.
修理の際は、必ず取扱説明書を準備し操作方法を確認の上作業を行ってください。
Printed in Japan
R
model CD-7
4822 725 51186
First Issue 1999.03
355K855010 MIT
MARANTZ DESIGN AND SERVICE
Using superior design and selected high grade components, MARANTZ company has created the ultimate in stereo sound.
Only original MARANTZ parts can insure that your MARANTZ product will continue to perform to the specifications for which
it is famous.
Parts for your
MARANTZ equipment are generally available to our National Marantz Subsidiary or Agent.
ORDERING PARTS :
Parts can be ordered either by mail or by Fax.. In both cases, the correct part number has to be specified.
The following information must be supplied to eliminate delays in processing your order :
1. Complete address
2. Complete part numbers and quantities required
3. Description of parts
4. Model number for which part is required
5. Way of shipment
6. Signature : any order form or Fax. must be signed, otherwise such part order will be considered as null and void.
CAUTION : After servicing this appliance and prior to returning to customer, measure the resistance between either primary AC
cord connector pins ( with unit NOT connected to A C mains and its Power switch ON ), and the face or F ront Panel of product and
controls and chassis bottom.
Any resistance measurement less than 1 Megohms should cause unit to be repaired or corrected before A C po wer is applied, and
verified before it is return to the user/customer.
Ref. UL Standard No. 1492.
In case of difficulties, do not hesitate to contact the Technical
Department at above mentioned address.
Improvement may result in changes in specifications and
design without notice.
1
2. SERVICING HINTS
3. SERVICE TOOLS
Audio signals disc4822 397 30184
Disc without errors (SBC444)+
Disc with DO errors, black spots and fingerprints (SBC444A)4822 397 30245
Disc (65 min 1kHz) without no pause4822 397 30155
Max. diameter disc (58.0 mm)4822 397 60141
Torx screwdrivers
Set (straight)4822 395 50145
Set (square)4822 395 50132
13th order filter4822 395 30204
Allen wrench (No. 3)
2
4. SERVICE MODE
1. How to enter into the Service Mode
Turn the power on while pressing [PLAY]+[OPEN/
CLOSE] buttons together.
1VSSA1*analog ground 1
2VDDA1* analog supply voltage 1
3D1unipolar current input (central diode signal input)
4D2unipolar current input (central diode signal input)
5D3unipolar current input (central diode signal input)
6VRLreference voltage input for ADC
7D4unipolar current input (central diode signal input)
8R1unipolar current input (satellite diode signal input)
9R2unipolar current input (satellite diode signal input)
10IrefTcurrent reference output for ADC calibration
11VRHreference voltage output from ADC
12VSSA2* analog ground 2
13SELPLLselects whether internal clock multiplier PLL is used
14ISLICEcurrent feedback output from data slicer
15HFINcomparator signal input
16VSSA3* analog ground 3
17HFREFcomparator common mode input
18Irefreference current output pin (nominally 0.5VDD )
19VDDA2* analog supply voltage 2
20TEST1test control input 1; this pin should be tied LOW
21CRINcrystal/resonator input
22CROUTcrystal/resonator output
23TEST2test control input 2; this pin should be tied LOW
24CL1616.9344 MHz system clock output
25CL1111.2896 or 5.6448 MHz clock output (3-state)
26RAradial actuator output
27FOfocus actuator output
28SLsledge control output
29TEST3test control input 3; this pin should be tied LOW
30VDDD1(P)* digital supply voltage 1 for periphery
31DOBMbi-phase mar k output (externally buffered; 3-state)
32VSSD1* digital ground 1
33MOTO1motor output 1; versatile (3-state)
34MOTO2motor output 2; versatile (3-state)
35SBSYsubcode block sync output (3-state)
36SFSYsubcode frame sync output (3-state)
37RCKsubcode clock input
38SUBP-to-W subcode output bits (3-state)
39VSSD2* digital ground 2
40V5versatile output pin 5
41V4versatile output pin 4
42V3versatile output pin 3 (open-drain)
43KILLkill output (programmable; open-drain)
44EFC2 error flag; output only defined in CD ROM modes and 1fs modes (3-state)
45DATAserial data output (3-state)
46WCLKword clock output (3-state)
47VDDD2(P)* digital supply voltage 2 for periphery
48SCLKserial bit clock output (3-state)
49VSSD3* digital ground 3
50CL44.2336 MHz microcontroller clock output
51SDAmicrocontroller interface data I/O line (open-drain output)
52SCLmicrocontroller interface clock line input
53RABmicrocontroller interface R/W and load control line input (4-wire bus mode)
54SILDmicrocontroller interface R/W and load control line input (4-wire-bus mode)
55n.c.not connected
56VSSD4* digital ground 4
57RESETpower-on reset input (active LOW)
58STATUSservo interrupt request line/decoder status register output (open-drain)
59VDDD3(C)* digital supply voltage 3 for core
60C2FAILindication of correction failure output (open-drain)
61CFLGcorrection flag output (open-drain)
62V1versatile input pin 1
63V2versatile input pin 2
64LDONlaser drive on output (open-drain)
Note : All supply pins must be connected to the same external power supply voltage.
7000 : TDA1302T
PINSYMBOLDESCRIPTION
1O4output of diode current amplifier 4
2O6output of diode current amplifier 6
3O3output of diode current amplifier 3
4O1output of diode current amplifier 1
5O5output of diode current amplifier 5
6O2output of diode current amplifier 2
7LDONcontrol pin for switching the laser
ON and OFF
8VDDLlaser supply voltage
9RFEequalized output voltage of sum
signal of amplifiers 1 to 4
10RFunequalized output
11HGcontrol pin for gain switch
12LScontrol pin for speed switch
13CLexternal capacitor
14ADJreference input normally
connected to ground via a resistor
15GND0 V supply; substrate connection
IECIN15E007high sensitivity IEC input
IECIN06IPP04 TTL level IEC input
IECSEL7IUP04 select IEC input 0 or 1 (0 = IECIN0; 1 = IECIN1); this input has an internal pull-up
IECO8OPFH3 digital audio output for optical and transformer link
IECOEN9IUP04digital audio output enable (0 = enabled; 1 = disabled/3-state); this input has an
TESTB10IPP04 enable factory test input (0 = normal application; 1 = scan mode)
TESTC11IPP04 enable factory test input (0 = normal application; 1 = observation outputs)
UNLOCK12 OPP41A PLL out-of-lock (0 = not locked; 1 = locked); this output can drive an LED
FS3213 OPP41A indicates sample frequency = 32 kHz (active LOW); this output can drive an LED
FS4414 OPP41A indicates sample frequency = 44.1 kHz (active LOW); this output can drive an LED
FS4815 OPP41A indicates sample frequency = 48 kHz (active LOW); this output can drive an LED
CHMODE16OPP41A use of channel status block (0 = professional use; 1 = consumer use); this output
V
DDD2
V
SSD2
RESET19IDP09 initialization after power-on, requires only an external capacitor connected to V
PD20IPP04enable power-down input in the standby mode (0 = normal application; 1 = standby
LADDR22IPP04 microcontroller interface address switch input (0 = 000001; 1 = 000010)
LMODE23IPP09microcontroller interface mode line input
LCLK24IPP09microcontroller interface clock line input
LDATA25IOF24 microcontroller interface data line input/output
STROBE26IDP04 strobe for control register (active HIGH); this input has an internal pull-down resistor
UDAVAIL27OPF23 synchronization for output user data (0= data available; 1 = no data)
TESTA28IPP04enable factory (scan) test input (0 = normal application; 1 = test clock enable)
COPY29OPP41A copyright status bit (0 = copyright asserted; 1 = no copyright asserted); this output
INVALID30IOD24 validity of audio sample input/output (0 = valid sample; 1 = invalid sample); this pin
DEEM31OPF23 pre-emphasis output bit (0 = no pre-emphasis; 1 = pre-emphasis)
MUTE32IUP04 audio mute input (0 = permanent mute; 1 = mute on receive error); this pin has an
I2SSEL33IUP04 select auxiliary input or normal input in transmit mode
SDAUX34IPP04auxiliary serial data input; I
SD35IOF24 serial audio data input/output; I
WS36IOF24 word select input/output; I
SCK37IOF29serial audio clock input/output; I
2
SOEN38IUP04 serial audio output enable (0 = enabled; 1 = disabled/3-state); this input has an
I
SYSCLKI39IPP09system clock input (transmit mode)
SYSCLKO40OPFA3 system clock output (receive mode)
V
SSD1
V
DDD1
CLKSEL43IUP04 select system clock (0 = 384f
RC
int
1E029PLL loop filter input
2E029decoupling internal reference voltage output
3E008analog supply voltage
4E004analog ground
resistor
internal pull-up resistor
17E008digital supply voltage 2
18E009digital ground 2
41E009digital ground 1
42E008digital supply voltage 1
44E029integrating capacitor output
can drive an LED
this is a Schmitt-trigger input with an internal pull-down resistor
mode)
input has an internal pull-up resistor
can drive an LED
has an internal pull-down resistor
internal pull-up resistor
2
S-bus
2
S-bus
2
S-bus
2
S-bus
internal pull-up resistor
; 1 = 256fs); this input has an internal pull-up resistor
s
DDD
QD03/QD53 : TDA1541A/S2
PINNING
SYMBOLPINDESCRIPTION
(1)
LE/WS
(1)
BCK
DATA L
(1)
/DATA
(1)
DATA R
GND(A)5analog ground
AOR6right channel output
DECOU7 to 13 decoupling
GND (D)14digital ground
V
DD2
COSC16,17 oscillator
DECOU18 to 24 decoupling
AOL25left channel output
V
DD1
(1)
OB/TWC
V
DD
Note
1. See Table 1 data selection input.
latch enable input/ word select
1
input
2bit clock input
data left channel input/ data
3
input (selected format)
4data right channel input
15−15 V supply voltage
26−5 V supply voltage
27mode select input
28+5 V supply voltage
: µ: µ
QF01
Q507/Q509 : DSP56004
49529
General
Serial
Purpose
Audio
Input/
Interface
Output
(SAI)
24-Bit
DSP56000
Core
Internal
Data
Bus
Switch
OnCETM Port
Clock
PLL
Gen.
;
43
IRQA, IRQB, NMI, RESET
Interrupt
Control
4
Address
Generation
Unit
Program
Decode
Controller
Program Control Unit
Power Inputs
V
CCP
3
V
CCQ
2
V
CCA
V
CCD
2
V
CCS
Ground
GND
P
GND
GND
GND
GND
3
Q
4
A
2
D
3
S
Serial
Host
Interface
(SHI)
GDB
PDB
XDB
YDB
External
Memory
Interface
(EMI)
Program
Address
Generator
DSP56004
Program
Memory*
PAB
XAB
YAB
24 × 24 + 56 → 56-bit MAC
*Refer to Table 1 for memory configurations.
Port B
Serial Host
Interface
Serial Audio
Interface
PCAP
PINIT
PLL
EXTAL
MA0ÐMA14
MD0ÐMD7
15
8
MA15/MCS3
MA16/MCS2/MCAS
MA17/MCS1/MRAS
MCS0
Port A
External Memory
Interface
MWR
MRD
MODC/NMI
MODB/IRQB
MODA/IRQA
RESET
Mode/Interrupt
Control
Reset
80 signals
OnCEª
16-Bit Bus
24-Bit Bus
X Data
Memory*
Data ALU
Two 56-Bit Accumulators
Port C
Rec0
Rec1
Tran0
Tran1
Tran2
4
GPIO
Port
Y Data
Memory*
MOSI/HA0
SS/HA2
MISO/SDA
SCK/SCL
HREQ
WSR
SCKR
SDI0
SDI1
WST
SCKT
SDO0
SDO1
SDO2
GPIO0ÐGPIO3
DSCK/OS1
DSI/OS0
DSO
DR
: µPD78076 MAIN
: µ: µ
Pin No. Port Name Function In/Out Active To/From Description
1STRBP120 Out HighQ304 Strobe signal for control resister for Q304(TDA1315H
2LMODP121 Out LowQ304 Interface mode line for Q304(TDA1315H
3OPENP122----4GNDP123GNDGND
5FS32P124In LowQ304 Samplin
6FS48P125In LowQ304 Sampling frequency input (L = 48KHz Receivin
7COAX/OPTP126 Out LowQ304 Digital input select signal (L = Optical , H = Coaxal
8DMUTP127 Out LowQ304 Digital muting control signal for Q304(TDA1315H
9GNDICGND GND
10 5MHzXTA
11 5MHzXTALX1XF01 Clock in (5MHz
12+5VVdd+5VPower supply +5V
13OPENXT2-------14+5VXT1+5VPower suppl
15REST RESET In LowQF02 Reset si
16RC5IINTP0 InZY01 Remote control si
17OPEN INTP1-------18CD7RP02Out LowQ102 CD7 Reset si
19SILDP03 Out LowQ102 Strobe signal for servo part of Q102(SAA7372GP
20RAB7P03Out LowQ102 Strobe signal for digital part of Q102(SAA7372GP
21LOCKINTP5 In LowQ304 Unlock signal of Q304(TDA1315H
22MSCPINTP6 In LowGND GND
23+5VAvdd+5VPower suppl
24+5VAvref0 In+5VPower suppl
25KEY0ANI0In Level Tact SwitchKe
26KEY1ANI1In Level Tact SwitchKe
27KEY2ANI2In Level Tact SwitchKe
28GNDANI3GND GND
29MUTEANI4 Out Hi
30PAUSANI5 Out HighQ507 Mute of pause on time for DSP Q507(DSP56004
31OPENANI6
32RELY2ANI7 Out Hi
33GNDAvssGND GND
34OPENP130 In/Out-------35OPENP131 Out-------36+5VAvrefIn+5VPower suppl
37STRDP70Out LowQY01 Strobe si
38SIODSO2 OutQY01 Serial data for QY01
39CLKDSCK2 Out LowQY01 Serial clock for QY01
40GNDVssGND GND
41OPENSI1In-------42OPENSO1-------43OPENSCK1-------44OPENP23
45OPENP24-------46OPENSB0----47OPENSB1 In/Out-------48SDASCK0 OutQ102/Q304 Serial data si
49SCLA0 Q102/Q304 Serial clock si
50OPENA1-------51OPENA2-------52OPENA3-------53OPENA4-------54OPENA5-------55OPENA6-------56OPENA7-------57GNDD0GND
58GNDD1GND
59GNDD2GND
60GNDD3GND
61GNDD4GND
62GNDD5GND
63GNDD6GND
64GNDD7GND
65OPENA8-------66OPENA9-------67OPENA10-------68OPENA11-------69OPENA12-------70OPENA13-------71GNDVssGND GND
72OPENA14
73RA11A15Out Hi
7416WDP60In LowGND Audio data select signal input (L = 16Bit
75FMUTP61Out HighQN05 Mute of switching on time killer
76RSD2P62Out Low Q309
77RSD1P63Out LowQ507 Reset of Q507
78NSSHRDOut Low Q508
79FIL3WROut High Q508,QY09Filter 3 select signal (H = select of filter 3
80FIL2P66Out High Q508,QY08Filter 2 select signal (H = select of filter 2
81FIL1P67Out HighQY07 Filter 1 select signal (H = select of filter 1
82OPTIP100In HighQ303 Optical input select ( H = OPT , L = COAX1
83OPENTO6-------84OPENP102-------85RELY1P103 Out Hi
86MSL1P30In HighHigh Level ----87MSL2P31In Low GND Level ----88OPENP32-------89CDRWP33Out Hi
90SLSWP34In Low VAM1201 Sled
91TROSP35In LowTRAY Tray in/out detect switch (L = out end
92TRISP36In LowTRAY Tray in/out detect switch (L = in end
93TRUSP37In LowTRAY Tray up/down detect switch (L = up end
94TRDSP90In LowTRAY Tray up/down detect switch (L = down end
95TROMP91Out High QM10 Tray motor control signal (H = tray out
96TRIMP93Out High QM09 Tray motor control signal (H = tray in
97TRDMP94Out High QM12 Tray motor control signal (H = tray down
98TRUMP95Out High QM11 Tray motor control signal (H = tray up
99AMUTP95Out LowNC-----
100DA/CDP96Out LowQ504 Mode select
X2XF01 Clock out (5MHz
hQ507 Mute signal for DSP Q507(DSP56004
CD7L)-----
hQY51 Display on/off control signal (L = off , H = on
---
---
RA12)-----
hQ506 Audio data select signal output (L = 16Bit
Q509 Reset of Q309,Q509
QY10Noise shaper on/off signal (L = on , H = off
hD301 Audio muting control signal of poer on/off(H=mute on
hNC-----
frequency input (L = 32KHz Receivin
+5V
nal input for QF02
nal input for ZY01
nal for Q102(SAA7372GP
+5V
+5V
Sensor
Sensor
Sensor
+5V
nal for QY01
-----
nal for Q102/Q304
nal for Q102/Q304
GND
GND
GND
GND
GND
GND
GND
GND
e detect switch (L = in end
L = D/A Mode , H = CD Mode
56
6. WIRING DIAGRAM
78
7. BLOCK DIAGRAM
g
g
g
g
)
)
)
g
(
(
(
(
(
g
(
(
g
g
(
(
(
(
)
(
(
(
(
(
(
(
(
(
(
(
(
(
(
g
g
y
g
g
(
g
(
(
(
Q103
Q104
Q102 SAA7372GP
Q304 TDA1315
8. FLAG No.
No. Flag NameFunction
0 MT-OUT Motor Drive Output
1 HF-OUT TDA1302T HF si
2
3 HF-HPF HF Si
4LDON Laser Diode Control Si
5
6RARadial Motor Control Si
7FOFocus Motor Control Signal(PDM
8SLSlegde Motor Control Signal(PDM
9
10DIGO Di
11CDR7 CD7
12SILDCD7
13RAB7 CD7
14SCDC CD7
15 WCDC CD7
16SIIOServo pcb and Main pcb comunicatein
17
18LRCK SM5844AF
19
20
21DADC CD7
22 36MHz Samplin
23 33MHz Samplin
24SDAFrom CPU
25SCLFrom CPU
26
27REST CPU
28RCDK Main pcb SIIO Latch pulse for
29 RCDG SERVO PCB SIIO Latch pulse for QF06
30
31
32
33
34
35OSCCPU
36OSCCPU
37
38
39
40
41LOCK TDA1315H
42EMPA TDA1315H
43DACD CD7
44
45
46
47
48DMUT from CPU
49
50FS32 TDA1315H
51FS44 TDA1315H
52FS48 TDA1315H
53SDTDA1315H
54WSTDA1315H
55SCKTDA1315H
56FRQ2 CD7
57 UNLOCK TDA1315H
58
59 COAX2 Di
60OPT0 Di
61
62
63
64
65
66OUT+ Correct phase AUDIO SIGNAL
67OUT- Inverse phase AUDIO SIGNAL
68
69 REMU Rela
70
71
72
73
74
75
76
77
78
79768FS Master clock selectin
80256FS Master clock divided output
81128FS Master clock divided output
824FS176.4KHz before Word select si
83 WSDA Word select for DSP
84FMUT Filter select switchin
85CLDA DSP
86BCEN DSP
87BCDA for DAC
88
89
90
91
92
93
94
95
96
97
98
99
nal HPF Output
ital Audio Output Signal
SAA7372) Reset Pulse
SAA7372) Servo Parte enable Signal
SAA7372) Decorde and DSP parte enable signal
SAA7372) data clock out signal
SAA7372) data word clock out signal
SAA7372) data out(16bit) signal
QF01) Power on reset
QF01) self clock
QF01) self clock
SAA7372) data out signal
SAA7372) Operating clock out signal
tal I/O input COAX2 signal
tal I/O input OPTICAL signal
mute by POWER ON/OFF and selecting FILTER mode
Q509) data clock signal
Q509) data clock enable signal for DAC
nal output
nal
nal(PDM
Q309) word clock signal
frequency 48KHz/32KHz Master clock
frequency 44KHz Master clock
QF01) TO TDA1315H(Q304) data signal
QF01) TO TDA1315H(Q304) clock signal
Q501,Q502,Q503
Q304) unlock delayed output signal
Q304) Deemphasis output signal
QF01) to TDA1315H(Q304) muting signal
Q304) 32k Sampling detected signal
Q304) 44.1k Sampling detected signal
Q304) 48k Sampling detected signal
Q304) data output signal
Q304) Word select output signal
Q304) data clock output signal
Q304) unlock output signal
output
Q509) and DAC(QD03,QD53) 176.4KHz
on time unenable for DAC
QD03,QD53) data clock 5.6448MHz
nal
signal
910
9. SCHEMATIC DIAGRAM AND PARTS LOCATION
1112
1314
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