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Datasheet TLE 6236 G
Smart Octal Low-Side Switch
Features Product Summary
• Short Circuit Protection
• Overtemperature Protection
• Overvoltage Protection
• 8 bit Serial Data Input and Diagnostic
Output (acc. SPI protocol)
• Direct Parallel Control of Four Channels for PWM Applications
Supply voltage V
Drain source clamping voltage V
On resistance R
Output current (all outp.ON equal) I
(individually) 500 mA
• General Fault Flag
• Daisy chainable with other SPI devices
• Very Low Leakage Current (≤ 1µA)
• Compatible with 3V Micro Controllers
• Electostatic Discharge (ESD) Protection
Application
• µC Compatible Power Switch for 12V and 24VApplications
• Switch for Automotive and Industrial System
• Solenoids, Relays, Resistive Loads, LEDs
• Robotic Controls
General description
Octal Low-Side Switch in Smart Power Technology (SPT) with a Serial
Peripheral Interface (SPI) and eight open drain DMOS output stages. The TLE 6236 G is protected by
embedded protection functions and designed for automotive and industrial applications. The output
stages are controlled via an SPI Interface. Additionally four channels can be controlled direct in parallel
for PWM applications. The open load detection (pull down sources) can be disabled via the OL/PRG
pin. Then the leakage current is reduced to 1µA (max.) to avoid e.g. the glowing of LEDs in off state.
Therefore the TLE 6236 G is particularly suitable for body control units, dash board illumination or engine management systems.
4.5 – 5.5 V
S
DS(AZ)max
ON
D(NOM)
P-DSO 28
Ordering Code:
Q67007-A9413-A705
60 V
1.7 Ω
200 mA
Block Diagram
OL/PRG
GND
IN1
IN2
IN3
IN4
SCLK
SI
CS
SO
as Ch. 1
as Ch. 1
as Ch. 1
Serial Interface
RESET FAULT
VS
LOGIC
8
8
SPI
1
4
Output Control
Buffer
GND
Protection
Functions
Output Stage
8
OL/PRG
V
BB
OUT1
OUT8
V2.1 Page 26.Aug. 2002
1
Datasheet TLE 6236 G
Detailed Block Diagram
IN1
GND
OL/PRG
≥1
FAULTRESET
VS
Channel 1
Open load/SCG
SCB/Overload
Output Stage
OUT1
IN2
IN3
IN4
SO
SI
SCLK
CS
SPI
Interface
16 bit
≥1
≥1
≥1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Channel 8
GND
OL/PRG
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
V2.1 Page 26.Aug. 2002
2
Pin Description
Pin Configuration (Top view)
Pin Symbol Function
1 GND Ground
2 NC not connected
3 OUT1 Power Output Channel 1
4 OUT2 Power Output Channel 2
5 IN1 Input Channel 1
6 IN2 Input Channel 2
7 VS Supply Voltage
8 OL/PRG Open load actice/inactive Program Pin
9 IN3 Input Channel 3
10 IN4 Input Channel 4
11 OUT3 Power Output Channel 3
12 OUT4 Power Output Channel 4
13 NC not connected
14 GND Ground
15 GND Ground
16 NC not connected
17 OUT5 Power Output Channel 5
18 OUT6 Power Output Channel 6
19
20
CS
FAULT
Chip Select
General Fault Flag
21 SO Serial Data Output
22 SCLK Serial Clock
23 SI Serial Data Input
24
RESET
Reset
25 OUT7 Power Output Channel 7
26 OUT8 Power Output Channel 8
27 NC not connected
28 GND Ground
Datasheet TLE 6236 G
GND 1• 28 GND
NC 2 27 NC
OUT1 3 26 OUT8
OUT2 4 25 OUT7
IN1 5 24
IN2 6 23 SI
VS 7 22 SCLK
OL/PRG
821SO
IN3 9 20
IN4 10 19
OUT3 11 18 OUT6
OUT4 12 17 OUT5
NC 13 16 NC
GND 14 15 GND
P-DSO 28
RESET
FAULT
CS
V2.1 Page 26.Aug. 2002
3
Datasheet TLE 6236 G
Maximum Ratings for Tj = – 40°C to 150°C
Parameter Symbol Values Unit
Supply Voltage V
Continuous Drain Source Voltage (OUT1...OUT8) V
Input Voltage, All Inputs and Data Lines V
Operating Temperature Range
Storage Temperature Range
Output Current per Channel (see el. characteristics) I
Output Current per Channel @ TA = 25°C
1
(All 8 Channels ON; Mounted on PCB )
)
Output Clamping Energy
I
= 0.25 A
D
Power Dissipation (mounted on PCB) @ TA = 25°C P
Electrostatic Discharge Voltage (Human Body Model)
S
DS
IN
T
j
T
stg
D(lim)
I
D
E
V
AS
tot
ESD
according to MIL STD 883D, method 3015.7 and EOS/ESD
assn. standard S5.1 - 1993
DIN Humidity Category, DIN 40 040 E
IEC Climatic Category, DIN IEC 68-1 40/150/56
Thermal Resistance
junction - pin
junction - ambient @ min. footprint
R
thJP
R
thJA
-0.3 ... +7 V
45 V
- 0.3 ... + 7 V
- 40 ... + 150
°C
- 55 ... + 150
I
D(lim) min
A
250 mA
10 mJ
2W
2000 V
25
K/W
80
1
)
Output current rating so long as maximum junction temperature is not exceeded. At T
rent has to be calculated using R
V2.1 Page 26.Aug. 2002
according mounting conditions.
thJA
4
= 125 °C the output cur-
A
Datasheet TLE 6236 G
Electrical Characteristics
Parameter and Conditions Symbol Values Unit
VS = 4.5 to 5.5 V ; Tj = - 40 °C to + 150 °C ; Reset = H
(unless otherwise specified)
1. Power Supply
min typ max
Supply Voltage
Supply Current I
Supply Current (in Standby Mode, RESET = L)
1)
2. Power Outputs
ON Resistance VS = 5 V; ID = 500 mA TJ = 25°C
T
= 150°C
J
Output Clamping Voltage Output OFF V
Current Limit I
Output Leakage Current V
Reset
= L
2)
Turn-On Time ID = 0.25 A, resistive load t
Turn-Off Time ID = 0.25 A, resistive load t
3. Digital Inputs
Input Low Voltage V
Input High Voltage V
Input Voltage Hysteresis V
Input Pull Down Current (IN1 ... IN4) I
OL/PRG, Reset Pull Up Current I
Input Pull Down Current (SI, SCLK) I
Input Pull Up Current ( CS ) I
V
S
S
I
S(Stdby)
R
DS(ON)
DS(AZ)
D(lim)
I
D(lkg)
ON
OFF
INL
INH
INHys
IN(1..4)
IN(OL/PRG,Res)
IN(SI,SCLK)
IN(CS)
4.5 -- 5.5
V
-- 1.5 3 mA
-- 50 µA
--
--
1.7
3
--
Ω
4
45 -- 60 V
500 750 1000 mA
-- -- 1 µA
-- 6 10 µs
-- 6 10 µs
- 0.3 -- 1.0 V
2.0 -- -- V
100 200 -- mV
20 50 100 µA
20 50 100 µA
10 20 50 µA
10 20 50 µA
4. Digital Outputs (SO,
FAULT
SO High State Output Voltage I
SO Low State Output Voltage I
)
= 2 mA V
SOH
= 2 mA V
SOL
SO Output Tri-state Leakage Current CS=H, 0 ≤ VSO ≤ VSI
FAULT Output Low Voltage I
= 1.6 mA V
FAULT
5. Diagnostic Functions
Open Load Detection Voltage V
Output Pull Down Current I
Fault Delay Time t
Overload Threshold Current I
Overtemperature Shutdown Threshold
Hysteresis
1
Test conditions : No floating digital Inputs
2
Measured on wafer level
SOH
SOL
SOlkg
FAULTL
DS(OL)
PD(OL)
d(fault)
D(lim) 1...8
T
th(sd)
T
hys
VS –
-- -- V
0.5V
-- -- 0.4 V
-10 0 10 µA
-- -- 0.4 V
0.6*VS0.7*VS0.8*V
V
S
200 300 450 µA
50 100 200 µs
500 700 1000 mA
170
--
-10
200
--
°C
K
V2.1 Page 26.Aug. 2002
5
Datasheet TLE 6236 G
Electrical Characteristics cont.
Parameter and Conditions Symbol Values Unit
VS = 4.5 to 5.5 V ; Tj = - 40 °C to + 150 °C ; Reset = H
(unless otherwise specified)
6. SPI-Timing
Serial Clock Frequency
Serial Clock Period (1/fclk) t
Serial Clock High Time t
Serial Clock Low Time t
Enable Lead Time (falling edge of CS to rising edge of
CLK)
Enable Lag Time (falling edge of CLK to rising edge ofCS) t
Data Setup Time (required time SI to falling of CLK) t
Data Hold Time (falling edge of CLK to SI) t
Enable Time t
Disable Time t
Data Valid Time CL = 50 pF
CL = 100 pF
CL = 220 pF
1
1
1
f
SCK
p(SCK)
SCKH
SCKL
t
lead
lag
SU
H
EN
DIS
t
valid
min typ max
DC -- 5 MHz
200 -- -- ns
80 -- -- ns
80 -- -- ns
250 -- -- ns
250 --- -- ns
-- 25 -- ns
-- 25 -- ns
250 -- -- ns
250 -- -- ns
--
--
--
110
120
150
160
170
200
ns
1
This parameter will not be tested but guaranteed by design
V2.1 Page 26.Aug. 2002
6
Datasheet TLE 6236 G
Functional Description
The TLE 6236 G is an octal-low-side power switch which provides a serial peripheral interface
(SPI) to control the 8 power DMOS switches, as well as diagnostic feedback. The power transistors are protected against short to VBB, overload, overtemperature and against overvoltage
by an active zener clamp.
The diagnostic logic recognizes a fault condition which can be read out via the serial diagnostic output (SO).
Circuit Description
Output Stage Control
Each output is independently controlled by an output latch and a common reset line, which
disables all eight outputs. Serial data input (SI) is read on the falling edge of the serial clock. A
logic high input data bit turns the respective output channel ON, a logic low data bit turns it
OFF. CS must be low whilst shifting all the serial data into the device. A low-to-high transition
of CS transfers the serial data input bits to the output buffer.
Special conditions for Channel 1 to 4:
In addition to the serial control of the outputs it is possible to control channel 1 to channel 4
directly in parallel for PWM applications. These inputs are high active and ORed with the SPI
control bit. The parallel inputs are provided with internal pull down sources, to guarantee that
the channels are switched off when the inputs are not connected.
The table shows the OR-operation of the parallel inputs 1 ..4 and the corresponding SPI bits.
IN 1 - 4 SPI-Bit 0 - 3 OUT 1 - 4
00OFF
01ON
10ON
11ON
The outputs 5 .. 8 can be controlled in serial via SPI
Interface
Serial Control Bits (SI)
Ch. 8 Ch. 7 Ch. 6 Ch. 5 Ch. 4 Ch. 3 Ch. 2 Ch. 1
76543210
MSB LSB
SPI-Bit 4 - 7 OUT 5 - 8
0OFF
1ON
Serial Diagnostic Bits (SO)
DIAG7 DIAG6 DIAG5 DIAG4 DIAG3 DIAG2 DIAG1 DIAG0
76543210
MSB LSB
V2.1 Page 26.Aug. 2002
7
Datasheet TLE 6236 G
Power Transistor Protection Functions
1)
Each of the eight output stages has its own zener clamp, which causes a voltage limitation at
the power transistor when solenoid loads are switched off. The outputs are provided with a
current limitation set to a minimum of 500 mA. The continuous current for each channel is
200 mA (all channels ON).
Each output is protected by embedded protection functions. In the event of an overload or
short to supply, the current is internally limited and a fault bit is generated for each output individually (early warning). If this operation leads to an overtemperature condition, a second
protection level (about 170 °C) will change the output into a low duty cycle PWM (channel selective thermal shutdown with restart) to prevent critical chip temperatures.
SPI Signal Description
CS - Chip Select. The system microcontroller selects the TLE 6236 G by means of the CS
pin. Whenever the pin is in a logic low state, data can be transferred from the µC and vice
versa.
CS High to Low transition: - diagnostic status information is transferred from the
power
outputs into the shift register.
- serial input data can be clocked in from then on
- SO changes from high impedance state to logic high or low
state corresponding to the SO bits
CS Low to High transition: - transfer of SI bits from shift register into output buffers
- reset of diagnosis register
To avoid any false clocking the serial clock input pin SCLK should be logic low state during
high to low transition of
CS . When CS is in a logic high state, any signals at the SCLK and SI
pins are ignored and SO is forced into a high impedance state.
The device will react to the CS only if one correct SCLK signal has been sent.
SCLK - Serial Clock. The system clock pin clocks the internal shift register of the TLE 6236 G.
The serial input (SI) accepts data into the input shift register on the falling edge of SCLK while
the serial output (SO) shifts diagnostic information out of the shift register on the rising edge of
serial clock. It is essential that the SCLK pin is in a logic low state whenever chip select
CS
makes any transition.
SI - Serial Input. Serial data bits are shifted in at this pin, the most significant bit first. SI information is read in on the falling edge of SCLK. Input data is latched in the shift register and
then transferred to the control buffer of the output stages.
A logic high bit at this pin (within the data byte) will switch the corresponding output on.
1)
The integrated protection functions prevent an IC destruction under fault conditions and may not be used in normal operation or perma-
nently
V2.1 Page 26.Aug. 2002
8
Datasheet TLE 6236 G
SO - Serial Output. Diagnostic data bits are shifted out serially at this pin, the most significant
bit first. SO is in a high impedance state until the CS pin goes to a logic low state. New diagnostic data will appear at the SO pin following the rising edge of SCLK.
RESET - Reset pin. If the reset pin is in a logic low state, it clears the SPI shift register and
switches all outputs OFF. An internal pull-up structure is provided on chip.
Diagnostics
FAULT - Fault pin. There is a general fault pin (open drain) which shows a high to low transi-
tion as soon as an error occurs for any one of the eight channels. This fault indication can be
used to generate a µC interrupt. Therefore a ‘diagnosis’ interrupt routine need only be called
after this fault indication. This saves processor time compared to a cyclic reading of the SO
information.
As soon as a fault occurs, the fault information is latched into the diagnosis register. Serial
data out pin (SO) is in a high impedance state when CS is high. If CS receives a LOW signal,
all diagnosis bits can be shifted out serially. The rising edge of CS will reset all error registers.
Logic table
Parallel
Input
SI Bits
0-7
SO DIAG-
Bits 0-7
Output State
Output voltage
V
OUT
Operating Mode
1 L L L OFF >Vref normal function
2 L H H ON < Vref normal function
3 H L L ON < Vref normal function
4 H H H ON < Vref normal function
5 L L H OFF < Vref open load/short to gnd
6 L H L ON >Vref overload
7 H L H ON >Vref overload
8 H H L ON >Vref overload
Table 1: Definition of diagnostic bits under parallel and serial control
Basic principle of fault detection:
SO Bit = SI Bit: Normal Function
SO Bit inverse to SI Bit : Fault Condition
The diagnostic bits DIAG0 to DIAG3 for channel 1 to 4 indicate a fault when the DIAG bit is
high during parallel control (IN1 .. IN4 = H; serial data bits 0 .. 3 = L). Note that the SPI serial
input (SI) bit overrides the ON state control from IN1 to IN4 regarding diagnostic information.
Compare DIAG Bit in line 3 (parallel ON only) with DIAG Bit in line 4 (serial and parallel ON)
under normal function.
Compare DIAG Bit in line 7 (parallel ON only) with DIAG Bit in line 8 (serial and parallel ON)
under fault condition.
V2.1 Page 26.Aug. 2002
9
Datasheet TLE 6236 G
SPI serial input (SI) bit overrides the parallel ON state control from IN1 to IN4
Vref is the threshold reference level for detecting an Open Load/Overload
The standard way of obtaining diagnostic information is as follows:
Clock in serial information into SI pin and wait approximately 200 µs to allow the outputs to
settle. Clock in the identical serial information once again - during this process the data coming out at SO contains the bit combinations representing the diagnosis conditions as described
in figure 1.
Based on the needs of the application, a software routine should be programmed into the micro controller to set the corrective action of each fault condition.
Open Load Program Pin (OL/PRG)
To detect open load/short to ground each channel has an internal pull down source (300 µA
typ.) which pulls the drain voltage under the detection threshold in case of an open load or
short to ground condition.
If the TLE 6236 G is used to drive LEDs this pull down current could causes a slight glowing of
the LED. To avoid this, the device is provided with a program pin, which enables or disables
this open load detection. The OL/PRG pin is internally pulled up, i.e. the open load detection is
enabled if the OL/PRG pin is not connected. To disable the open load detection this pin must
be pulled to GND, e.g with a micro controller port.
In this way the open load detection can be enabled (e.g during start up of the system or in a
diagnosis routine) and disabled (e.g. during normal operation to avoid LED glowing) by the µC.
If the open load detection is disabled, the leakage current is reduced to a maximum of 1µA.
OL/PRG
OL
300µ
V
ref
V
Bat
OL
VDS ≈ 3.5V OL
V2.1 Page 26.Aug. 2002
10
CS
SCLK
Datasheet TLE 6236 G
Timing Diagrams
SI
7 6 5 4 3 2 1 0
MSB
SO
7 6 5 4 3 2 1 0
Outputs
Figure 2: Serial Interface
CS
0.2 V
S
t
SCKH
t
lead
SCLK
t
SU
SI
0.7V
t
S
SCKL
LSB
OLD NEW
t
H
0.7V
S
0.2V
S
t
lag
0.2V
S
Figure 3: Input Timing Diagram
0.7 V
SCLK
SO
t
valid
0.2 V
S
0.7 V
S
S
CS
SO
0.2 V
S
t
EN
t
Dis
SO
0.7 V
S
0.2 V
S
Figure 4:
SO Valid Time Waveforms Enable and Disable Time Waveforms
V2.1 Page 26.Aug. 2002
11
Application Circuits
t
t
V
IN
Datasheet TLE 6236 G
t
V
DS
ON
80%
20%
Figure 5: Power Outputs
VS = 5V
µC
e.g. C167
MTSR
MRST
CLK
P xy
10k
OL/PRG
FAULT
RESET
IN1
IN2
IN3
IN4
SI
SO
CLK
CS
t
VS
OUT1
OUT2
TLE
6236 G
OUT8
GND
OFF
V
BB
V2.1 Page 26.Aug. 2002
12
Typical electrical Characteristics
]
Drain-Source on-resistance
R
= f (Tj) ; Vs = 5V
DS(ON)
Datasheet TLE 6236 G
Typical Drain- Source ON-Resistance
Channel 1,4,5,8
Channel 2,3,5,6
3,2
3
2,8
2,6
2,4
2,2
2
1,8
RDS(ON) [Ohm
1,6
1,4
1,2
1
-50 -25 0 25 50 75 100 125 150 175
Tj[°C]
Figure 6 : Typical ON Resistance versus Junction-Temperature
Channel 1-8
Output Clamping Voltage
V
= f (Tj) ; Vs = 5V
DS(AZ)
Typical Clamping Voltage
45
44
43
VDS(AZ) [ V]
42
41
-50 -25 0 25 50 75 100 125 150 175
Channel 1-8
Tj[°C]
Figure 7 : Typical Clamp Voltage versus Junction-Temperature
Channel 1-8
V2.1 Page 26.Aug. 2002
13
Datasheet TLE 6236 G
Parallel SPI Configuration
Engine Management Application
TLE 6236 G in combination with TLE 6240 GP (16-fold switch) for relays and general purpose loads
and TLE 6220 GP (quad switch) to drive the injector valves. This arrangement covers the numerous
loads to be driven in a modern Engine Management/Powertrain system. From 28 channels in sum 16
can be controlled direct in parallel for PWM applications.
Injector 1
P x.1-4
4
4 PWM
Channels
Injector 2
µC
C167
MTSR
MRST
CLK
P x.y
P x.1-4
P x.y
P x.1-8
P x.y
SI
SO
CLK
CS
CS
4
4 PWM
Channels
SI
SO
CLK
TLE
6220 GP
Quad
TLE
6236 G
Injector 3
Injector 4
Octal
CS
8
8 PWM
Channels
SI
SO
CLK
CS
TLE
6240 GP
16-fold
V2.1 Page 26.Aug. 2002
14
Package and Ordering Code
(all dimensions in mm)
P-DSO 28 Ordering Code
TLE 6236 G Q67007-A9413-A705
Datasheet TLE 6236 G
Published by
Infineon Technologies AG,
Bereichs Kommunikation
St.-Martin-Strasse 76,
D-81541 München
© Infineon Technologies AG 1999
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits,
descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question
please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of
Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support
device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it
is reasonable to assume that the health of the user or other persons may be endangered.
V2.1 Page 26.Aug. 2002
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