0.4Sep. 27. 201225-27Update the EDID (Color coordinates)0.2
6Change the LED Power Input Voltage (7V ˧ 6V)
19Update the LCM Drawing
6
19Add the Location of Pin 1
25-27Update the EDID (Product Code : 0363˧03B6)
Change
Life Time (12,000˧15,000)
EDID
ver
0.0
0.1
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1. General Description
The LP140WHU is a Color Active Matrix Liquid Crystal Display with an integral LED backlight system. The
matrix employs a-Si Thin Film Transistor as the active element. It is a transmissive type display operating in
the normally white mode. This TFT-LCD has 14.0 inches diagonally measured active display area with HD
resolution (1366 horizontal by 768 vertical pixel array). Each pixel is divided into Red, Green and Blue subpixels or dots which are arranged in vertical stripes. Gray scale or the brightness of the sub-pixel color is
determined with a 6-bit gray scale signal for each dot, thus, presenting a palette of more than 262,144
colors. The LP140WHU has been designed to apply the interface method that enables low power, high
speed, low EMI. The LP140WHU is intended to support applications where thin thickness, low power are
critical factors and graphic displays are important. In combination with the vertical arrangement of the subpixels, the LP140WHU characteristics provide an excellent flat display for office automation products such
as Notebook PC.
The LP140WHU requires two power inputs. The first logic is employed to power the LCD electronics and to
drive the TFT array and liquid crystal. The second backlight is the input about LED BL with LED Driver.
Table 2. ELECTRICAL CHARACTERISTICS
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LP140WHU
Liquid Crystal Display
Product Specification
ParameterSymbol
UnitNotes
MinTypMax
LOGIC :
Values
Power Supply Input VoltageV
Power Supply Input CurrentMosaicI
Power ConsumptionP
Power Supply Inrush CurrentI
LVDS ImpedanceZ
CC3.03.33.6V1
CC-TBDTBDmA2
CC-TBDTBDW2
CC_P--1500mA3
LVDS90100110
ȳ
BACKLIGHT : ( with LED Driver)
LED Power Input VoltageV
LED Power Input CurrentI
LED Power ConsumptionP
LED Power Inrush CurrentI
LED6.012.021.0V5
LED-TBDTBDmA6
LED-TBDTBDW6
LED_P--2000mA7
PWM Duty Ratio5-100%8
PWM Jitter
PWM ImpedanceZ
-
PWM204060kȳ
0-0.2%9
4
PWM FrequencyF
PWM High Level VoltageV
PWM Low Level VoltageV
LED_EN ImpedanceZ
LED_EN High VoltageV
LED_EN Low VoltageV
PWM200-1000Hz10
PWM_H
PWM_L
PWM204060kȳ
LED_EN_H3.0-3.6V
LED_EN_L0-0.3V
3.0-3.6V
0-0.3V
Life Time15,000--Hrs11
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Note)
1. The measuring position is the connector of LCM and the test conditions are under 25, fv = 60Hz,
Black pattern.
2. The specified Icc current and power consumption are under
the Vcc = 3.3V , 25, fv = 60Hz condition and Mosaic pattern.
3. This Spec. is the max load condition for the cable impedance designing.
4. The below figures are the measuring Vcc condition and the Vcc control block LGD used.
The Vcc condition is same as the minimum of T1 at Power on sequence.
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LP140WHU
Liquid Crystal Display
Product Specification
Rising time
Vcc
0V
5. This impedance value is needed for proper display and measured form LVDS Tx to the mating connector.
6. The measuring position is the connector of LCM and the test conditions are under 25.
7. The current and power consumption with LED Driver are under the Vled = 12.0V , 25, Dimming of
Max luminance and White pattern with the normal frame frequency operated(60Hz).
8. The below figures are the measuring Vled condition
and the Vled control block LGD used.
VLED control block is same with Vcc control block.
90%
10%
0.5ms
3.3V
Rising time
LED
V
0V
10%
12.0V
90%
0.5ms
9. The operation of LED Driver below minimum dimming ratio may cause flickering or reliability issue.
10. If Jitter of PWM is bigger than maximum, it may induce flickering.
11. This Spec. is not effective at 100% dimming ratio as an exception because it has DC level equivalent
to 0Hz. In spite of acceptable range as defined, the PWM Frequency should be fixed and stable for
more consistent brightness control at any specific level desired.
12. The life time is determined as the time at which brightness of LCD is 50% compare to that of minimum
value specified in table 7. under general user condition.
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3-2. Interface Connections
This LCD employs two interface connections, a 40 pin connector used for the module electronics interface and
the other connector used for the integral backlight system.
Table 3. MODULE CONNECTOR PIN CONFIGURATION (CN1)
PinSymbolDescriptionNotes
1NCNo Connection
2VCCLCD Logic and driver power (3.3V Typ.)
3VCCLCD Logic and driver power (3.3V Typ.)
4V EEDIDDDC Power (3.3V)
5NCNo Connection
6Clk EEDIDDDC Clock
7DATA EEDIDDDC Data
8ORX0-Negative LVDS differential data input
9ORX0+Positive LVDS differential data input
10GNDHigh Speed Ground
11ORX1-Negative LVDS differential data input
12ORX1+Positive LVDS differential data input
13GNDHigh Speed Ground
14ORX2-Negative LVDS differential data input
15ORX2+Positive LVDS differential data input
16GNDHigh Speed Ground
17ORXC-Negative LVDS differential clock input
18ORXC+Positive LVDS differential clock input
19GNDHigh Speed Ground
20
21
22GNDHigh Speed Ground
23
24
25GNDHigh Speed Ground
26
27
28GNDHigh Speed Ground
29
30
31
32
33
34
35
36
37
38
39
40
NC
NC
NC
NC
NC
NC
NC
NC
GNDLED Backlight Ground
GNDLED Backlight Ground
GNDLED Backlight Ground
NC
PWMSystem PWM Signal input for dimming
LED_EN
NC
VLEDLED Backlight Power (6V-21V)
VLEDLED Backlight Power (6V-21V)
VLEDLED Backlight Power (6V-21V)
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
LED Backlight On/Off
No Connection
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Product Specification
Liquid Crystal Display
[Interface Chip]
1. LCD :
TLI, TL2356EP(LCD Controller)
Including LVDS Receiver.
2. System : TLI LVDSRx or equivalent
* Pin to Pin compatible with LVDS
[Connector]
Hirose KN38-40S-0.5H
[Connector pin arrangement]
40
[LCD Module Rear View]
LP140WHU
1
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3-3. LVDS Signal Timing Specifications
3-3-1. DC Specification
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LP140WHU
Liquid Crystal Display
Product Specification
VDD=1.8V
DescriptionSymbolMinTypMaxUnitNotes
LVDS Differential Voltage|V
LVDS Common mode VoltageV
LVDS Input Voltage RangeV
3-3-2. AC Specification
DescriptionSymbolMinMaxUnitNotes
LVDS Clock to Data Skew Margin
|100-600mV-
ID
CM
IN
|VID| /21.2VDD- |VID|/2V-
0.3-VDDV-
t
SKEW
t
SKEW
- 400+ 400ps
- 600+ 600ps
85MHz > Fclk ˻
65MHz
65MHz > Fclk ˻
25MHz
LVDS Clock to Clock Skew Margin (Even
to Odd)
Maximum deviation
of input clock frequency during SSC
Maximum modulation frequency
of input clock during SSC
Ver. 0.4Sep 27, 2012
t
SKEW_EO
F
DEV
F
MOD
-1/7+ 1/7T
clk
-· 3%-
-200KHz-
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