LG Display LP140WD2-TLB1 Specification
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LP140WD2
Liquid Crystal Display
Product Specification
SPECIFICATION
FOR
APPROVAL
()Preliminary Specification
ଝ
()Final Specification
Title 14.0”W HD+ TFT LCD
Customer LENOVO
MODEL
/
/
SUPPLIER LG Display Co., Ltd.
*MODEL LP140WD2
Suffix TLB1
*When you obtain standard approval,
please use the above model name without suffix
APPROVED BY
SIGNATUREAPPROVED BY
APPROVED BY
S. R. Kim / S.Manager
REVIEWED BY
REVIEWED BY
J. S. Park / Manager
SIGNATURE
SIGNATURE
/
Please return 1 copy for your confirmation with
your signature and comments.
Ver. 1.0 Dec. 16. 2010
PREPARED BY
PREPARED BY
C. W. Lee/ Engineer
D. J. Lee/ Engineer
Products Engineering Dept.
LG Display Co., Ltd
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LP140WD2
Liquid Crystal Display
Product Specification
Contents
No ITEM
COVER
CONTENTS
RECORD OF REVISIONS
1 GENERAL DESCRIPTION
2 ABSOLUTE MAXIMUM RATINGS
3 ELECTRICAL SPECIFICATIONS
3-1 ELECTRICAL CHARACTREISTICS
3-2 INTERFACE CONNECTIONS
3-3 LVDS SIGNAL TIMING SPECIFICATIONS
3-4 SIGNAL TIMING SPECIFICATIONS
3-5 SIGNAL TIMING WAVEFORMS
3-6 COLOR INPUT DATA REFERNECE
3-7 POW ER SEQUENCE
4 OPTICAL SFECIFICATIONS
Page
1
2
3
4
5
6-7
8
9-10
11
11
12
13
14-16
5 MECHANICAL CHARACTERISTICS
6 RELIABLITY
7 INTERNATIONAL STANDARDS
7-1 SAFETY
7-2 EMC
8 PACKING
8-1 DESIGNATION OF LOT MARK
8-2 PACKING FORM
8-3 LABEL DESCRIPTION
9 PRECAUTIONS
A APPENDIX A. Enhanced Extended Display Identification Data
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LP140WD2
Liquid Crystal Display
Product Specification
RECORD OF REVISIONS
Revision No Revision Date Page Description
0.0 Oct. 18, 2010 All First Draft (Preliminary Specification) 0.1
0.1 Oct. 21, 2010 13 Update Power Sequence
14 Update Color Coordinates
26-28 Update EDID 0.3
0.2 Dec. 10. 2010 4 Update General Description 0.3
6 Update Electrical Specifications
11 Update TIMING TABLE
14 Update Optical Specification
15 Update Gray scale specification
0.3 Dec. 16. 2010 6 Update Electrical Specifications 0.3
EDID
ver
Ver. 1.0 Dec. 16. 2010
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1. General Description
The LP40WD2 is a Color Active Matrix Liquid Crystal Display with an integral LED backlight system. The
matrix employs a-Si Thin Film Transistor as the active element. It is a transmissive type display operating in
the normally white mode. This TFT-LCD has 14.0 inches diagonally measured active display area with HD+
resolution (1600 horizontal by 900 vertical pixel array). Each pixel is divided into Red, Green and Blue subpixels or dots which are arranged in vertical stripes. Gray scale or the brightness of the sub-pixel color is
determined with a 6-bit gray scale signal for each dot, thus, presenting a palette of more than 262,144
colors. The LP140WD2 has been designed to apply the interface method that enables low power, high
speed, low EMI. The LP140WD2 is intended to support applications where thin thickness, low power are
critical factors and graphic displays are important. In combination with the vertical arrangement of the subpixels, the LP140WD2 characteristics provide an excellent flat display for office automation products such
as Notebook PC.
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LP140WD2
Liquid Crystal Display
Product Specification
EEPROM Block
for EDID
EEPROM Block
User connector
for Tc on Operating
1
1600
TFT-LCD Panel
40
Pin
LVDS
2port
VCC
VLED
LED_EN
PWM
Timing Control
(Tcon) Block
DVCC
Power
Block
LED Driver
Block
TCLKs
VGH, VGL, GMA
Control & Data Power
900
AVCC, AVDD
GSP, GSC, GOE
VOUT_LED
FB1~4
(HD+, TN)
Source Driver
(Bottom Bent)
LED Backlight Ass’y
EDID signal & Power
General Features
Active Screen Size 14.0 inches diagonal
Outline Dimension
Pixel Pitch
Pixel Format 1600 horiz. By 900 vert. Pixels RGB strip arrangement
Color Depth 6-bit, 262,144 colors
Luminance, W hite 250 cd/m
Power Consumption Total 4.81 Watt (Typ.) @ Logic input 0.91Watt (Typ.), B/L input 3.9 Watt (Typ.)
Weight 320g (Max.)
Display Operating Mode Transmissive mode, normally white
Surface Treatment Anti-glare treatment of the front polarizer(3H)
RoHS Comply Yes
322.3(H, typ) ϧ 187.1(V, typ) Ý 3.6(D,max) [mm]
0.1932mm Ý 0.1932 mm
2
(Typ.5 point)
ڌ
ڔڋڋ
ڞۃۄۋٻڪۉٻڢڼۏۀ
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2. Absolute Maximum Ratings
The following are maximum values which, if exceeded, may cause faulty operation or damage to the unit.
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LP140WD2
Liquid Crystal Display
Product Specification
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter Symbol
Power Input Voltage
Operating Temperature
Storage Temperature
Operating Ambient Humidity
Storage Humidity
VCC -0.3 4.0 Vdc
TOP 050
HST -20 60
HOP 10 90 %RH 1
HST 10 90 %RH 1
Values
Units Notes
Min Max
°C
°C
Note : 1. Temperature and relative humidity range are shown in the figure below.
Wet bulb temperature should be 39
Wet Bulb
Temperature [
10
0
20
]
30
°C Max, and no condensation of water.
90% 80%
60
50
40
60%
Humidity[(%)RH]
40%
20%
10%
Storage
Operation
at 25 ± 5°C
1
1
-20
10
20 30 40 50
60 70 800
Dry Bulb Temperature []
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3. Electrical Specifications
3-1. Electrical Characteristics
The LP140WD2 requires two power inputs. The first logic is employed to power the LCD electronics and to
drive the TFT array and liquid crystal. The second backlight is the input about LED BL with LED Driver.
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LP140WD2
Liquid Crystal Display
Product Specification
Table 2. ELECTRICAL CHARACTERISTICS
Parameter Symbol
Unit Notes
Min Typ Max
LOGIC :
Values
Power Supply Input Voltage V
Mosaic I
CC 3.0 3.3 3.6 V 1
CC - 275 317 mA 2
Power Supply Input Current
Black I
Power Consumption P
Power Supply Inrush Current I
LVDS Impedance Z
CC_max - 365 420 mA 3
CC - 0.91 1.1 W 2
CC_P - - 2000 mA 4
LVDS 90 100 110 Ω 5
BACKLIGHT : ( with LED Driver)
LED Power Input Voltage V
LED Power Input Current I
LED Power Consumption P
LED Power Inrush Current I
LED 7.0 12.0 21.0 V 6
LED - 325 350 mA 7
LED -3.94.2W7
LED_P - - 2000 mA 8
PWM Duty Ratio 1 - 100 % 9
PWM Jitter
-
0 - 0.2 % 10
PWM Impedance Z
PWM Frequency F
PWM High Level Voltage V
PWM Low Level Voltage V
LED_EN Impedance Z
LED_EN High Voltage
LED_EN Low Voltage
PWM 20 40 60 kΩ
PWM - 220 - Hz 11
PWM_H
PWM_L
PWM 20 40 60 kΩ
V
LED_EN
_H
V
LED_EN
_L
2.2 - 5.3 V
0-0.5V
2.2 - 5.3 V
0-0.5V
Life Time 12,000 - - Hrs 12
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Note)
1. The measuring position is the connector of LCM and the test conditions are under 25, fv = 60Hz,
Black pattern.
2. The specified Icc current and power consumption are under
the Vcc = 3.3V , 25, fv = 60Hz condition and Mosaic pattern.
3. This Spec. is the max load condition for the cable impedance designing.
4. The below figures are the measuring Vcc condition and the Vcc control block LGD used.
The Vcc condition is same as the minimum of T1 at Power on sequence.
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LP140WD2
Liquid Crystal Display
Product Specification
Rising time
Vcc
0V
5. This impedance value is needed for proper display and measured form LVDS Tx to the mating connector.
6. The measuring position is the connector of LCM and the test conditions are under 25.
7. The current and power consumption with LED Driver are under the Vled = 12.0V , 25, Dimming of
Max luminance and W hite pattern with the normal frame frequency operated(60Hz).
8. The below figures are the measuring Vled condition
and the Vled control block LGD used.
VLED control block is same with Vcc control block.
90%
10%
0.5ms
3.3V
Rising time
V
LED
0V
10%
12.0V
90%
0.5ms
9. The operation of LED Driver below minimum dimming ratio may cause flickering or reliability issue.
10. If Jitter of PWM is bigger than maximum, it may induce flickering.
11. This Spec. is not effective at 100% dimming ratio as an exception because it has DC level equivalent
to 0Hz. In spite of acceptable range as defined, the PWM Frequency should be fixed and stable for
more consistent brightness control at any specific level desired.
12. The life time is determined as the time at which brightness of LCD is 50% compare to that of minimum
value specified in table 7. under general user conditionU
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3-2. Interface Connections
This LCD employs two interface connections, a 40 pin connector used for the module electronics interface and
the other connector used for the integral backlight system.
Table 3. MODULE CONNECTOR PIN CONFIGURATION (CN1)
Pin Symbol Description Notes
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
19
23
24
19
26
27
19
29
30
31
32
33
34
35
36 LED_EN LED Backlight On/Off
37
38
39
40
NC No Connection
VCC LCD Logic and driver power (3.3V Typ.)
VCC LCD Logic and driver power (3.3V Typ.)
V EEDID DDC Power (3.3V)
NC No Connection
Clk EEDID DDC Clock
DATA EEDID DDC Data
ORX0- Negative LVDS differential data input
ORX0+ Positive LVDS differential data input
GND LCM Ground
ORX1- Negative LVDS differential data input
ORX1+ Positive LVDS differential data input
GND LCM Ground
ORX2- Negative LVDS differential data input
ORX2+ Positive LVDS differential data input
GND LCM Ground
ORXC- Negative LVDS differential clock input
ORXC+ Positive LVDS differential clock input
GND LCM Ground
ERX0- Negative LVDS differential data input
ERX0+ Positive LVDS differential data input
GND LCM Ground
ERX1- Negative LVDS differential data input
ERX1+ Positive LVDS differential data input
GND LCM Ground
ERX2- Negative LVDS differential data input
ERX2+ Positive LVDS differential data input
GND LCM Ground
ERXC- Negative LVDS differential clock input
ERXC+ Positive LVDS differential clock input
GND LCM Ground (LED Backlight Ground)
GND LCM Ground (LED Backlight Ground)
GND LCM Ground (LED Backlight Ground)
NC
No Connection
PWM System PWM Signal input for dimming
NC No Connection
VLED LED Backlight Power (7V-21V)
VLED LED Backlight Power (7V-21V)
VLED LED Backlight Power (7V-21V)
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Product Specification
LP140WD2
Liquid Crystal Display
[Interface Chip]
1. LCD :
SiW, SW 0646(LCD Controller)
Including LVDS Receiver.
2. System : SiW LVDSRx or equivalent
* Pin to Pin compatible with LVDS
[Connector]
LSMtron GT05Q-40S-H10 or equivalent
[Mating Connector]
Mating of IPEX 20455-040 or equivalent
[Connector pin arrangement]
[W
[LCD Module Rear View]
X
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3-3. LVDS Signal Timing Specifications
3-3-1. DC Specification
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LP140WD2
Liquid Crystal Display
Product Specification
Description
LVDS Differential Voltage |V
LVDS Common mode Voltage V
LVDS Input Voltage Range V
3-3-2. AC Specification
Description Symbol Min Max Unit Notes
LVDS Clock to Data Skew Margin
Symb
ol
| 100 600 mV -
ID
CM
IN
t
SKEW
t
SKEW
Min Max Unit Notes
0.6 1.8 V -
0.3 2.1 V -
- 400 + 400 ps
- 600 + 600 ps
85MHz > Fclk ≥
65MHz > Fclk ≥
65MHz
25MHz
LVDS Clock to Clock Skew Margin (Even
to Odd)
Maximum deviation
of input clock frequency during SSC
Maximum modulation frequency
of input clock during SSC
Ver. 1.0 Dec. 16. 2010
t
SKEW_EO
F
DEV
F
MOD
-1/7 + 1/7 T
clk
- · 3% -
- 200 KHz -
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