20Update Detail Information of PPID label and Revision Code-
29-31Update E-EDID Table (Checksum : 31)-
EDID
ver
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1. General Description
The LP133WH2 is a Color Active Matrix Liquid Crystal Display with an integral LED backlight system. The
matrix employs a-Si Thin Film Transistor as the active element. It is a transmissive type display operating in
the normally white mode. This TFT-LCD has 13.3 inches diagonally measured active display area with HD
resolution (1366 horizontal by 768 vertical pixel array). Each pixel is divided into Red, Green and Blue subpixels or dots which are arranged in vertical stripes. Gray scale or the brightness of the sub-pixel color is
determined with a 6-bit gray scale signal for each dot, thus, presenting a palette of more than 262,144
colors. The LP133WH2 has been designed to apply the interface method that enables low power, high
speed, low EMI. The LP133WH2 is intended to support applications where thin thickness, low power are
critical factors and graphic displays are important. In combination with the vertical arrangement of the subpixels, the LP133WH2 characteristics provide an excellent flat display for office automation products such
as Notebook PC.
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LP133WH2
Liquid Crystal Display
Product Specification
EEPROM Block
EEPROM Block
for EDID
for EDID
EEPROM Block
EEPROM Block
for Tcon Operating
User connector
for TconOperating
1
TFT-LCD Panel
40
Pin
Timing Control
LVDS
1port
VCC
VLED
LED_EN
PWM
Timing Control
(Tcon) Block
(Tcon) Block
DVCC
Power
Block
LED Driver
LED Driver
Block
TCLKs
Power
Block
Block
VGH, VGL, GMA
Control & DataPower
E
PI
DVCC, AVDD
GIP CLKs, DSC
VOUT_LED
FB1~4
768
(HD, GIP, TN)
Source Driver
LED Backlight Ass’y
EDID signal & Power
General Features
Active Screen Size13.3 inches diagonal
Outline Dimension306.3(Typ. H) Ý 177.7(Typ. V) Ý 3.6(D, Max.) mm
Pixel Pitch0.2148 Ý 0.2148 mm
Pixel Format1366 horiz. by 768 vert. Pixels RGB strip arrangement
Color Depth6-bit, 262,144 colors
2
Luminance, White200 cd/m
Power Consumption
Weight300 g (Max.)
Display Operating ModeTransmissive mode, Normally white
Surface TreatmentGlare treatment of the front polarizer
RoHS ComplianceYes
BFR / PVC / As Free Yes for all.
Total 3.0W(Max.) Logic : 0.8 W (Max.@ RGB), B/L : 2.2 W (Max.@ VLED 12V )
( 5P Typ.)
1366
(Bottom)
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2. Absolute Maximum Ratings
The following are maximum values which, if exceeded, may cause faulty operation or damage to the unit.
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LP133WH2
Liquid Crystal Display
Product Specification
Table 1. ABSOLUTE MAXIMUM RATINGS
ParameterSymbol
Power Input Voltage
Operating Temperature
Storage Temperature
Operating Ambient Humidity
Storage Humidity
VCC-0.34.0Vdcat 25 r 5qC
TOP050qC1
HST-2060qC1
HOP1090%RH1
HST1090%RH1
Values
UnitsNotes
MinMax
Note : 1. Temperature and relative humidity range are shown in the figure below.
Wet bulb temperature should be 39
Wet Bulb
20
]
30
Temperature [
10
0
qC Max, and no condensation of water.
90% 80%
60
50
40
60%
Humidity[(%)RH]
40%
20%
10%
Storage
Operation
-20
10
20304050
6070800
Dry Bulb Temperature []
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The LP133WH2 requires two power inputs. The first logic is employed to power the LCD electronics and to
drive the TFT array and liquid crystal. The second backlight is the input about LED BL with LED Driver.
Table 2. ELECTRICAL CHARACTERISTICS
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LP133WH2
Liquid Crystal Display
Product Specification
ParameterSymbol
UnitNotes
MinTypMax
LOGIC :
Values
Power Supply Input VoltageV
Power Supply Input CurrentRGBI
Power ConsumptionP
Power Supply Inrush CurrentI
LVDS ImpedanceZ
CC3.03.33.6V1
CC-220255mA2
CC-0.70.8W2
CC_P--1500mA3
LVDS90100110
ȳ
BACKLIGHT : ( with LED Driver)
LED Power Input VoltageV
LED Power Input CurrentI
LED Power ConsumptionP
LED Power Inrush CurrentI
LED7.012.021.0V5
LED--190mA6
LED-2.2W
LED_P--1500mA7
PWM Duty Ratio5-100%8
PWM Jitter
PWM ImpedanceZ
-
PWM204060kȳ
0-0.2%9
4
PWM FrequencyF
PWM High Level VoltageV
PWM Low Level VoltageV
LED_EN ImpedanceZ
LED_EN High VoltageV
LED_EN Low VoltageV
PWM200-1000Hz10
PWM_H
PWM_L
PWM204060kȳ
LED_EN_H3.0-5.3V
LED_EN_L0-0.3V
3.0-5.3V
0-0.3V
DBC_EN High Voltage3.0-5.3V
DBC_EN Low Voltage0-0.3V
Life Time
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15,000--Hrs12
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Note)
1. The measuring position is the connector of LCM and the test conditions are under 25, fv = 60Hz,
Black pattern.
2. The specified Icc current and power consumption are under
the Vcc = 3.3V , 25, fv = 60Hz condition and Mosaic pattern.
3. This Spec. is the max load condition for the cable impedance designing.
4. The below figures are the measuring Vcc condition and the Vcc control block LGD used.
The Vcc condition is same as the minimum of T1 at Power on sequence.
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LP133WH2
Liquid Crystal Display
Product Specification
Rising time
Vcc
0V
5. This impedance value is needed for proper display and measured form LVDS Tx to the mating connector.
6. The measuring position is the connector of LCM and the test conditions are under 25.
7. The current and power consumption with LED Driver are under the Vled = 12.0V , 25, Dimming of
Max luminance and White pattern with the normal frame frequency operated(60Hz).
8. The below figures are the measuring Vled condition
and the Vled control block LGD used.
VLED control block is same with Vcc control block.
90%
10%
0.5ms
3.3V
Rising time
LED
V
0V
10%
12.0V
90%
0.1ms
9. The operation of LED Driver below minimum dimming ratio may cause flickering or reliability issue.
10. If Jitter of PWM is bigger than maximum, it may induce flickering.
11. This Spec. is not effective at 100% dimming ratio as an exception because it has DC level equivalent
to 0Hz. In spite of acceptable range as defined, the PWM Frequency should be fixed and stable for
more consistent brightness control at any specific level desired.
12. The life time is determined as the time at which brightness of LCD is 50% compare to that of minimum
value specified in table 7. under general user condition.
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3-2. Interface Connections
This LCD employs two interface connections, a 40 pin connector used for the module electronics interface and
the other connector used for the integral backlight system.
Table 3. MODULE CONNECTOR PIN CONFIGURATION (CN1)
PinSymbolDescriptionNotes
1Test LoopDell’s Test loop to 34pin
2VCCLCD Logic and driver power (3.3V Typ.)
3VCCLCD Logic and driver power (3.3V Typ.)
4V EEDIDDDC Power (3.3V)
5BistLCD Panel Self Test Enable
6Clk EEDIDDDC Clock
7DATA EEDIDDDC Data
8ORX0-Negative LVDS differential data input
9ORX0+Positive LVDS differential data input
10GNDLCM Ground
11ORX1-Negative LVDS differential data input
12ORX1+Positive LVDS differential data input
13GNDLCM Ground
14ORX2-Negative LVDS differential data input
15ORX2+Positive LVDS differential data input
16GNDLCM Ground
17ORXC-Negative LVDS differential clock input
18ORXC+Positive LVDS differential clock input
19GNDLCM Ground
20
21
22GNDLCM Ground
23
24
25GNDLCM Ground
26
27
28GNDLCM Ground
29
30
31
32
33
34
35
36
37
38
39
40
NC
NC
NC
NC
NC
NC
NC
NC
GND
GND
GND
Test Loop
PWMSystem PWM Signal input for dimming
LED_EN
DBC_ENDynamic Backlight Control enable
VLEDLED Backlight Power (7V-21V)
VLEDLED Backlight Power (7V-21V)
VLEDLED Backlight Power (7V-21V)
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
LCM Ground (LED Backlight Ground)
LCM Ground (LED Backlight Ground)
LCM Ground (LED Backlight Ground)
Dell’s Test loop to 1pin
LED Backlight On/Off
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Product Specification
LP133WH2
Liquid Crystal Display
[Interface Chip]
1. LCD :
LGE, LG5410S (LCD Controller)
Including LVDS Receiver.
2. System : Pin to Pin compatible with LVDS
[Connector]
Hirose KN38-40S-0.5H
UJU IS050-L40B-C10 or equivalent
[Mating Connector]
20453-#40E-## series or equivalent
[Connector pin arrangement]
40
[LCD Module Rear View]
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3-3. LVDS Signal Timing Specifications
3-3-1. DC Specification
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LP133WH2
Liquid Crystal Display
Product Specification
VDD=1.8V
DescriptionSymbolMinTypMaxUnitNotes
LVDS Differential Voltage|V
LVDS Common mode VoltageV
LVDS Input Voltage RangeV
3-3-2. AC Specification
DescriptionSymbolMinMaxUnitNotes
LVDS Clock to Data Skew Margin
|100-600mV-
ID
CM
IN
|VID| /21.2VDD- |VID|/2V-
0.3-VDDV-
t
SKEW
t
SKEW
- 400+ 400ps
- 600+ 600ps
85MHz > Fclk ˻
65MHz
65MHz > Fclk ˻
25MHz
LVDS Clock to Clock Skew Margin (Even
to Odd)
Maximum deviation
of input clock frequency during SSC
Maximum modulation frequency
of input clock during SSC
Ver. 0.0Aug. 09. 2011
t
SKEW_EO
F
DEV
F
MOD
-1/7+ 1/7T
clk
-· 3%-
-200KHz-
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Freq.
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LP133WH2
Liquid Crystal Display
Product Specification
< Clock skew margin between channel >
F
max
F
center
F
min
3-3-3. Data Format
1) LVDS 1 Port
RCLK+
RA+/-
RB+/-
R3R2
G4G3
R1R0
G2G1
X
m
tvk
< Spread Spectrum >
G0R5R4R3R2R1R0
B1B0G5G4G3G2G1
m
G0
B1
QGm
kl}
Time
R5R4
B0G5
RC+/-
RD+/-
B5B4
G7G6
Previous (N-1)th CycleNext (N+1 )th Cycle
B3B2
R7R6
DE VSYNC HSYNCB5B4B3B2
XB7B6G7G6R7R6
Current (Nth ) Cycle
DE
VSYNC HSYNC
X
< LVDS Data Format >
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