The LD470DUE is a Color Active Matrix Liquid Crystal Display with an integral Light Emitting Diode (LED)
backlight system. The matrix employs a-Si Thin Film Transistor as the active element.
It is a transmissive display type which is operating in the normally black mode. It has a 46.96 inch diagonally
measured active display area with WUXGA resolution (1080 vertical by 1920 horizontal pixel array).
Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arrayed in vertical stripes.
Gray scale or the luminance of the sub-pixel color is determined with a 8-bit gray scale signal for each dot.
Therefore, it can present a palette of more than 16.7Million colors.
It has been designed to apply the 8-bit 2-port LVDS interface.
It is intended to support LCD PD where high brightness, super wide viewing angle, high color gamut,
high color depth and fast response time are important.
EPI(RGB)
Control
Signals
Power Signals
CNT (7pin)
LVDS
2Port
LVDS
Select
+12.0V
CN1
(51pin)
LVDS 1,2
Option
signal
I2C
LED Anode
LED Cathode
EEPROM
SCL
Timing Controller
LVDS Rx + Scanning
Power Circuit
SDA
Integrated
Block
General Features
Active Screen Size 46.96 inches(1192.78mm) diagonal
Outline Dimension 1067.6(H) X 617.4(V) X 36.5(B) mm (Typ.)
Source Driver Circuit
S1 S1920
G1
TFT - LCD Panel
(1920 × RGB × 1080 pixels)
[Gate In Panel]
G1080
Back light Assembly
Pixel Pitch 0.5415 mm x 0.5415 mm
Pixel Format 1920 horiz. by 1080 vert. Pixels, RGB stripe arrangement
Color Depth 8bit, 16.7Million colors
Luminance, White 400 cd/m2 (Center 1point ,Typ.)
Viewing Angle (CR>10) Viewing angle free ( R/L 178 (Min.), U/D 178 (Min.))
Power Consumption Total 86.4W(TBD) [Logic= 6.5W, LED only= 79.9W (ExtVbr_B=100% )]
Weight 9.4 kg (TBD)
Display Mode Transmissive mode, Normally black
Surface Treatment (TBD)Hard coating(3H), Anti-glare treatment of the front polarizer (Haze 1%)
Ver. 0.1
4 / 39
LD470DUE
Product Specification
2. Absolute Maximum Ratings
The following items are maximum values which, if exceeded, may cause faulty operation or permanent damage
to the LCD module.
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter Symbol
Unit Note
Min Max
Power Input Voltage LCD Circuit VLCD -0.3 +14.0 VDC
Value
LED Input Voltage Forward Voltage VF - +130(TBD) VDC
T-Con Option Selection Voltage VLOGIC
-0.3 +4.0 VDC
1
Operating Temperature TOP 0 +50 °C
2,3
Storage Temperature TST -20 +60 °C
Panel Front Temperature TSUR
- +68 °C 4
Operating Ambient Humidity HOP 10 90 %RH
2,3
Storage Humidity HST 10 90 %RH
Note
1. Ambient temperature condition (Ta = 25 2 °C )
2. Temperature and relative humidity range are shown in the figure below.
Wet bulb temperature should be Max 39°C, and no condensation of water.
3. Gravity mura can be guaranteed below 40°C condition.
4. The maximum operating temperatures is based on the test condition that the surface temperature
of display area is less than or equal to 68°C with LCD module alone in a temperature controlled chamber.
Thermal management should be considered in final product design to prevent the surface temperature of
display area from being over 68℃. The range of operating temperature may be degraded in case of
improper thermal management in final product design.
It requires two power inputs. One is employed to power for the LCD circuit. The other Is used for the LED
backlight and LED Driver circuit.
Table 2. ELECTRICAL CHARACTERISTICS
Parameter Symbol
Unit Note
Min Typ Max
Circuit :
Power Input Voltage VLCD 10.8 12.0 13.2 VDC
- 501(TBD) 626(TBD) mA 1
Power Input Current ILCD
- 717(TBD) 897(TBD) mA 2
Power Consumption PLCD 6.00(TBD) 8.26(TBD) Watt 1
Rush current IRUSH - - 5.0 A 3
Value
Note
1. The specified current and power consumption are under the V
=12.0V, Ta=25 2°C, fV=60Hz
LCD
condition, and mosaic pattern(8 x 6) is displayed and fV is the frame frequency.
2. The current is specified at the maximum current pattern.
3. The duration of rush current is about 2ms and rising time of power input is 0.5ms (min.).
4. Ripple voltage level is recommended under ±5% of typical voltage
Ver. 0.1
White : 255 Gray
Black : 0 Gray
Mosaic Pattern(8 x 6)
6 / 39
Product Specification
Table 3. ELECTRICAL CHARACTERISTICS (Continue)
LD470DUE
Parameter Symbol
Backlight Assembly :
Forward Current
(one array)
Forward Voltage V
Forward Voltage Variation △V
Power Consumption P
Burst Dimming Duty On duty
Burst Dimming Frequency 1/T
LED Array : (APPENDIX-V)
Life Time 30,000 Hrs 7
Notes :
The design of the LED driver must have specifications for the LED array in LCD Assembly.
Anode I
Cathode I
F (anode)
F (cathode)
F
F
BL
Min Typ Max
91.8 99.9 108 Vdc
- 79.9 W 6
1 100 %
95 182 Hz 8
Values
400 mAdc
400 mAdc
Unit Note
Vdc
The electrical characteristics of LED driver are based on Constant Current driving type.
The performance of the LED in LCM, for example life time or brightness, is extremely influenced by the
characteristics of the LED Driver. So, all the parameters of an LED driver should be carefully designed.
When you design or order the LED driver, please make sure unwanted lighting caused by the mismatch of the
LED and the driver (no lighting, flicker, etc) has never been occurred. When you confirm it, the LCD–
Assembly should be operated in the same condition as installed in your instrument.
1. Electrical characteristics are based on LED Array specification.
2. Specified values are defined for a Backlight Assembly. (IBL :6 LED array/LCM)
3. Each LED array has one anode terminal and one cathode terminals.
The forward current(IF) of the anode terminal is TBDmA and it supplies TBDmA into 1 strings, respectively
Anode#1
400mA
1 Arrary(9 LED PKG)
°°°
Cathode #1
°°°
Cathode #2
1 String (3 Array)
°°°
Cathode #3
400 mA
4. The forward voltage(VF) of LED array depends on ambient temperature (Appendix-V)
5. ΔVF means Max VF-Min VF in one Backlight. So VF variation in a Backlight isn’t over Max. TBDV
6. Maximum level of power consumption is measured at initial turn on.
Typical level of power consumption is measured after 1hrs aging at 25 2°C.
7. The life time(MTTF) is determined as the time at which brightness of the LED is 50% compared to that of
initial value at the typical LED current on condition of continuous operating at 25 2°C, based on duty 100%.
8. The reference method of burst dimming duty ratio.
It is recommended to use synchronous V-sync frequency to prevent waterfall
(Vsync * 2 =Burst Frequency)
Though PWM frequency is over 182Hz (max252Hz), function of backlight is not affected.
Ver. 0.1
±5%
2, 3
4
5
7 /35
Product Specification
3-2. Interface Connections
This LCD module employs two kinds of interface connection, 51-pin connector is used for the module
electronics and 14-pin connector is used for the integral backlight system.
3-2-1. LCD Module
-LCD Connector(CN1): FI-RE51S-HF(manufactured by JAE)
No Connection or Ground
No Connection (Note 4)
No Connection (Note 4)
No Connection (Note 4)
No Connection (Note 4)
No Connection (Note 4)
‘H’ =JEIDA , ‘L’ or NC = VESA
No Connection (Note 4)
No Connection (Note 4)
No Connection (Note 4)
Ground
FIRST LVDS Receiver Signal (A-)
FIRST LVDS Receiver Signal (A+)
FIRST LVDS Receiver Signal (B-)
FIRST LVDS Receiver Signal (B+)
FIRST LVDS Receiver Signal (C-)
FIRST LVDS Receiver Signal (C+)
Ground
FIRST LVDS Receiver Clock Signal(-)
FIRST LVDS Receiver Clock Signal(+)
Ground
FIRST LVDS Receiver Signal (D-)
FIRST LVDS Receiver Signal (D+)
No Connection
No Connection
No Connection or Ground
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
- - -
NC
R2AN
R2AP
R2BN
R2BP
R2CN
R2CP
GND
R2CLKN
R2CLKP
GND
R2DN
R2DP
NC
NC
NC or GND
NC or GND
GND Ground
GND Ground
GND Ground
NC No connection
VLCD Power Supply +12.0V
VLCD Power Supply +12.0V
VLCD Power Supply +12.0V
VLCD Power Supply +12.0V
No Connection
SECOND LVDS Receiver Signal (A-)
SECOND LVDS Receiver Signal (A+)
SECOND LVDS Receiver Signal (B-)
SECOND LVDS Receiver Signal (B+)
SECOND LVDS Receiver Signal (C-)
SECOND LVDS Receiver Signal (C+)
Ground
SECOND LVDS Receiver Clock Signal(-)
SECOND LVDS Receiver Clock Signal(+)
Ground
SECOND LVDS Receiver Signal (D-)
SECOND LVDS Receiver Signal (D+)
No Connection
No Connection
No Connection or Ground
No Connection or Ground
LD470DUE
Note
1. All GND(ground) pins should be connected together to the LCD module’s metal frame.
2. All VLCD (power input) pins should be connected together.
3. All Input levels of LVDS signals are based on the EIA 644 Standard.
4. #1~#6 & #8~#10 NC (No Connection): These pins are used only for LGD (Do not connect)
5. Specific pin No. #44is used for “No signal detection” of system signal interface.
It should be GND for NSB(No Signal Black) during the system interface signal is not.
If this pin is “H”, LCD Module displays AGP(Auto Generation Pattern).
Ver. 0.1
8 / 39
Product Specification
3-2-2. Backlight Module
[ CN201 ]
1) LED Array assy Connector (Plug)
: SMH200-07 (TBD)
1 L2 Cathode LED Output Current L2
2 NC
3 L2 Anode LED Input Current for L2
4 NC
5 L1 Cathode LED Output Current for L1
6 NC
7 L1 Anode LED Input Current for L1
◆ Rear view of LCM
Description
L6
L4 L5
CN201
7pin
Note
R6
R4 R5
Ver. 0.1
L2 L3
TBD
R2 R3
L1
T-con
배면
R1
9 /35
LD470DUE
Product Specification
3-3. Signal Timing Specifications
Table 6 shows the signal timing required at the input of the LVDS transmitter. All of the interface signal
timings should be satisfied with the following specification for normal operation.
Table 6. TIMING TABLE (DE Only Mode)
ITEM Symbol Min Typ Max Unit Note
Horizontal
Vertical
Frequency
Display
Period
Blank tHB 100 140 240 tCLK 1
Total tHP 1060 1100 1200 tCLK
Display
Period
Blank tVB
Total tVP
ITEM Symbol Min Typ Max Unit Note
DCLK fCLK 63.00 74.25 78.00 MHz
Horizontal fH 57.3 67.5 70 KHz 2
Vertical fV
tHV 960 960 960 tCLK 1920 / 2
tVV 1080 1080 1080 Lines
20
(228)
1100
(1308)
57
(47)
45
(270)
1125
(1350)
60
(50)
69
(300)
1149
(1380)
63
(53)
Lines 1
Lines
Hz
NTSC
(PAL)
2
Note: 1. The input of HSYNC & VSYNC signal does not have an effect on normal operation (DE Only Mode).
If you use spread spectrum of EMI, add some additional clock to minimum value for clock margin.
2. The performance of the electro-optical characteristics may be influenced by variance of the vertical
refresh rate and the horizontal frequency
※ Timing should be set based on clock frequency.
Ver. 0.1
10 / 39
3-4. LVDS Signal Specification
3-4-1. LVDS Input Signal Timing Diagram
LD470DUE
Product Specification
DE, Data
DCLK
First data
Second data
0.7VDD
0.3VDD
tCLK
DE(Data Enable)
0.5 VDD
Invalid data
Invalid data
Valid data
Pixel 0,0 Pixel 2,0
Valid data
Pixel 1,0 Pixel 3,0
tHP
Invalid data
Invalid data
tHV
DE(Data Enable)
Ver. 0.1
1 1080
tVV
tVP
11 / 39
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