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LD420WUN
Product Specification
CONTENTS
NumberITEM
COVER1
CONTENTS
RECORD OF REVISIONS
1GENERAL DESCRIPTION
2ABSOLUTE MAXIMUM RATINGS
3ELECTRICAL SPECIFICATIONS
3-1ELECTRICAL CHARACTERISTICS
3-2INTERFACE CONNECTIONS
3-3SIGNAL TIMING SPECIFICATIONS
3-4SIGNAL TIMING WAVEFORMS
3-5COLOR DATA REFERENCE
3-6POWER SEQUENCE
4OPTICAL SPECIFICATIONS
5MECHANICAL CHARACTERISTICS
Page
2
3
4
5
6
6
8
10
11
12
13
15
19
6RELIABILITY
7INTERNATIONAL STANDARDS
7-1SAFETY
7-2EMC
8PACKING
8-1DESIGNATION OF LOT MARK
8-2PACKING FORM
9PRECAUTIONS
9-1MOUNTING PRECAUTIONS
9-2OPERATING PRECAUTIONS
9-3ELECTROSTATIC DISCHARGE CONTROL
9-4PRECAUTIONS FOR STRONG LIGHT EXPOSURE
9-5STORAGE
9-6HANDLING PRECAUTIONS FOR PROTECTION FILM
9-7APPROPRIATE CONDITION FOR PUBLIC DISPLAY
Ver. 1.0
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Revision No.Revision DatePageDescription
1.0Nov, 24, 2008-Final Specification
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LD420WUN
Product Specification
RECORD OF REVISIONS
Ver. 1.0
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1. General Description
LD420WUN is a Color Active Matrix Liquid Crystal Display with an integral Cold Cathode Fluorescent
Lamp(EEFL) backlight system. The matrix employs a-Si Thin Film Transistor as the active element.
It is a transmissive type display operating in the normally black mode. It has a 42 inch diagonally measured
active display area with WUXGA resolution (1080 vertical by 1920 horizontal pixel array)
Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arranged in vertical stripes.
Gray scale or the luminance of the sub-pixel color is determined with a 8bit or 10-bit gray scale signal for
each dot, thus presenting a palette of more than 1.06Billion of colors.
It has been designed to apply the 10-bit 2 port LVDS interface.
It is intended to support Public Display where high brightness, super wide viewing angle, high color gamut,
high color depth and fast moving picture response time are important.
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LD420WUN
Product Specification
Mini-LVDS(RGB)
G1
Gate Driver Circuit
G1080
Source Driver Circuit
S1S1920
TFT - LCD Panel
(1920 Ý RGB Ý 1080 pixels)
+12.0V
LVDS
2Port
Bit
Selection
DCR
Enable
VBR_EXT
VBR_OUT
CN1
(51pin)
EEPROM
SCL
SDA
Timing Controller
[LVDS Rx + DCR + ODC
integrated]
Power Circuit
Block
+24.0V, GND, VBR-A, VBR-B
Status
+24.0V, GND
Inverter(14Pin)
3PinX1CN(High)
Back light Assembly
3PinX1CN(High)
General Features
Active Screen Size42.02 inches(1067.31mm) diagonal
Outline Dimension983.0(H) x 576.0 (V) x 51.0 mm(D) (Typ.)
Pixel Pitch0.4845 mm x 0.4845 mm
Pixel Format1920 horiz. by 1080 vert. Pixels, RGB stripe arrangement
1. Electrical characteristics are determined after the unit has been ‘ON’ and stable for approximately 120
minutes at 25·2¶C. The specified current and power consumption are under the typical supply Input voltage
24Vand V
BR (VBR-A : 1.65V & VBR-B :3.3V), it is total power consumption.
The ripple voltage of the power supply input voltage is under 0.5 Vp-p. LPL recommend Input Voltage is
24.0V · 5%.
2. Electrical characteristics are determined within 30 minutes at 25·2¶C.
The specified currents are under the typical supply Input voltage 24V.
3. The brightness of the lamp after lighted for 5minutes is defined as 100%.
TS is the time required for the brightness of the center of the lamp to be not less than 95% at typical current.
The screen of LCD module may be partially dark by the time the brightness of lamp is stable after turn on.
4. Specified Values are for a single lamp which is aligned horizontally.
The life time is determined as the time which luminance of the lamp is 50% compared to that of initial value
at the typical lamp current (V
BR-A : 1.65V & VBR-B :3.3V), on condition of continuous operating at 25· 2¶C
5. The duration of rush current is about 10 ms.
6. Brightness Control.
BR-B Voltage control brightness.
This V
VBR-B Voltage
Function
VBR-B Voltage
Function
Maximum Duty (100%)3.3VMinimum Duty (18%)0V
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3-2. Interface Connections
This LCD module employs two kinds of interface connection, a 51-pin connector is used for the module
electronics and Master 14-pin and Slave 12-pin connectors are used for the integral backlight system.
3-2-1. LCD Module
- LCD Connector(CN1): FI-R51S-HF(manufactured by JAE) or KN25-51P-0.5SH(manufactured by Hirose)
- Mating Connector : FI-R51HL(JAE) or compatible
Table 4. MODULE CONNECTOR(CN1) PIN CONFIGURATION
NoSymbolDescriptionNoSymbolDescription
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
GND
NCNo Connection
NCNo Connection
NCNo Connection
NCNo Connection
NCNo Connection
LVDS Select‘H’ =JEIDA , ‘L’ = VESA
VBR_EXTExternal VBR
VBR_OUTVBR output
DCR_Enable‘H’ = Enable , ‘L’ = Disable
GND
RO0N
RO0P
RO1N
RO1P
RO2N
RO2P
GND
ROCLKN
ROCLKP
GND
RO3N
RO3P
RO4N
RO4P
Reserved
FIRST CHANNEL 0-
FIRST CHANNEL 0+
FIRST CHANNEL 1-
FIRST CHANNEL 1+
FIRST CHANNEL 2-
FIRST CHANNEL 2+
FIRST CLOCK CHANNEL C-
FIRST CLOCK CHANNEL C+
FIRST CHANNEL 3-
FIRST CHANNEL 3+
FIRST CHANNEL 4- (For 10bit D)
FIRST CHANNEL 4+ (For 10bit D)
No connection or GND
Ground
Ground
Ground
Ground
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Product Specification
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
-
Bit Selection
RE0N
RE0P
RE1N
RE1P
RE2N
RE2P
GND
RECLKN
RECLKP
GND
RE3N
RE3P
RE4N
RE4P
Reserved
Reserved
GND
GND
GND
NC
VLCD
VLCD
VLCD
VLCD
LD420WUN
‘L’=8bit,’H’=10bit (D)
SECOND CHANNEL 0-
SECOND CHANNEL 0+
SECOND CHANNEL 1-
SECOND CHANNEL 1+
SECOND CHANNEL 2-
SECOND CHANNEL 2+
Ground
SECOND CLOCK CHANNEL C-
SECOND CLOCK CHANNEL C+
Ground
SECOND CHANNEL 3-
SECOND CHANNEL 3+
SECOND CHANNEL 4- (For 10bit D)
SECOND CHANNEL 4+ (For 10bit D)
No connection or GND
No connection or GND
Ground
Ground
Ground
No connection
Power Supply +12.0V
Power Supply +12.0V
Power Supply +12.0V
Power Supply +12.0V
--
Notes :
1. The pin no 44 is LCD Test option. “AGP” (Auto Generation LCM operates Pattern) or “NSB” (No Signal
Black) is case that LVDS signals are out of frequency or abnormal condition in spite of 12 volt power
supply. LPL recommends “NSB”. ( AGP : “VCC” or “OPEN” / NSB : “GND” )
2. All GND(ground) pins should be connected together to the LCD module’s metal frame.
3. All VLCD (power input) pins should be connected together.
4. All Input levels of LVDS signals are based on the IEA 664 Standard.
5. Specific pins(pin No. #1~#10) are used for internal data process of the LCD module.
If not used, these pins are no connection.
6. If DCR function should be enable(‘H’), 10th pin must be connected to serial resistor which value is under
1k ohm.
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ଝ
3-2-2. Backlight Inverter
Inverter Connector : S14B-PH-SMC
(manufactured by JST) or Equivalent
- Mating Connector : PHR-14 or Equivalent
Table 5. INVERTER CONNECTOR PIN CONFIGULATION
Pin NoSymbolDescriptionInv.Note
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LD420WUN
Product Specification
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VBLPower Supply +24.0VVBL
VBLPower Supply +24.0V
VBLPower Supply +24.0V
VBLPower Supply +24.0V
VBLPower Supply +24.0V
GNDBacklight Ground
GNDBacklight Ground
GNDBacklight Ground
GNDBacklight Ground
GNDBacklight Ground
VBR-A
ON/OFF
V
VBR-B
Status
Analog dimming voltage
DC 0.0V ~ 3.3V (Typ : 1.65V)
0.0V ~ 5.0V
Burst dimming voltage
DC 0.0V ~ 3.3V
Normal : Upper 3.0V
Abnormal : Under 0.7V
VBL
VBL
VBL
VBL
GND
GND
GND
GND
GND
V
BR-A2, 3
On/Off
V
BR-B
Status4
Notes : 1. GND should be connected to the LCD module’s metal frame.
2. If Pin #11 is open, V
BR-A = 1.65V. When apply over 1.65V( ~ 3.3V) continuously,
its luminance is increasing however lamp’s life time is decreasing.
It could be usable for boost up luminance when using DCR (=Dynamic contrast ratio) function only.
3. Minimum Brightness : V
BR-B =0V Maximum Brightness : VBR-B = 3.3V
4. Even though Pin #14 is open, there is no effect on inverter operating, The output terminal of inverter..
5. Each impedance of pin #11,12 and 13 is 240[༮], 80[༮], 160[༮]
1
3
Rear view of LCM
14
…
1
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3-3. Signal Timing Specifications
Table 6 shows the signal timing required at the input of the LVDS transmitter. All of the interface signal timing
should be satisfied with the following specification for normal operation.
Table 6. TIMING TABLE for NTSC (DE Only Mode)
ITEMSymbolMinTypMaxUnitNote
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LD420WUN
Product Specification
Horizontal
Vertical
Frequency
Display Periodt
Blank
Total
Display Periodt
Blankt
Totalt
Symbol
DCLK
Horizontal
Vertical
HV
HB
t
tHP
VV-1080-Lines
VB114569Lines
VP109111251149Lines
fCLK
fH
f
V
-960-tclk
100140240tclk
106011001200tclk2200/2
NoteUnitMaxTypMinITEM
148.5/2MHz7774.2570
KHz7067.565
Hz636057
Table 7 shows the signal timing required at the input of the LVDS transmitter. All of the interface signal timing
should be satisfied with the following specification for normal operation.
Table 7. TIMING TABLE for PAL (DE Only Mode)
Display Period
Symbol
tHV
tclk-960-
NoteUnitMaxTypMinITEM
Horizontal
Vertical
Frequency
Blank
Total
DCLK
Horizontal
Vertical
tHB
HP
t
VVDisplay Period
VBBlank
VPTotal
Symbol
fCLK
fH
fV
tclk240140100
2200/2tclk120011001060
Lines-1080-t
Lines300270228t
Lines138013501308t
NoteUnitMaxTypMinITEM
148.5/2MHz7774.2570
KHz7067.565
Hz535047
Note : The Input of HSYNC & VSYNC signal does not have an effect on normal operation(DE Only Mode).
The performance of the electro-optical characteristics may be influenced by variance of the vertical refresh rate.
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