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1. General Description
LD420WUB is a Color Active Matrix Liquid Crystal Display with an integral Cold Cathode Fluorescent
Lamp(CCFL) backlight system. The matrix employs a-Si Thin Film Transistor as the active element.
It is a transmissive type display operating in the normally black mode. It has a 42 inch diagonally measured
act i ve d is p la y area w i th W U X GA res o l u t io n (1080 ve rtical b y 1920 horizontal pixel ar ray)
Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arranged in vertical stripes.
Gray scale or the luminance of the sub-pixel color is determined with a 8bit or 10-bit gray scale signal for
each dot, thus presenting a palette of more than 1.06Billion of colors.
It has been designed to apply the 10-bit 2 port LVDS interface.
It is intended to support Public Display where high brightness, super wide viewing angle, high color gamut,
high color depth and fast moving picture response time are important.
1. Electrical characteristics are determined after the unit has been ‘ON’ and stable for approximately 120
minutes at 25±2°C. The specified current and power consumption are under the typical supply Input voltage
24Vand VBR (VBR-A : 1.65V & VBR-B : 3.3V), it is total power consumption.
The ripple voltage of the power supply input voltage is under 0.5 Vp-p. LGD recommend Input Voltage is
24.0V ± 5%.
2. Electrical characteristics are determined within 30 minutes at 25±2°C.
The specified currents are under the typical supply Input voltage 24V.
3. The brightness of the lamp after lighted for 5minutes is defined as 100%.
TS is the time required for the brightness of the center of the lamp to be not less than 95% at typical current.
The screen of LCD module may be partially dark by the time the brightness of lamp is stable after turn on.
4. Specified Values are for a single lamp which is aligned horizontally.
The life time is determined as the time which luminance of the lamp is 50% compared to that of initial value
at the typical lamp current (VBR-A : 1.65V & VBR-B : 3.3V), on condition of continuous operating at 25± 2°C
5. The duration of rush current is about 20ms.
Ver1.0
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3-2. Interface Connections
This LCD module employs two kinds of interface connection, a 51-pin connector is used for the module
electronics and Master 14-pin and Slave 12-pin connectors are used for the integral backlight system.
3-2-1. LCD Module
- LCD Connector(CN1): FI-R51S-HF(manufactured by JAE) or KN25-51P-0.5SH(manufactured by Hirose)
- Mating Connector : FI-R51HL(JAE) or compatible
Table 4. MODULE CONNECTOR(CN1) PIN CONFIGURATION
LD420WUB
Product Specification
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
DescriptionSymbolNo
1
2
3
4
5
6
7
8
9
GND
GND
RO0N
RO0P
RO1N
RO1P
RO2N
RO2P
GND
ROCLKN
ROCLKP
GND
RO3N
RO3P
RO4N
RO4P
Reserved
FIRST CLOCK CHANNEL C-
FIRST CLOCK CHANNEL C+
FIRST CHANNEL 4- (For 10bit D)
FIRST CHANNEL 4+ (For 10bit D)
Ground
No ConnectionNC
No ConnectionNC
No ConnectionNC
No ConnectionNC
No ConnectionNC
‘H’ =JEIDA , ‘L’ = VESA LVDS Select
No ConnectionNC
No ConnectionNC
No ConnectionNC
Ground
FIRST CHANNEL 0-
FIRST CHANNEL 0+
FIRST CHANNEL 1-
FIRST CHANNEL 1+
FIRST CHANNEL 2-
FIRST CHANNEL 2+
Ground
Ground
FIRST CHANNEL 3-
FIRST CHANNEL 3+
No connection or GND
No
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
-
Symbol
Bit Selection
RE0N
RE0P
RE1N
RE1P
RE2N
RE2P
GND
RECLKN
RECLKP
GND
RE3N
RE3P
RE4N
RE4P
Reserved
Reserved
GND
GND
GND
NC
VLCD
VLCD
VLCD
VLCD
-
SECOND CLOCK CHANNEL C-
SECOND CLOCK CHANNEL C+
SECOND CHANNEL 4- (For 10bit D)
SECOND CHANNEL 4+ (For 10bit D)
Description
‘L’=8bit,’H’=10bit (D)
SECOND CHANNEL 0-
SECOND CHANNEL 0+
SECOND CHANNEL 1-
SECOND CHANNEL 1+
SECOND CHANNEL 2-
SECOND CHANNEL 2+
Ground
Ground
SECOND CHANNEL 3-
SECOND CHANNEL 3+
No connection or GND
No connection or GND
Ground
Ground
Ground
No connection
Power Supply +12.0V
Power Supply +12.0V
Power Supply +12.0V
Power Supply +12.0V
-
Notes :
1. The pin no 47 is LCD Test option. “AGP” (Auto Generation LCM operates Pattern) or “NSB” (No Signal
Black) is case that LVDS signals are out of frequency or abnormal condition in spite of 12 volt power
supply. LGD recommends “NSB”.( AGP : “VCC” / NSB : “GND” )
2. All GND(ground) pins should be connected together to the LCD module’s metal frame.
3. All VLCD (power input) pins should be connected together.
4. All Input levels of LVDS signals are based on the IEA 664 Standard.
5. Specific pins(pin No. #1~#10) are used for internal data process of the LCD module.
If not used, these pins are no connection.
6. If OPC function should be enable(‘H’), 10th pin must be connected to serial resistor which value is under
1k ohm.
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3-2-2. Backlight Inverter
Inverter Connector : S14B-PH-SMC
(manufactured by JST) or Equivalent
- Mating Connector : PHR-14 or Equivalent
Table 5. INVERTER CONNECTOR PIN CONFIGULATION
Product Specification
Master
Slave
LD420WUB
NoteDescriptionSymbolPin No
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VBR-A
ON/OFF
VBR-B
Status
Power Supply +24.0VVBL
Power Supply +24.0VVBL
Power Supply +24.0VVBL
Power Supply +24.0VVBL
Power Supply +24.0VVBL
Backlight GroundGND
Backlight GroundGND
Backlight GroundGND
Backlight GroundGND
Backlight GroundGND
Analog dimming voltage
DC 0.0V ~ 3.3V (Typ : 1.65V)
Burst dimming voltage
DC 0.0V ~ 3.3V
Normal : Upper 3.0V
Abnormal : Under 0.7V
VBL
VBL
VBL
VBL
VBL
GND
GND
GND
GND
GND
VBR-B
Status
Notes : 1. GND should be connected to the LCD module’s metal frame.
2. If Pin #11 is open, VBR-A = 1.65V. When apply over 1.65V( ~ 3.3V) continuously,
its luminance is increasing however lamp’s life time is decreasing.
It could be usable for boost up luminance when using DCR (=Dynamic contrast ratio) function only.
4. Even though Pin #14 is open, there is no effect on inverter operating, The output terminal of inverter..
5. Each impedance of pin #11,12 and 13 is 186[㏀], 27.6[㏀], 116[㏀]
Don’t careOn/Off0.0V ~ 5.0VV
VBL
VBL
VBL
VBL
VBL
GND
GND
GND
GND
GND
-
1
2, 3Don’t careVBR-A
3
4-
◆◆◆◆ Rear view of LCM
14
…
PCB
…
1
PCB
…
…
1
<Master>
Ver1.0
12
<Slave>
9 / 35
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3-3. Signal Timing Specifications
Table 6 shows the signal timing required at the input of the LVDS transmitter. All of the interface signal
timings should be satisfied with the following specification for normal operation.
Table 6-1. TIMING TABLE for NTSC (DE Only Mode)
ITEMSymbolMinTypMaxUnitNote
Display PeriodtHV-960-tclk
LD420WUB
Product Specification
Horizontal
Vertical
Frequency
BlanktHB100140240tclk
TotaltHP106011001200tclk2200/2
Display PeriodtVV-1080-tHP
BlanktVB114569tHP
TotaltVP109111251149tHP
DCLKfCLK7074.2577MHz148.5/2
HorizontalfH6567.570KHz
VerticalfV576063Hz
Table 6-2. TIMING TABLE for PAL (DE Only Mode)
ITEMSymbolMinTypMaxUnitNote
Display PeriodtHV-960-tclk
Horizontal
BlanktHB100140240tclk
TotaltHP106011001200tclk2200/2
Display PeriodtVV-1080-tHP
Vertical
Frequency
Note
The Input of HSYNC & VSYNC signal does not have an effect on normal operation(DE Only Mode).
BlanktVB228270300tHP
TotaltVP130813501380tHP
DCLKfCLK7074.2577MHz148.5/2
HorizontalfH6567.570KHz
VerticalfV475053Hz
The performance of the electro-optical characteristics may be influenced by variance of the vertical
refresh rate.
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3-4. LVDS Signal Specification
3-4-1. LVDS Input Signal Timing Diagram
LD420WUB
Product Specification
DE, Data
DCLK
First data
Second data
0.7VDD
0.3VDD
tCLK
DE(Data Enable)
0.5 VDD
Invalid data
Invalid data
Valid data
Pixel 0,0
Valid data
Pixel 1,0
tHP
Pixel 2,0
Pixel 3,0
Invalid data
Invalid data
tHV
DE(Data Enable)
Ver1.0
11080
tVV
tVP
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