LG Display LC840EQD-SEM1 Specification
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Product Specification
SPECIFICATION
FOR
APPROVAL
G
LC840EQD
( ) Preliminary Specification
()Final Specification
Title 84.0” QWUXGA TFT LCD
BUYER General
MODEL
APPROVED BY
/
/
SIGNATURE
DATE
SUPPLIER LG Display Co., Ltd.
*MODEL LC840EQD
SUFFIX SEM1 (RoHS Verified)
*When you obtain standard approval,
please use the above model name without suffix
APPROVED BY
S.K.Park / Team Leader
REVIEWED BY
S.W. Yu / Project Leader
SIGNATURE
DATE
PREPARED BY
/
Please return 1 copy for your confirmation with
your signature and comments.
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G
K.H.Jang / Engineer
TV Product Development Dept.
LG Display Co., Ltd.
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Product Specification
CONTENTS
G
LC840EQD
Number ITEM
COVER -
CONTENTS
RECORD OF REVISIONS 2
1 GENERAL DESCRIPTION
2 ABSOLUTE MAXIMUM RATINGS
3 ELECTRICAL SPECIFICATIONS
3-1 ELECTRICAL CHARACTERISTICS
3-2 INTERFACE CONNECTIONS
3-3 SIGNAL TIMING SPECIFICATIONS
3-4 V by One SIGNAL SPECIFICATIONS 12
3-5 COLOR DATA REFERENCE
3-6 POW ER SEQUENCE
4 OPTICAL SPECIFICATIONS
5 MECHANICAL CHARACTERISTICS
6 RELIABILITY
Page
1
3
4
5
5
7
11
14
15
17
21
24
7 INTERNATIONAL STANDARDS
7-1 SAFETY
7-2 EMC
7-3 ENVIRONMENT
8 PACKING
8-1 INFORMATION OF LCM LABEL
8-2 PACKING FORM
9 PRECAUTIONS 27
9-1 MOUNTING PRECAUTIONS 27
9-2 OPERATING PRECAUTIONS 27
9-3 ELECTROSTATIC DISCHARGE CONTROL 28
9-4 PRECAUTIONS FOR STRONG LIGHT EXPOSURE 28
9-5 STORAGE 28
9-6 HANDLING PRECAUTIONS FOR PROTECTION FILM 28
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Revision No. Revision Date Page Description
0.1 Mar, 30, 2012 - Preliminary Specification (First Draft)
0.2 July.16.2012 3,5,6 Update the power consumption
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LC840EQD
Product Specification
RECORD OF REVISIONS
3,21 Update the information of weight
13 Delete The intra pair skew
15 Update the power sequence( Delete Vcm ot the interface sigmal )
17 Update the optical Spec.
G
22,23 Update the mechanical drawing
26,29 Update the information of packing
0.3 Aug.02.2012 22,23 Update the mechanical drawing
1.0 Aug.02.2012 - CAS Version 1.0 Release
- Final Specification
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1. General Description
The LC840EQD is a Color Active Matrix Liquid Crystal Display with an integral Light Emitting Diode (LED)
backlight system. The matrix employs a-Si Thin Film Transistor as the active element.
It is a transmissive display type which is operating in the normally black mode. It has a 84.04 inch diagonally
measured active display area with QWUXGA resolution (2160 vertical by 3840 horizontal pixel array).
Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arrayed in vertical stripes.
Gray scale or the luminance of the sub-pixel color is determined with a 10-bit gray scale signal for each dot.
Therefore, it can present a palette of more than 1.06Bilioncolors.
It has been designed to apply the 10-bit 16 Lane V by One interface.
It is intended to support LCD TV, PCTV where high brightness, super wide viewing angle, high color gamut,
high color depth and fast response time are important.
Vby1
8lane
Vby1
8lane
CN1
5pin)
CN2
(51pin)
CN3
(41pin)
+12.0V
Vby1
1~8lane
Option
signal
Vby1
9~16lane
EEPROM
SCL
Timing Controller
Power Circuit
+12.0V
Data
format
Bit
selection
L-DIM
Enable
HTPDN
LOCKN
SDA
Vby1 Rx +L/D
+ DGA + ODC
Block
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Product Specification
EPI (RGB)
Gate Driver Circuit
Control
Signals
Power Signals
EPI (RGB)
G2160
G
LC840EQD
Source Driver Circuit
S1 S3840
G1
TFT - LCD Panel
(3840 Ý RGB Ý 2160 pixels)
S1 S3840
Source Driver Circuit
VSYNC, SIN, SCLK, GND
+24.0V, GND, On/Off
ExtV
BR-B
LED Driver
Local Dimming
: 32 Block
Active Screen Size 84.04 inches(2134.62 mm) diagonal
Outline Dimension
1904.0(H) Ý 1096.0(V) X 15.5(B) /24.0 mm(D) (Typ.)
Pixel Pitch 0.4845 mm x 0.4845 mm
Pixel Format 3840 horiz. by 2160 vert. Pixels, RGB stripe arrangement
Color Depth 10bit(D), 1.06Billon colors
Luminance, W hite 350 cd/m
2
(Center 1point ,Typ.)
Viewing Angle (CR>10) Viewing angle free ( R/L 178 (Min.), U/D 178 (Min.))
Power Consumption
Total 398W (Typ.) [Logic= 18W,
LED Driver=380W (ExtVbr_B=100% )]
Weight 42.9 Kg (Typ.)
Display Mode Transmissive mode, Normally black
Surface Treatment Hard coating(3H), Anti-glare treatment of the front polarizer (Haze 10%)
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2. Absolute Maximum Ratings
The following items are maximum values which, if exceeded, may cause faulty operation or permanent damage
to the LCD module.
Table 1. ABSOLUTE MAXIMUM RATINGS
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Product Specification
G
LC840EQD
Parameter Symbol
Unit notes
Min Max
Value
LCD Circuit V
LCD -0.3 +14.0 VDC
Power Input Voltage
Driver V
ON/OFF V
BL -0.3 + 27.0 VDC
OFF / VON -0.3 +5.5 VDC
Driver Control Voltage
Brightness EXTVBR-B 0.0 +5.5 VDC
T-Con Option Selection Voltage VLOGIC -0.3 +4.0 VDC
Operating Temperature TOP 0+50
Storage Temperature T
Panel Front Temperature T
Operating Ambient Humidity H
Storage Humidity H
notes :1. Ambient temperature condition (Ta =
ST -20 +60
SUR -+68
OP 10 90 %RH
ST 10 90 %RH
25 ± 2 ¶C )
¶C
¶C
¶C
2. Temperature and relative humidity range are shown in the figure below.
Wet bulb temperature should be Max 39¶C, and no condensation of water.
3. Gravity mura can be guaranteed below 40¶C condition.
4. The maximum operating temperatures is based on the test condition that the surface temperature
of display area is less than or equal to 68¶C with LCD module alone in a temperature controlled chamber.
Thermal management should be considered in final product design to prevent the surface temperature of
display area from being over 68. The range of operating temperature may be degraded in case of
improper thermal management in final product design.
90%
1
2,3
4
2,3
60
60%
Wet Bulb
Temperature [
10
0
10 20 30 40 50 60 70 800-20
Dry Bulb Temperature [
¶C]
20
30
40
50
40%
Humidity [(%)RH]
10%
¶C]
Storage
Oper ati on
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3. Electrical Specifications
3-1. Electrical Characteristics
It requires two power inputs. One is employed to power for the LCD circuit. The other Is used for the LED
backlight and LED Driver circuit.
Table 2. ELECTRICAL CHARACTERISTICS
Parameter Symbol
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Product Specification
Value
Min Typ Max
G
LC840EQD
Unit notes
Circuit :
Power Input Voltage V
Power Input Current ILCD
Power Consumption P
Rush current I
LCD 10.8 12.0 13.2 VDC
- 1500 1950 mA 1
- 4400 5720 mA 2
LCD - 18.0 23.4 Watt 1
RUSH --8.0A3
notes : 1. The specified current and power consumption are under the V
condition, and mosaic pattern(8 x 6) is displayed and f
is the frame frequency.
V
2. The current is specified at the maximum current pattern.
3. The duration of rush current is about 2ms and rising time of power input is 0.5ms (min.).
4. Ripple voltage level is recommended under ·5% of typical voltage
White : 1023 Gray
Black : 0 Gray
=12.0V, Ta=25 ± 2¶C, fV=120Hz
LCD
Mosaic Pattern(8 x 6)
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Table 3. ELECTRICAL CHARACTERISTICS (Continue)
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Product Specification
G
LC840EQD
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[
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Notes :
1. Electrical characteristics are determined after the unit has been ‘ON’ and stable for approximately 60
minutes at 25·2¶C. The specified current and power consumption are under the typical supply Input voltage
24Vand V
BR (ExtVBR-B : 100%), it is total power consumption.
2. The life time (MTTF) is determined as the time which luminance of the LED is 50% compared to that of initial
value at the typical LED current (ExtVBR-B :100%) on condition of continuous operating in LCM state at
25·2¶C.
3. LGD recommend that the PWM freq. is synchronized with One time harmonic of V_sync signal of system.
Though PWM frequency is over 120Hz (max 252Hz), function of LED Driver is not affected.
4. The duration of rush current is about 200ms. This duration is applied to LED on time
5. Even though inrush current is over the specified value, there is no problem if I
2
T spec of fuse is satisfied.
6. Ext_PWM Signal have to input available duty range.
Between 99% and 100%
But
ExtVBR-B 0% and 100% is possible.
High
ExtVBR-B duty have to be avoided. ( 99% < ExtVBR-B < 100%)
Available duty range
Low
0% 1%
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99% 100%Ext_PWM Input Duty
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Product Specification
3-2. Interface Connections
This LCD module employs theree kinds of interface connection, 5-pin connector, 51-pin connector
and 41-pin connector are used for the module electronics and 14-pin,12-pin connector is used for the integral
backlight system.
3-2-1. LCD Module
- LCD Connector(CN1): SM05B-PASS-TB(manufactured by JST)
- Mating Connector : PAP-05V-S(JST) or compatible
Table 4-1. MODULE CONNECTOR(CN1) PIN CONFIGURATION
G
LC840EQD
No Symbol Description
1
2
3
4
5
GND Ground
GND Ground
VLCD Power Supply +12.0V
VLCD Power Supply +12.0V
VLCD Power Supply +12.0V
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Product Specification
- LCD Connector(CN1): FI-RE51S-HF(manufactured by JAE)
- Mating Connector : FI-R51HL(JAE) or compatible
Table 4-2. MODULE CONNECTOR(CN2) PIN CONFIGURATION
No Symbol Description No Symbol Description
1
NC (Reserved)
2
NC (Reserved) Power Supply +12.0V (reserved)
3
NC (Reserved) Power Supply +12.0V (reserved) 29 Rx0p V-by-One HS Data Lane 0
4
NC (Reserved) Power Supply +12.0V (reserved) 30 GND Ground
5
NC (Reserved) Power Supply +12.0V (reserved)
6
NC (Reserved) Power Supply +12.0V (reserved)
7
NC (Reserved) Power Supply +12.0V (reserved) 33 GND Ground
8 NC (Reserved) Power Supply +12.0V (reserved) 34 Rx2n V-by-One HS Data Lane 2
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
NC NO CONNECTION (notes 4)
GND Ground
GND Ground 37 Rx3n V-by-One HS Data Lane 3
GND Ground 38 Rx3p V-by-One HS Data Lane 3
GND Ground
GND Ground
Data format 0
Data format 1
NC NO CONNECTION (notes 4)
NC NO CONNECTION (notes 4)
NC NO CONNECTION (notes 4)
NC NO CONNECTION (notes 4)
Bit SEL
L-DIM Enable
GND Ground (notes 7)
GND Ground
HTPDN Hot plug detect
LOCKN Lock detect
Power Supply +12.0V (reserved)
Input Data Format [1:0] :
‘00’=Mode1, ’01’=Mode2,
’10’=Mode3, ’11’=Mode4
H or NC= 10bit(D) , L = 8bit
H’ = Enable , ‘L’ or NC = Disable
27
28
31
32
35
36
39
40
41
42
43
44
45
46
47
48
49
50
51
-- -
GND Ground
Rx0n V-by-One HS Data Lane 0
Rx1n V-by-One HS Data Lane 1
Rx1p V-by-One HS Data Lane 1
Rx2p V-by-One HS Data Lane 2
GND Ground
GND Ground
Rx4n V-by-One HS Data Lane 4
Rx4p V-by-One HS Data Lane 4
GND Ground
Rx5n V-by-One HS Data Lane 5
Rx5p V-by-One HS Data Lane 5
GND Ground
Rx6n V-by-One HS Data Lane 6
Rx6p V-by-One HS Data Lane 6
GND Ground
Rx7n V-by-One HS Data Lane 7
Rx7p V-by-One HS Data Lane 7
GND Ground
G
LC840EQD
notes
1. All GND (ground) pins should be connected together to the LCD module’s metal frame.
2. #1~#8 NC (No connection ) : These pins are used for back up power source, V
LCD (power input) .
These pins are should be connected together.
3. All Input levels of V-by-One signals are based on the V-by-One HS Standard Version 1.3.
4. #9 & #17~#20 NC (No Connection) : These pins are used only for LGD (Do not connect)
5. Specific pin (#22) is used for Local Dimming function of the LCD module.
If not used, these pins are no connection. (Please see the Appendix IV-2 for more information.)
6. About spcific pin (#15,#16) , Please see the Appendix VII.
7. Specific pin No. #23 is used for “No signal detection” of system signal interface.
It should be GND for NSB (No Signal Black) while the system interface signal is not.
If this pin is “H” or “NC”, LCD Module displays AGP (Auto Generation Pattern).
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Product Specification
-LCD Connector (CN2) : FI-RE41S-HF (manufactured by JAE)
- Mating Connector : FI-RE41HL or compatible
Table 4-3. MODULE CONNECTOR(CN3) PIN CONFIGURATION
No Symbol Description No Symbol Description
1
GND Ground
2
Rx8n V-by-One HS Data Lane 8
3
Rx8p V-by-One HS Data Lane 8
4
GND Ground
5
Rx9n V-by-One HS Data Lane 9
6 Rx9p V-by-One HS Data Lane 9 27 NC NO CONNECTION
7 GND Ground 28 NC NO CONNECTION
8 Rx10n V-by-One HS Data Lane 10 29 NC
9 Rx10p V-by-One HS Data Lane 10 30 NC NO CONNECTION
10 GND Ground 31 NC NO CONNECTION
11 Rx11n V-by-One HS Data Lane 11 32 NC NO CONNECTION
12 Rx11p V-by-One HS Data Lane 11 33 NC NO CONNECTION
13 GND Ground 34 NC NO CONNECTION
14 Rx12n V-by-One HS Data Lane 12 35 NC NO CONNECTION
15 Rx12p V-by-One HS Data Lane 12 36 NC NO CONNECTION
16 GND Ground 37 NC NO CONNECTION
17 Rx13n V-by-One HS Data Lane 13 38 NC NO CONNECTION
18 Rx13p V-by-One HS Data Lane 13 39 NC NO CONNECTION
19 GND Ground 40 NC NO CONNECTION
20 Rx14n V-by-One HS Data Lane 14 41 NC NO CONNECTION
21 Rx14p V-by-One HS Data Lane 14 -
22
GND Ground
23
Rx15n V-by-One HS Data Lane 15
24
Rx15p V-by-One HS Data Lane 15
25
GND Ground
26
NC NO CONNECTION
NO CONNECTION
G
LC840EQD
notes : 1. All GND (ground) pins should be connected together to the LCD module’s metal frame.
2. #26~#41 NC (No Connection) : These pins are used only for LGD (Do not connect)
CN1
#1
#5
CN1
#1 #5
CN2 CN3
#1 #51 #1 #41
CN2 CN3
#1 #51
#1 #41
Rear view of LCM
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Product Specification
3-2-2. Backlight Module
Master
-LED Driver Connector
: 20022WR - H14B2(Yeonho) , 20022WR-H12B2(Yeonho)
- Mating Connector
: 20022HS-H14B2(Yeonho),20022HS-H12B2(Yeonho) or Compatible
Table 5-1. LED DRIVER CONNECTOR PIN CONFIGURATION
G
LC840EQD
Pin No Symbol
1 VBL Power Supply +24.0V Power Supply +24.0V
2 VBL Power Supply +24.0V Power Supply +24.0V
3 VBL Power Supply +24.0V Power Supply +24.0V
4 VBL Power Supply +24.0V Power Supply +24.0V
5 VBL Power Supply +24.0V Power Supply +24.0V
6
7
8
9
10
11
12
13 NC
14 EXTVBR_B
GND
GND
GND
GND
GND
Status
VON/OFF
Backlight Ground Backlight Ground
Backlight Ground Backlight Ground
Backlight Ground Backlight Ground
Backlight Ground Backlight Ground
Backlight Ground Backlight Ground
Backlight Status
Backlight ON/OFF control
Don’t care
External PWM
Description
(CN_A1/CN_A2)
Description
(CN_A2/CN_B2)
Don’t care 2
Don’t care
notes : 1. GND should be connected to the LCD module’s metal frame.
2. Normal : Low (under 0.7V) / Abnormal : Open
3. High : on duty / Low : off duty, Pin#14 can be opened. ( if Pin #14 is open , EXTVBR-B is 100% )
4. Each impedance of pin #12 and 14 is over 50 [KΩ] .
Note
1
3
ଝ Rear view of LCM
Board B
ଝ Status
112
114
1
12
…
CN_B2 CN_B1
Board A
112
114
1
14
…
CN_A2 CN_A1
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3-3. Signal Timing Specifications
Table 6 shows the signal timing required at the input of the LVDS transmitter. All of the interface signal
timings should be satisfied with the following specification for normal operation.
Table 6. TIMING TABLE (DE Only Mode)
ITEM Symbol Min Typ Max Unit Note
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Product Specification
G
LC840EQD
Horizontal
Vertical
Frequency
Display
Period
Blank
Total
Display
Period
Blank
Total
ITEM Symbol Min Typ Max Unit Note
DCLK
Horizontal
Vertical
tHV
tHB
tHP
tVV
tVB
tVP
fCLK
fH
fV
240
25
265
2160
40
(456)
2200
(2616)
67
244
108
(95)
240
35
275
2160
90
(540)
2250
(2700)
74.25
270
120
(100)
240
60
300
2160
172
(600)
2332
(2760)
78.00
280
122
(104)
tCLK
tCLK
tCLK
Lines
Lines
Lines
MHz
KHz
Hz
3840/16
1
1
1188/16
1
2
NTSC
(PAL)
notes: 1. The input of HSYNC & VSYNC signal does not have an effect on normal operation (DE Only Mode).
If you use spread spectrum of EMI, add some additional clock to minimum value for clock margin.
2. The performance of the electro-optical characteristics may be influenced by variance of the vertical
refresh rate and the horizontal frequency
Timing should be set based on clock frequency.
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ื
ื
ื ื
ื
ื
3-4. V by One input signal Characteristics
3-4-1. V by One Input Signal Timing Diagram
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Product Specification
1UI = 1/(Serial data rate)
G
LC840EQD
Y
X
X=0 UI X=1 UI
Table7. Eye Mask Specification
X[UI] Note Y[mV] Note
A 0.25 (max) 2 0 -
B 0.3 (max) 2 50 3
C 0.7(min) 3 50 3
D 0.75(min) 3 0 -
B
A
ื
FE
C
D
Y=0mV
E 0.7(min) 3 l -50 l 3
F 0.3(max) 2 l -50 l 3
notes 1. All Input levels of V by One signals are based on the V by One HS Standard Ver. 1.3
2. This is allowable maximum value.
3. This is allowable minimum value.
4. The eye diagram is measured by the oscilloscope and receiver CDR characteristic must be
emulated.
- PLL bandwidth : 11 Mhz
- Damping Factor : 1
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