The LC600EUD is a Color Active Matrix Liquid Crystal Display with an integral Light Emitting Diode (LED)
ba ck li g ht s ys te m. T he m a tr ix e mp l oys a - Si Th in F ilm T ran s is to r as t he ac ti v e e lem en t .
It is a transmissive display type which is operating in the normally black mode. It has a 59.58 inch diagonally
measured active display area with WUXGA resolution (1080 vertical by 1920 horizontal pixel array).
Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arrayed in vertical stripes.
Gray scale or the luminance of the sub-pixel color is determined with a 10-bit gray scale signal for each dot.
Therefore, it can present a palette of more than 1.06Bilion colors.
It has been designed to apply the 10-bit 4-port LVDS interface.
It is intended to support LCD TV, PCTV where high brightness, super wide viewing angle, high color gamut,
high color depth and fast response time are important.
Mini-LVDS(RGB)
Control
Signals
Power Signals
Source Driver Circuit
S1S1920
G1
TFT - LCD Panel
(1920 × RGB × 1080 pixels)
G1080
LVDS
2Port
LVDS
2Port
LVDS
Select
Bit
Select
+12.0V
CN2
(41pin)
CN1
(51pin)
LVDS 3,4
LVDS 1,2
Option
signal
I2C
EEPROM
SCL
SDA
Timing Controller
LVDS Rx + L/Dim + DGA + ODC
Integrated
Power Circuit
Block
SIN, SCLK, V_Sync
+24.0V, GND, On/Off
ExtVBR-B
LED Driver
V : 8BlockH : 2Block
Local Dimming :
General Features
Active Screen Size59.58 inch (1513.397mm) diagonal
Outline Dimension1346.0(H) x 769.3(V) x 11.9 (D)(Typ.)
Pixel Pitch687㎛ x 687㎛ x RGB
Pixel Format1920 horiz. by 1080 vert. Pixels, RGB stripe arrangement
Surface TreatmentHard coating(2H), Anti-glare treatment of the front polarizer (Haze < 1%)
Total 145.04(TBD) W (Typ.) [Logic= 5.04(TBD)W, LED Backlight= 140(TBD)W
(IF=125mA)]
16 Block
Ver. 0.1
4 / 46
LC600EUD
Product Specification
2. Absolute Maximum Ratings
The following items are maximum values which, if exceeded, may cause faulty operation or permanent damage
to the LCD module.
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter`Symbol
Power Input Voltage
Driver Control Voltage
Operating TemperatureTOP0+50°C
Storage TemperatureTST-20+60°C
Panel Front Temperature TSUR-+68°C4
Operating Ambient HumidityHOP1090%RH
Storage HumidityHST1090%RH
Note
1. Ambient temperature condition (Ta = 25 ± 2 °C )
LCD CircuitVLCD-0.3+14.0VDC
DriverVBL-0.3+ 27.0VDC
ON/OFFVOFF / VON-0.3+5.5VDC
BrightnessEXTVBR-B0.0+5.5VDC
Value
UnitNote
MinMax
2. Temperature and relative humidity range are shown in the figure below.
Wet bulb temperature should be Max 39°C, and no condensation of water.
3. Gravity mura can be guaranteed below 40°C condition.
4. The maximum operating temperatures is based on the test condition that the surface temperature
of display area is less than or equal to 68°C with LCD module alone in a temperature controlled chamber.
Thermal management should be considered in final product design to prevent the surface temperature of
display area from being over 68℃. The range of operating temperature may be degraded in case of
improper thermal management in final product design.
90%
1
2,3
2,3
Ver. 0.1
Wet Bulb
Temperature [°C]
20
10
0
10203040506070800-20
Dry Bulb Temperature [°C]
30
40
50
60
60%
40%
10%
Storage
Operation
Humidity [(%)RH]
5 / 46
LC600EUD
Product Specification
3. Electrical Specifications
3-1. Electrical Characteristics
It requires two power inputs. One is employed to power for the LCD circuit. The other Is used for the LED
backlight.
Table 2. ELECTRICAL CHARACTERISTICS
ParameterSymbol
Circuit :
Power Input VoltageVLCD10.812.013.2VDC
Power Input CurrentILCD
Power ConsumptionPLCD-5.046.55Watt1
Rush currentIRUSH--5.0A3
Note
1. The specified current and power consumption are under the V
(TBD)
Value
MinTypMax
-420546mA1
-450585mA2
UnitNote
=12.0V, Ta=25 ± 2°C, fV=120Hz
LCD
condition, and mosaic pattern(8 x 6) is displayed and fVis the frame frequency.
2. The current is specified at the maximum current pattern.
3. The duration of rush current is about 2ms and rising time of power input is 0.5ms (min.).
4. Ripple voltage level is recommended under ±5% of typical voltage
White : 1023 Gray
Black : 0 Gray
Ver. 0.1
Mosaic Pattern(8 x 6)
6 / 46
Product Specification
Table 3. ELECTRICAL CHARACTERISTICS (Continue)
LC600EUD
ParameterSymbol
LED Driver :
Power Supply Input VoltageVBL22.824.025.2Vdc1
Power Supply Input Current IBL
Power Supply Input Current (In-Rush)In-rush
Power ConsumptionPBL
On/Off
Brightness AdjustExtVBR-B1-100%On Duty , 6
Input Voltage for
Control System
Signals
LED :
Life Time30,000Hrs2
PWM Frequency for
NTSC & PAL
Pulse Duty Level
(PWM)
VSYNC, SIN, SCLK,
Reverse
(Local Dimming)
OnV on2.5-5.0Vdc
OffV off-0.30.00.7Vdc
PAL100Hz3
NTSC120Hz3
High Level2.5-5.0
Low Level0.0-0.7
High Level2.73.33.6
Low Level-0.30.00.4
MinTypMax
Values
5.9(TBD)
-
--8.2(TBD) A peak
-
140.0
(TBD)
6.5(TBD)
155.6
(TBD)
UnitNotes
A rms1
W1
Vdc
Vdc
Vdc
Vdc
VBL = 22.8V
Ext VBR-B = 100%, 4
HIGH : on duty
LOW : off duty
Notes :
1. Electrical characteristics are determined after the unit has been ‘ON’ and stable for approximately 60
minutes at 25±2°C. The specified current and power consumption are under the typical supply Input voltage
24Vand VBR (ExtVBR-B : 100%), it is total power consumption.
2. The life time (MTTF) is determined as the time which luminance of the LED is 50% compared to that of initial
value at the typical LED current (ExtVBR-B :100%) on condition of continuous operating in LCM state at
25±2°C.
3. LGD recommend that the PWM freq. is synchronized with One time harmonic of V_sync signal of system.
Though PWM frequency is over 120Hz (max 252Hz), function of LED Driver is not affected.
4. The duration of rush current is about
200ms. This duration is applied to LED on time.
5. Even though inrush current is over the specified value, there is no problem if I2T spec of fuse is satisfied.
6. Ext_PWM Signal have to input available duty range.
Between 99% and 100% ExtVBR-B duty have to be avoided. ( 99% < ExtVBR-B < 100%)
But ExtVBR-B 0% and 100% is possible.
High
Available duty range
Low
0%
1%
Ver. 0.1
99% 100%Ext_PWM Input Duty
7 / 46
LC600EUD
Product Specification
3-2. Interface Connections
This LCD module employs two kinds of interface connection, 51-pin connector and 41-pin connector are used
for the module electronics and Two 8-pin connectors are used for the integral backlight system.
3-2-1. LCD Module
- LCD Connector(CN1): FI-RE51S-HF(manufactured by JAE) or GT05P-51S-H38(manufactured by LSM)
or IS050-C51B-C39(manufactured by UJU)
FIRST LVDS Receiver Signal (E-)
FIRST LVDS Receiver Signal (E+)
No Connection or Ground
27
Bit Select
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
---
R2AN
R2AP
R2BN
R2BP
R2CN
R2CP
GND
R2CLKN
R2CLKP
GND
R2DN
R2DP
R2EN
R2EP
NC or GND
NC or GND
GNDGround (Note 6)
GNDGround
GNDGround
NCNo connection
VLCDPower Supply +12.0V
VLCDPower Supply +12.0V
VLCDPower Supply +12.0V
VLCDPower Supply +12.0V
‘H’ or NC= 10bit(D) , ‘L’ = 8bit
SECOND LVDS Receiver Signal (A-)
SECOND LVDS Receiver Signal (A+)
SECOND LVDS Receiver Signal (B-)
SECOND LVDS Receiver Signal (B+)
SECOND LVDS Receiver Signal (C-)
SECOND LVDS Receiver Signal (C+)
Ground
SECOND LVDS Receiver Clock Signal(-)
SECOND LVDS Receiver Clock Signal(+)
Ground
SECOND LVDS Receiver Signal (D-)
SECOND LVDS Receiver Signal (D+)
SECOND LVDS Receiver Signal (E-)
SECOND LVDS Receiver Signal (E+)
No Connection or Ground
No Connection or Ground
Note
Ver. 0.1
1. All GND (ground) pins should be connected together to the LCD module’s metal frame.
2. All VLCD (power input) pins should be connected together.
3. All Input levels of LVDS signals are based on the EIA 644 Standard.
4. #1~#6 & #8~#10 NC (No Connection): These pins are used only for LGD (Do not connect)
5. LVDS pin (pin No. #24,25,40,41) are used for 10Bit(D) of the LCD module.
If used for 8Bit(R), these pins are no connection.
6. Specific pin No. #44 is used for “No signal detection” of system signal interface.
It should be GND for NSB (No Signal Black) while the system interface signal is not.
If this pin is “H”, LCD Module displays AGP (Auto Generation Pattern).
8 / 46
LC600EUD
Product Specification
- LCD Connector(CN2): FI-RE41S-HF(manufactured by JAE) or GT05P-41S-H38(manufactured by LSM)
or IS050-C41B-C39(manufactured by UJU)
Note : 1. All GND (ground) pins should be connected together to the LCD module’s metal frame.
2. LVDS pin (pin No. #22,23,38,39) are used for 10Bit(D) of the LCD module.
If used for 8Bit(R), these pins are no connection.
CN1 CN2
#1
CN1CN2
#1#51
#51#1#41
#1#41
Rear view of LCM
Ver. 0.1
9 / 46
Product Specification
3-2-2. Backlight Module
Master
-LED Driver Connector
:
20022WR - H14B2(Yeonho)
- Mating Connector
: 20022HS - 14B2 or compatible
Table 5-1. LED DRIVER CONNECTOR PIN CONFIGURATION
Pin NoSymbolDescriptionNote
1VBLPower Supply +24.0V
2VBLPower Supply +24.0V
3VBLPower Supply +24.0V
4VBLPower Supply +24.0V
5VBLPower Supply +24.0V
6GNDBacklight Ground
7GNDBacklight Ground
8GNDBacklight Ground
9GNDBacklight Ground
10GNDBacklight Ground
LC600EUD
1
11Status
12VON/OFF
13NC
14EXTVBR-B
Back Light Status
Backlight ON/OFF control
Don’t care
External PWM
Notes :1. GND should be connected to the LCD module’s metal frame.
2. Normal : Low (under 0.7V) / Abnormal :Open
3. High : on duty / Low : off duty, Pin#14 can be opened. ( if Pin #14 is open , EXTVBR-B is 100% )
4. Each impedance of pin #12 and #14 is over
TBD [KΩ] .
◆ Rear view of LCM
PCB
1
14
…
1
14
…
<Master>
2
3
◆ Status
Ver. 0.1
10 / 46
3-2-3. Local Dimming Interface
LC600EUD
Product Specification
- Local Dimming Interface Connector : 12507WR-
H08L(YEONHO Elec.)
- Mating Connector: 12507HS-08L(YEONHO Elec.)
Table 5-2. LOCAL DIMMING INTERFACE CONNECTOR PIN CONFIGULATION
Pin NoSymbolDescriptionNote
1VSYNCVertical Sync signal
2N.CNo Connection
3N.CNo Connection
4SINLocal Dimming Serial Data (SPI)
5GNDBacklight Ground1
6SCLKLocal Dim Serial Clock (SPI)
7
8N.CNo Connection2
N.CNo Connection2
Notes : 1. GND should be connected to the LCD module’s metal frame.
2.This pin is used only for LGD (Do not connect)
SPI
Command 7 Bit
LowNon-reverse mode
HighReverse mode
◆ Rear view of LCM
8
1
Ver. 0.1
…
Result
PCB
…
11 / 46
LC600EUD
Product Specification
3-3. Signal Timing Specifications
Table 6 shows the signal timing required at the input of the LVDS transmitter. All of the interface signal
timings should be satisfied with the following specification for normal operation.
Table 6. TIMING TABLE (DE Only Mode)
ITEMSymbolMinTypMaxUnitNote
Horizontal
Vertical
Frequency
Display
Period
BlanktHB4070200tCLK1
TotaltHP520550680tCLK
Display
Period
BlanktVB
TotaltVP
ITEMSymbolMinTypMaxUnitNote
DCLKfCLK66.9774.2578.00MHz
HorizontalfH121.8135140KHz2
VerticalfV
tHV480480480tCLK1920 / 4
tVV108010801080Lines
20
(228)
1100
(1308)
108
(95)
45
(270)
1125
(1350)
120
(100)
86
(300)
1166
(1380)
122
(104)
Lines1
Lines
Hz
NTSC
(PAL)
2
Note: 1. The input of HSYNC & VSYNC signal does not have an effect on normal operation (DE Only Mode).
If you use spread spectrum of EMI, add some additional clock to minimum value for clock margin.
2. The performance of the electro-optical characteristics may be influenced by variance of the vertical
refresh rate and the horizontal frequency
※ Timing should be set based on clock frequency.
Ver. 0.1
12 / 46
3-4. LVDS Signal Specification
3-4-1. LVDS Input Signal Timing Diagram
LC600EUD
Product Specification
DCLK
First data
Second data
Third data
Forth data
DE(Data Enable)
tCLK
0.5 VDD
Invalid data
Invalid data
Invalid data
Invalid data
DE, Data
Valid data
Pixel 0
Valid data
Pixel 1
Valid data
Pixel 2
Valid data
Pixel 3
Pixel 4
Pixel 5
Pixel 6
Pixel 7
0.7VDD
0.3VDD
Invalid data
Invalid data
Invalid data
Invalid data
DE(Data Enable)
Ver. 0.1
* tHB = tHFP + tWH +tHBP
* tVB = tVFP + tWV +tVBP
11080
tVV
tVP
13 / 46
3-4-2. LVDS Input Signal Characteristics
1) DC Specification
LVDS -
LVDS +
LC600EUD
Product Specification
# VCM= {(LVDS +) + ( LVDS - )} /2
0V
V
CM
V
IN _ MAXVIN _MIN
DescriptionSymbolMinMaxUnitNote
LVDS Common mode VoltageV
LVDS Input Voltage RangeV
CM
IN
1.01.5V-
0.71.8V-
Change in common mode VoltageΔVCM-250mV-
2) AC Specification
T
clk
LVDS Clock
A
LVDS Data
(F
= 1 /T
)
clk
A
LVDS 1’st Clock
LVDS 2nd/ 3rd/ 4thClock
tSKEW
t
SKEW_mintSKEW_max
tSKEW
clk
T
clk
80%
20%
t
RF
DescriptionSymbolMinMaxUnitNote
LVDS Differential Voltage
LVDS Clock to Data Skewt
LVDS Clock/DATA Rising/Falling timet
Effective time of LVDSt
LVDS Clock to Clock Skew (Even to Odd)t
Note
1. All Input levels of LVDS signals are based on the EIA 644 Standard.
2. If tRFisn’t enough, t
should be meet the range.
eff
3. LVDS Differential Voltage is defined within t
Ver. 0.1
V
TH
V
TL
SKEW
RF
eff
SKEW_EO
100600mV
Tested with Differential Probe
-600-100mV
-|(0.25*T
260|(0.3*T
)/7|ps-
clk
)/7|ps2
clk
|±360|-ps-
-|1/7* T
eff
|ps-
clk
3
14 / 46
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