2. Temperature and relative humidity range are shown in the figure below. Wet bulb temperature should be Max 39°C, and no condensation of water.
3. Gravity mura can be guaranteed below 40°C condition.
4. The maximum operating temperatures is based on the test condition that the surface temperatureof display area is less than or equal to 68°C with LCD module alone in a temperature controlled chamber.
Thermal management should be considered in final product design to prevent the surface temperature of
display area from being over 68℃. The range of operating temperature may be degraded in case ofimproper thermal management in final product design.
It requires two power inputs. One is employed to power for the LCD circuit. The other Is used for the LED
backlight and LED Driver circuit.
Table 2. ELECTRICAL CHARACTERISTICS
ParameterSymbol
MinTypMax
Circuit :
Power Input VoltageVLCD10.812.013.2VDC
Value
UnitNote
Power Input CurrentILCD
Power ConsumptionPLCD6.888.94Watt1
Rush currentIRUSH--5.0A3
ExtV
BR-B
Brightness Adjust for Back Light
ExtV
Frequency
Pulse Duty Level
(PWM)
Note
1. The specified current and power consumption are under the V
High Level
Low Level
BR-B
-573745mA1
-8401092mA2
5-100%1-100%
4050/6080Hz
2.5-3.6Vdc0-0.8Vdc
=12.0V, Ta=25 2°C, fV=60Hz
LCD
HIGH : on duty
LOW : off duty
condition, and mosaic pattern(8 x 6) is displayed and fV is the frame frequency.
2. The current is specified at the maximum current pattern.
3. The duration of rush current is about 2ms and rising time of power input is 0.5ms (min.).
4. ExtVAfter Driver ON signal is applied, ExtV After that, ExtV
signal have to input available duty range and sequence.
BR-B
should be sustained from 5% to 100% more than 500ms.
BR-B
1% and 100% is possible
BR-B
For more information, please see 3-6-2. Sequence for LED Driver.
5. Ripple voltage level is recommended under ±5% of typical voltage
On Duty
4
Ver. 1.0
White : 255 Gray
Black : 0 Gray
Mosaic Pattern(8 x 6)
5 /35
Product Specification
Table 3. ELECTRICAL CHARACTERISTICS (Continue)
LC550EUN
ParameterSymbol
LED Driver :
Power Supply Input VoltageVBL22.824.025.2Vdc1
Power Supply Input Current IBL
Power Supply Input Current (In-Rush)In-rush--6.0A
Power ConsumptionPBL-
Input Voltage for
Control System
Signals
LED :
Life Time30,00050,000Hrs2
On/Off
OnV on2.5-5.0 Vdc
OffV off-0.30.00.7Vdc
MinTypMax
Values
-
3.36
80.7
3.62
86.9
UnitNotes
A1
VBL = 22.8V
ExtV
W1
BR-B
= 100%
3
Notes :
1. Electrical characteristics are determined after the unit has been ‘ON’ and stable for approximately 60minutes at 25±2°C. The specified current and power consumption are under the typical supply Input voltage
24Vand VBR (ExtVBR-B: 100%), it is total power consumption.
2. The life time (MTTF) is determined as the time which luminance of the LED is 50% compared to that of initial
value at the typical LED current (ExtVBR-B :100%) on condition of continuous operating in LCM state at
25±2°C.
3. The duration of rush current is about 200ms. This duration is applied to LED on time.
4. Even though inrush current is over the specified value, there is no problem if I2T spec of fuse is satisfied.
Ver. 1.0
6 /35
LC550EUN
Product Specification
3-2. Interface Connections
This LCD module employs two kinds of interface connection, 51-pin connector is used for the module
electronics and 14-pin connector is used for the integral backlight system.
3-2-1. LCD Module
- LCD Connector(CN1): FI-RE51S-HF(manufactured by JAE) or GT05P-51S-H38(manufactured by LSM) or
IS050-C51B-C39(manufactured by UJU)
No Connection (Note 4)
No Connection (Note 4)
No Connection (Note 4)
No Connection (Note 4)
No Connection (Note 4)No Connection (Note 4)
‘H’ =JEIDA , ‘L’ or NC = VESA External PWM (from System)
No Connection (Note 4)
GroundFIRST LVDS Receiver Signal (A-)
FIRST LVDS Receiver Signal (A+)FIRST LVDS Receiver Signal (B-)FIRST LVDS Receiver Signal (B+)FIRST LVDS Receiver Signal (C-)FIRST LVDS Receiver Signal (C+)
GroundFIRST LVDS Receiver Clock Signal(-)
FIRST LVDS Receiver Clock Signal(+)Ground
FIRST LVDS Receiver Signal (D-)
FIRST LVDS Receiver Signal (D+)
SECOND LVDS Receiver Signal (A-)
SECOND LVDS Receiver Signal (A+)
SECOND LVDS Receiver Signal (B-)
SECOND LVDS Receiver Signal (B+)SECOND LVDS Receiver Signal (C-)
SECOND LVDS Receiver Signal (C+)Ground
SECOND LVDS Receiver Clock Signal(-)SECOND LVDS Receiver Clock Signal(+)
GroundSECOND LVDS Receiver Signal (D-)
SECOND LVDS Receiver Signal (D+)
No Connection or GroundNo Connection or Ground
Note
Ver. 1.0
1. All GND(ground) pins should be connected together to the LCD module’s metal frame.
2. All VLCD (power input) pins should be connected together.
3. All Input levels of LVDS signals are based on the EIA 644 Standard.
4. #1~#6 & #9 NC (No Connection): These pins are used only for LGD (Do not connect)
5. Specific pins(pin No. #10) are used for OPC function of the LCD module.
If not used, these pins are no connection. (Please see the Appendix VI for more information.)
6. Specific pin No. #44 is used for “No signal detection” of system signal interface.
It should be GND for NSB(No Signal Black) during the system interface signal is not.
If this pin is “H”, LCD Module displays AGP(Auto Generation Pattern).
Notes :1. GND should be connected to the LCD module’s metal frame.
2. Normal : Low (under 0.7V) / Abnormal : Open
3. Each impedance of pin #12 is over 50 [KΩ] .
◆ Rear view of LCM
1
Ver. 1.0
14
…
<Master>
◆ Status
PCB
1
14
…
8 /35
LC550EUN
Product Specification
3-3. Signal Timing Specifications
Table 6 shows the signal timing required at the input of the LVDS transmitter. All of the interface signal timings
should be satisfied with the following specification for normal operation.
Table 6. TIMING TABLE (DE Only Mode)
ITEMSymbolMinTypMaxUnitNote
Horizontal
Vertical
Frequency
Display
Period
BlanktHB100140240tCLK1
TotaltHP106011001200tCLK
Display
Period
BlanktVB
TotaltVP
ITEMSymbolMinTypMaxUnitNote
DCLKfCLK63.0074.2578.00MHz
HorizontalfH57.367.570KHz2
VerticalfV
tHV960960960tCLK1920 / 2
tVV108010801080Lines
20
(228)1100
(1308)
57
(47)
45
(270)
1125
(1350)
60
(50)
69
(300)1149
(1380)
63
(53)
Lines1
Lines
Hz
NTSC
(PAL)
2
Note: 1. The input of HSYNC & VSYNC signal does not have an effect on normal operation (DE Only Mode).
If you use spread spectrum of EMI, add some additional clock to minimum value for clock margin.
2. The performance of the electro-optical characteristics may be influenced by variance of the vertical
refresh rate and the horizontal frequency
※ Timing should be set based on clock frequency.
Ver. 1.0
9 /35
3-4. LVDS Signal Specification
3-4-1. LVDS Input Signal Timing Diagram
LC550EUN
Product Specification
DE, Data
DCLK
First data
Second data
0.7VDD
0.3VDD
tCLK
DE(Data Enable)
0.5 VDD
Invalid data
Invalid data
Valid data
Pixel 0,0
Valid data
Pixel 1,0
tHP
Pixel 2,0
Pixel 3,0
Invalid data
Invalid data
tHV
DE(Data Enable)
Ver. 1.0
11080
tVV
tVP
10 /35
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