LG Display LC550EUN-PEF1 Specification

Global LCD Panel Exchange Center

www.panelook.com

LC550EUN

Product Specification

SPECIFICATION

FOR

APPROVAL

()Preliminary Specification
() Final Specification

Title 55.0” WUXGA TFT LCD

BUYER

MODEL

APPROVED BY

/

/

SIGNATURE

DATE

SUPPLIER LG Display Co., Ltd.

*MODEL LC550EUN

SUFFIX PEF1 (RoHS Verified)

*When you obtain standard approval,

please use the above model name without suffix

APPROVED BY

S.H. Lee / Team Leader

REVIEWED BY

H.J. An / Project Leader

SIGNATURE

DATE

PREPARED BY

/

Please return 1 copy for your confirmation with

your signature and comments.

Ver. 1.2

J.S. Ham / Engineer

TV Product Development Dept.

LG Display Co., Ltd.

One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!

0/380/38

www.panelook.com

Global LCD Panel Exchange Center

6

RELIABILITY

25

9-3

ELECTROSTATIC DISCHARGE CONTROL

29

www.panelook.com

LC550EUN

Product Specification

CONTENTS

Number ITEM

COVER

CONTENTS

RECORD OF REVISIONS

1 GENERAL DESCRIPTION

2 ABSOLUTE MAXIMUM RATINGS

3 ELECTRICAL SPECIFICATIONS

3-1 ELECTRICAL CHARACTERISTICS

3-2 INTERFACE CONNECTIONS

3-3 SIGNAL TIMING SPECIFICATIONS

3-4 SIGNAL TIMING WAVEFORMS

3-5 COLOR DATA REFERENCE

3-6 POWER SEQUENCE

4 OPTICAL SPECIFICATIONS

5 MECHANICAL CHARACTERISTICS

Page

0

1

2

3

4

5

5

7

9

10

13

14

16

22

7 INTERNATIONAL STANDARDS

7-1 SAFETY

7-2 EMC

7-3 ENVIRONMENT

8 PACKING

8-1 DESIGNATION OF LOT MARK

8-2 PACKING FORM

9 PRECAUTIONS

9-1 MOUNTING PRECAUTIONS

9-2 OPERATING PRECAUTIONS

9-4 PRECAUTIONS FOR STRONG LIGHT EXPOSURE

9-5 STORAGE

9-6 OPERATING GONDITION GUIDE

Ver. 1.2

26

26

26

26

27

27

27

28

28

28

29

29

29

1/381/38

One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!

www.panelook.com

Global LCD Panel Exchange Center

Revision No. Revision Date Page Description

0.1 Dec. 09. 2011 - Preliminary Specification (First Draft)

1.0 Mar. 02. 2012 CAS Version 1.0 Release

1.1 Mar. 06. 2012 7 Pin Map adjustment

1.2 Mar. 28. 2012 6 ELECTRICAL CHARACTERISTICS update

www.panelook.com

LC550EUN

Product Specification

RECORD OF REVISIONS

Ver. 1.2

One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!

2/382/38

www.panelook.com

Global LCD Panel Exchange Center

Itisintended

to

support

LCD

TV,PCTV

where

high

brightness

super

wide

viewing

angle

high

color

gamut

Timing Controller

1. General Description

The LC550EUN is a Color Active Matrix Liquid Crystal Display with an integral Light Emitting Diode (LED)
backlight system. The matrix employs a-Si Thin Film Transistor as the active element.
It is a transmissive display type which is operating in the normally black mode. It has a 54.64 inch diagonally
measured active display area with WUXGA resolution (1080 vertical by 1920 horizontal pixel array).
Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arrayed in vertical stripes.
Gray scale or the luminance of the sub-pixel color is determined with a 8-bit gray scale signal for each dot.
Therefore, it can present a palette of more than 16.7Milion colors.
It has been designed to apply the 8-bit 2-port LVDS interface.

high color depth and fast response time are important.

www.panelook.com

Product Specification

LC550EUN

,

,

,

LVDS

2Port

LVDS
Select

OPC
Enable

ExtV

BR-B

+12.0V

PWM_OUT

1~3

CN1

(51pin)

CN2

(4 pin)

LVDS 1,2

Option
signal

I2C

EEPROM

SCL

LVDS Rx + OPC + DGA

Power Circuit

SDA

Integrated

Block

EPI(RGB)

Control
Signals

Power Signals

Source Driver Circuit

S1 S1920

G1

TFT - LCD Panel

(1920 Ý RGB Ý 1080 pixels)

[Gate In Panel]

G1080

Scanning

PWM_OUT

1~3

+24.0V, GND, On/Off

LED Driver

Block 1

General Features

Active Screen Size 54.64 inches(1387.80mm) diagonal

Outline Dimension

Pixel Pitch 0.630 mm x 0.630 mm

Pixel Format 1920 horiz. by 1080 vert. Pixels, RGB stripe arrangement

Color Depth 8bit, 16.7 Million colors

Luminance, White 360 cd/m

Viewing Angle (CR>10) Viewing angle free ( R/L 178 (Min.), U/D 178 (Min.))

1244.6(H) ϧ 711.4(V) ϧ 9.6(B) / 23.2(D) mm (Typ.)

2

(Center 1point ,Typ.)

Scanning

Block 2

Scanning

Block 3

Power Consumption Total 73.9W (Typ.) [Logic= 7.3W, LED Driver=66.6W((ExtVbr_B=100% )]

Weight 17.5Kg (Typ.), 18.4 (Max.)
Display Mode Transmissive mode, Normally black
Surface Treatment Hard coating(2H), Anti-glare treatment of the front polarizer (Haze < 1%)

Ver. 1.2

One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!

3/383/38

www.panelook.com

Global LCD Panel Exchange Center

g

CD Circuit

C

0.3

0

C

C C cu t

C

03

0

C

g

gp

3. G

40

¶

C

diti

2. Absolute Maximum Ratings

The following items are maximum values which, if exceeded, may cause faulty operation or permanent damage
to the LCD module.

Table 1. ABSOLUTE MAXIMUM RATINGS

www.panelook.com

LC550EUN

Product Specification

Parameter Symbol

Power Input Voltage

Driver Control Voltage

T-Con Option Selection Voltage VLOGIC -0.3 +4.0 VDC

Operating Temperature TOP 0+50

Stora

e Temperature TST -20 +60

Panel Front Temperature TSUR -+68

Operating Ambient Humidity HOP 10 90 %RH

Storage Humidity H

Note

1. Ambient temperature condition (Ta = 25 r 2 ¶C )

L

Driver V

ON/OFF V

Brightness EXTVBR-B -0.3 +4.0 VDC

VL

D -

BL -0.3 + 27.0 VDC

OFF / VON -0.3 +5.5 VDC

ST 10 90 %RH

Value

Min Max

+14.

Unit Note

VD

¶C

¶C

¶C

2. Temperature and relative humidity range are shown in the figure below.
Wet bulb temperature should be Max 39¶C, and no condensation of water.

ravity mura can be guaranteed below

con

on.

4. The maximum operating temperatures is based on the test condition that the surface temperature

of display area is less than or equal to 68¶C with LCD module alone in a temperature controlled chamber.
Thermal management should be considered in final product design to prevent the surface temperature of
display area from being over 68ć. The range of operating temperature may be degraded in case of
improper thermal management in final product design.

90%

1

2,3

4

2,3

60

60%

Storage

Operation

40

50

40%

Humidity [(%)RH]

10%

¶C]

Wet Bulb
Temperature [

0

Ver. 1.2

One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!

¶C]

30

20

10

10 20 30 40 50 60 70 800-20

Dry Bulb Temperature [

4/384/38

www.panelook.com

Global LCD Panel Exchange Center

3-1. Electrical Ch

eter

Symbo

UnitNote

aa ete

Sy bo

Ut

ote

3. Electrical Specifications

aracteristics

It requires two power inputs. One is employed to power for the LCD circuit. The other Is used for the LED
backlight and LED Driver circuit.

Table 2. ELECTRICAL CHARACTERISTICS

Param

Circuit :

www.panelook.com

LC550EUN

Product Specification

Value

l

Min Typ Max

Power Input Voltage V

Power Input Current ILCD

Power Consumption PLCD - 7.3 9.13 Watt 1

Rush current IRUSH --5.0A 3

Brightness Adjust for Back Light

Pulse Duty Level
(PWM)

Note

1. The specified current and power consumption are under the V
condition, and mosaic pattern(8 x 6) is displayed and f

LCD 10.8 12.0 13.2 VDC

- 611 764 mA 1

- 925 1156 mA 2

ExtV

BR-B

ExtV

BR-B

Frequency
High Level

Low Level

5 - 100 %
1 - 100 %

40 50/60 80 Hz

2.5 - 3.6 Vdc
0 - 0.8 Vdc

=12.0V, Ta=25 r 2¶C, fV=60Hz

LCD

is the frame frequency.

V

On Duty

4

HIGH : on duty

LOW : off duty

2. The current is specified at the maximum current pattern.

3. The duration of rush current is about 2ms and rising time of power input is 0.5ms (min.).

4. ExtV
After Driver ON signal is applied, ExtV
After that, ExtV

signal have to input available duty range and sequence.

BR-B

1% and 100% is possible

BR-B

should be sustained from 5% to 100% more than 500ms.

BR-B

For more information, please see 3-6-2. Sequence for LED Driver.

5. Ripple voltage level is recommended under ·5% of typical voltage

White : 255 Gray
Black : 0 Gray

Mosaic Pattern(8 x 6)

Ver. 1.2

One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!

5/385/38

www.panelook.com

Global LCD Panel Exchange Center

Values

Power Supply Input Current (In

Rush)

In

rush

6.5AExtV

BR-B

100%

4. E

ified

I

2

T

Table 3. ELECTRICAL CHARACTERISTICS (Continue)

www.panelook.com

LC550EUN

Product Specification

Parameter Symbol

LED Driver :

Power Supply Input Voltage VBL 22.8 24.0 25.2 Vdc 1

Power Supply Input Current IBL

-

Power Consumption PBL -

Input Voltage for

Control System

Signals

LED :

Life Time 30,000 50,000 Hrs 2

On/Off

On V on 2.5 - 5.0 Vdc
Off V off -0.3 0.0 0.7 Vdc

-

Min Typ Max

-

--

2.77

66.6 70.7

2.94

Unit Notes

A1

VBL = 22.8V

=

3

W1

Notes :

1. Electrical characteristics are determined after the unit has been ‘ON’ and stable for approximately 60
minutes at 25·2¶C. The specified current and power consumption are under the typical supply Input voltage
24Vand V

BR (ExtVBR-B : 100%), it is total power consumption.

2. The life time (MTTF) is determined as the time which luminance of the LED is 50% compared to that of initial
value at the typical LED current (ExtVBR-B :100%) on condition of continuous operating in LCM state at
25·2¶C.

3. The duration of rush current is about 200ms. This duration is applied to LED on time.

ven though inrush current is over the spec

value, there is no problem if

spec of fuse is satisfied.

Ver. 1.2

One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!

6/386/38

www.panelook.com

Global LCD Panel Exchange Center

This LCD module employs two kinds of interface connection, 51

pin connector is used for the module

ExtVBR

B

GND

G

d

5. S

ifi

#10

)

OPC f

LCD

3-2. Interface Connections

electronics and 14-pin connector is used for the integral backlight system.

3-2-1. LCD Module

- LCD Connector(CN1): FI-R51S-HF(manufactured by JAE) or compatible

- Mating Connector : FI-R51HL(JAE) or compatible

Table 4. MODULE CONNECTOR(CN1) PIN CONFIGURATION

No Symbol Description No Symbol Description

1
2
3
4
5
6
7
8
9

10
11

12
13
14
15
16
17
18
19
20
21
22
23
24

25
26

NC
NC
NC
NC
NC
NC

LVDS Select

NC

OPC Enable ‘H’ = Enable , ‘L’ or NC = Disable

GND
R1AN
R1AP
R1BN
R1BP

R1CN
R1CP

GND

R1CLKN

R1CLKP

GND
R1DN
R1DP

NC No connection
NC No connection

NC or GND

No Connection (Note 4)
No Connection (Note 4)
No Connection (Note 4)
No Connection (Note 4)
No Connection (Note 4)
No Connection (Note 4)

ಫHಬ =JEIDA , ಫLಬ or NC = VESA

-

External PWM (from System)
No Connection (Note 4)

Ground

FIRST LVDS Receiver Signal (A-)
FIRST LVDS Receiver Signal (A+)
FIRST LVDS Receiver Signal (B-)
FIRST LVDS Receiver Signal (B+)
FIRST LVDS Receiver Signal (C-)
FIRST LVDS Receiver Signal (C+)

Ground

FIRST LVDS Receiver Clock Signal(-)
FIRST LVDS Receiver Clock Signal(+)

Ground
FIRST LVDS Receiver Signal (D-)
FIRST LVDS Receiver Signal (D+)

No Connection or Ground

www.panelook.com

Product Specification

-

27

28
29
30

31
32

33
34
35
36
37
38
39

40
41
42
43
44
45
46

47
48
49
50
51

-- -

R2AN
R2AP
R2BN

R2BP

R2CN

R2CP

R2CLKN

R2CLKP

R2DN

R2DP

NC or GND
NC or GND

VLCD Power Supply +12.0V
VLCD Power Supply +12.0V
VLCD Power Supply +12.0V

VLCD Power Supply +12.0V

NC No connection

SECOND LVDS Receiver Signal (A-)
SECOND LVDS Receiver Signal (A+)
SECOND LVDS Receiver Signal (B-)

SECOND LVDS Receiver Signal (B+)
SECOND LVDS Receiver Signal (C-)

SECOND LVDS Receiver Signal (C+)

roun

SECOND LVDS Receiver Clock Signal(-)
SECOND LVDS Receiver Clock Signal(+)

GND

NC No connection
NC No connection

GND Ground (Note 6)
GND Ground
GND Ground

NC No connection

Ground

SECOND LVDS Receiver Signal (D-)
SECOND LVDS Receiver Signal (D+)

No Connection or Ground
No Connection or Ground

LC550EUN

Note

1. All GND(ground) pins should be connected together to the LCD module’s metal frame.

2. All V

LCD (power input) pins should be connected together.

3. All Input levels of LVDS signals are based on the EIA 644 Standard.

4. #2~#6 & #9 NC (No Connection): These pins are used only for LGD (Do not connect)
pec

c pins(pin No.

are used for

unction of the

module.

If not used, these pins are no connection. (Please see the Appendix VI for more information.)

6. Specific pin No. #44 is used for “No signal detection” of system signal interface.

It should be GND for NSB(No Signal Black) during the system interface signal is not.
If this pin is “H”, LCD Module displays AGP(Auto Generation Pattern).

Ver. 1.2

One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!

7/387/38

www.panelook.com

Global LCD Panel Exchange Center

Pin No

Symbol

Description

Note

3.Each

impedance

of

pin#12isover50[K]

www.panelook.com

Product Specification

3-2-2. Backlight Module

Master

-LED Driver
: 20022WR - H14B2(Yeonho) or Compatible

- Mating Connector
: 20022HS - 14B2 or Compatible

Table 5-1. LED DRIVER CONNECTOR PIN CONFIGURATION

Connector

LC550EUN

1
2
3

4

5
6
7
8

9
10
11

12

13

14

VBL Power Supply +24.0V

VBL Power Supply +24.0V

VBL Power Supply +24.0V

VBL Power Supply +24.0V

VBL Power Supply +24.0V

GND

GND

GND

GND

GND

Status

ON/OFF

V

NC

NC

Backlight Ground

Backlight Ground

Backlight Ground

Backlight Ground

Backlight Ground

Back Light Status

Backlight ON/OFF control

Don’t care

Don’t care

Notes :1. GND should be connected to the LCD module’s metal frame.

2. Normal : Low (under 0.7V) / Abnormal : Open
.

1

2

3

ଝ Status

ଝ Rear view of LCM

PCB

1

14

…

1

14

…

<Master>

Ver. 1.2

One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!

8/388/38

www.panelook.com

Global LCD Panel Exchange Center

Horizontal

fH57.3

67.570KHz

2

If

EMI

dditi

3-3. Signal Timing Specifications

Table 6 shows the signal timing required at the input of the LVDS transmitter. All of the interface signal
timings should be satisfied with the following specification for normal operation.

Table 6. TIMING TABLE (DE Only Mode)

ITEM Symbol Min Typ Max Unit Note

www.panelook.com

LC550EUN

Product Specification

Horizontal

Vertical

Frequency

Display

Period

Blank tHB 100 140 240 tCLK 1

Total tHP 1060 1100 1200 tCLK

Display

Period

Blank t

Total tVP

ITEM Symbol Min Typ Max Unit Note

DCLK fCLK 63.00 74.25 78.00 MHz

Vertical fV

tHV 960 960 960 tCLK 1920 / 2

VV 1080 1080 1080 Lines

t

VB

20

(228)

1100

(1308)

57

(47)

45

(270)

1125

(1350)

60

(50)

69

(300)

1149

(1380)

63

(53)

Lines 1

Lines

Hz

NTSC
(PAL)

2

Note: 1. The input of HSYNC & VSYNC signal does not have an effect on normal operation (DE Only Mode).

you use spread spectrum of

, add some a

onal clock to minimum value for clock margin.

2. The performance of the electro-optical characteristics may be influenced by variance of the vertical
refresh rate and the horizontal frequency

Ć Timing should be set based on clock frequency.

Ver. 1.2

One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!

9/389/38

www.panelook.com

Global LCD Panel Exchange Center

0.5 VDD

Valid data

t

3-4. LVDS Signal Specification

3-4-1. LVDS Input Signal Timing Diagram

www.panelook.com

LC550EUN

Product Specification

DE, Data

DCLK

First data

Second data

0.7VDD

0.3VDD

tCLK

Invalid data

Invalid data

DE(Data Enable)

Valid data

Pixel 0,0

Pixel 1,0

tHP

Pixel 2,0

Pixel 3,0

Invalid data

Invalid data

tHV

DE(Data Enable)

Ver. 1.2

1 1080

VV

tVP

10 /3810 /38

One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!

www.panelook.com

Global LCD Panel Exchange Center

1) DC S

ificati

# V

{(LVDS+)

(

LVDS-)}/

2

2) AC Specification

A

3-4-2. LVDS Input Signal Characteristics

pec

on

LVDS -

LVDS +

www.panelook.com

LC550EUN

Product Specification

V

CM

=

0V

CM

+

V

IN _MAXVIN _MIN

Description Symbol Min Max Unit Note

LVDS Common mode Voltage V

LVDS Input Voltage Range V

CM

IN

1.0 1.5 V -

0.7 1.8 V -

Change in common mode Voltage VCM - 250 mV -

T

clk

LVDS Clock

A

LVDS Data

(F

= 1/T

)

clk

LVDS 1’st Clock

LVDS 2nd/ 3rd/ 4thClock

tSKEW

t

SKEW_mintSKEW_max

tSKEW

clk

T

clk

80%

20%

t

RF

Description Symbol Min Max Unit Note

V

LVDS Differential Voltage

LVDS Clock to Data Skew t

LVDS Clock/DATA Rising/Falling time t

TH

V

TL

SKEW

RF

Effective time of LVDS t

LVDS Clock to Clock Skew (Even to Odd) t

Note

1. All Input levels of LVDS signals are based on the EIA 644 Standard.

2. If t

isn’t enough, t

RF

should be meet the range.

eff

SKEW_EO

3. LVDS Differential Voltage is defined within t

Ver. 1.2

One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!

100 600 mV

-600 -100 mV

- |(0.20*T

260 |(0.3*T

|·360|

- |1/7* T

eff

)/7| ps -

clk

)/7| ps 2

clk

-ps -

|ps -

clk

Tested with Differential Probe

3

11 /40

11 /38

www.panelook.com