LG Display LC550EUD-SEF2 Specification
Global LCD Panel Exchange Center
www.panelook.com
LC550EUD
Product Specification
CONTENTS
Number ITEM
COVER
CONTENTS
RECORD OF REVISIONS 3
1 GENERAL DESCRIPTION
2 ABSOLUTE MAXIMUM RATINGS
3 ELECTRICAL SPECIFICATIONS
3-1 ELECTRICAL CHARACTERISTICS
3-2 INTERFACE CONNECTIONS
3-3 SIGNAL TIMING SPECIFICATIONS
3-4 SIGNAL TIMING WAVEFORMS 12
3-5 COLOR DATA REFERENCE
3-6 POWER SEQUENCE
4 OPTICAL SPECIFICATIONS
5 MECHANICAL CHARACTERISTICS
6 RELIABILITY
Page
1
2
4
5
6
6
8
11
15
16
18
24
27
7 INTERNATIONAL STANDARDS
7-1 SAFETY
7-2 EMC 28
7-3 Environment 28
8 PACKING
8-1 DESIGNATION OF LOT MARK
8-2 PACKING FORM
9 PRECAUTIONS 30
9-1 MOUNTING PRECAUTIONS 30
9-2 OPERATING PRECAUTIONS 30
9-3 ELECTROSTATIC DISCHARGE CONTROL 31
9-4 PRECAUTIONS FOR STRONG LIGHT EXPOSURE 31
9-5 STORAGE 31
9-6 HANDLING PRECAUTIONS FOR PROTECTION FILM 31
Ver.0.0
28
28
29
29
29
2/ 43
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
www.panelook.com
Global LCD Panel Exchange Center
Revision No. Revision Date Page Description
0.0 Jul, 21, 2011 - Preliminary Specification
www.panelook.com
LC550EUD
Product Specification
RECORD OF REVISIONS
Ver.0.0
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
3/ 43
www.panelook.com
Global LCD Panel Exchange Center
1. General Description
The LC550EUD is a Color Active Matrix Liquid Crystal Display with an integral Light Emitting Diode (LED)
backlight system. The matrix employs a-Si Thin Film Transistor as the active element.
It is a transmissive display type which is operating in the normally black mode. It has a 46.96 inch diagonally
measured active display area with WUXGA resolution (1080 vertical by 1920 horizontal pixel array).
Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arrayed in vertical stripes.
Gray scale or the luminance of the sub-pixel color is determined with a 10-bit gray scale signal for each dot.
Therefore, it can present a palette of more than 1.06Bilion colors.
It has been designed to apply the 10-bit 4-port LVDS interface.
It is intended to support LCD TV, PCTV where high brightness, super wide viewing angle, high color gamut,
high color depth and fast response time are important.
www.panelook.com
LC550EUD
Product Specification
LVDS
CN2
(41pin)
2Port
LVDS 3,4
LVDS
2Port
LVDS
Select
Bit
Select
+12.0V
Local Dim
Dim
DCLK
VSYNC, SIN, SCLK, GND
+24.0V, GND, On/Off
ExtV
CN1
(51pin)
CN3
(8 pin)
BR-B
LVDS 1,2
Option
signal
I2C
EEPROM
SCL
SDA
Timing Controller
LVDS Rx + L/Dim + DGA + ODC
Integrated
Power Circuit
Block
LED Driver
EPI(RGB)
Control
Signals
Power Signals
S1 S1920
G1
TFT - LCD Panel
(1920 × RGB × 1080 pixels)
G1080
V : 8Block
General Features
Active Screen Size
Outline Dimension
Pixel Pitch 0.630 mm x 0.630 mm x RGB
Pixel Format 1920 horiz. by 1080 vert. Pixels, RGB stripe arrangement
54.64 inch (1387.80mm) diagonal
1244.6(H) × 720.9(V) × 9.9(B) / 23.1(D) mm (Typ.) (TBD)
Source Driver Circuit
V : 8Block
Local Dimming : 16 Block
Color Depth 10Bit(D), 1.06 Billion colors
Luminance, White
450 cd/m2 (Center 1point ,Typ.)
Viewing Angle (CR>10) Viewing angle free ( R/L 178 (Min.), U/D 178 (Min.))
Power Consumption Total 122.5W(Typ.) [Logic= 6.1W, Backlight=116.4W (ExtVbr_B=100% )]
Weight 15.8Kg (Typ.) (TBD)
Display Mode Transmissive mode, Normally black
Surface Treatment Hard coating(2H), Anti-glare treatment of the front polarizer (Haze 10%)
Ver.0.0
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
4/ 43
www.panelook.com
Global LCD Panel Exchange Center
2. Absolute Maximum Ratings
The following items are maximum values which, if exceeded, may cause faulty operation or permanent damage
to the LCD module.
Table 1. ABSOLUTE MAXIMUM RATINGS
www.panelook.com
LC550EUD
Product Specification
Parameter Symbol
Unit Note
Min Max
Value
LCD Circuit V
LCD -0.3 +14.0 VDC
Power Input Voltage
Driver V
ON/OFF V
BL -0.3 + 27.0 VDC
OFF / VON -0.3 +5.5 VDC
Driver Control Voltage
Brightness EXTVBR-B 0.0 +5.5 VDC
T-Con Option Selection Voltage VLOGIC -0.3 +4.0 VDC
Operating Temperature TOP 0+50
Storage Temperature T
Panel Front Temperature T
Operating Ambient Humidity H
Storage Humidity H
Note
1. Ambient temperature condition (Ta =
25 r 2 °C )
ST -20 +60
SUR -+68
OP 10 90 %RH
ST 10 90 %RH
°C
°C
°C
2. Temperature and relative humidity range are shown in the figure below.
Wet bulb temperature should be Max 39°C, and no condensation of water.
3. Gravity mura can be guaranteed below 40°C condition.
4. The maximum operating temperatures is based on the test condition that the surface temperature
of display area is less than or equal to 68°C with LCD module alone in a temperature controlled chamber.
Thermal management should be considered in final product design to prevent the surface temperature of
display area from being over 68. The range of operating temperature may be degraded in case of
improper thermal management in final product design.
90%
1
2,3
4
2,3
60
60%
Wet Bulb
Temperature [
10
0
10 20 30 40 50 60 70 800-20
Dry Bulb Temperature [
°C]
20
30
40
50
40%
Humidity [(%)RH]
10%
°C]
Storage
Operation
Ver.0.0
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
5/ 43
www.panelook.com
Global LCD Panel Exchange Center
3. Electrical Specifications
3-1. Electrical Characteristics
It requires two power inputs. One is employed to power for the LCD circuit.
The other Is used for the CCFL backlight circuit.
Table 2. ELECTRICAL CHARACTERISTICS
www.panelook.com
LC550EUD
Product Specification
Parameter Symbol
Value
Min Typ Max
Circuit :
Power Input Voltage V
Power Input Current I
Power Consumption P
Rush current I
LCD
LCD
LCD
RUSH
10.8 12.0 13.2 V
- 510 663 mA 1
- 765 995 mA 2
- 6.1 8.0 Watt 1
--5.0 A 3
Note : 1. The specified current and power consumption are under the V
condition whereas mosaic pattern(8 x 6) is displayed and f
is the frame frequency.
V
2. The current is specified at maximum current pattern.
3. The duration of rush current is about 2ms and rising time of power input is 0.5ms (min.).
White : 1023 Gray
Black : 0 Gray
Unit Note
DC
=12.0V, 25 r 2°C, fV=120Hz
LCD
Mosaic Pattern(8 x 6)
Ver.0.0
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
6/ 43
www.panelook.com
Global LCD Panel Exchange Center
Table 3. ELECTRICAL CHARACTERISTICS (Continue)
www.panelook.com
LC550EUD
Product Specification
Parameter Symbol
LED Driver :
Power Supply Input Voltage VBL 22.8 24.0 25.2 Vdc 1
Power Supply Input Current IBL
Power Supply Input Current (In-Rush) In-rush - 6.7 A
Power Consumption PBL -
On/Off
Input Voltage for
Control System
Signals
LED :
Life Time 30,000 Hrs 2
Brightness Adjust ExtV
PWM Frequency for
NTSC & PAL
Pulse Duty Level
(PWM)
On V on 2.5 - 5.0 Vdc
Off V off -0.3 0.0 0.7 Vdc
BR-B 1 - 100 %
PAL 100 Hz 3
NTSC 120 Hz 3
High Level 2.5 - 5.0
Low Level 0.0 - 0.7
Min Typ Max
Values
-
4.85
116.4 127.3
5.30
Unit Notes
A1
BL = 22.8V
V
Ext V
BR-B = 100%
W1
On Duty
Vdc
Vdc
HIGH : on duty
LOW : off duty
4
6
Notes :
1. Electrical characteristics are determined after the unit has been ‘ON’ and stable for approximately 60
minutes at 25±2°C. The specified current and power consumption are under the typical supply Input voltage
24Vand V
BR (ExtVBR-B : 100%), it is total power consumption.
2. The life time (MTTF) is determined as the time which luminance of the LED is 50% compared to that of initial
value at the typical LED current (ExtVBR-B :100%) on condition of continuous operating in LCM state at
25±2°C.
3. LGD recommend that the PWM freq. is synchronized with One time harmonic of V_sync signal of system.
Though PWM frequency is over 120Hz (max 252Hz), function of LED Driver is not affected.
4. The duration of rush current is about 200ms.
5. Even though inrush current is over the specified value, there is no problem if I
2
T spec of fuse is satisfied.
6. Ext_PWM Signal have to input available duty range.
Between 99% and 100%
ExtVBR-B 0% and 100% is possible.
But
High
ExtVBR-B duty have to be avoided. ( 99% < ExtVBR-B < 100%)
Available duty range
Low
0%
1%
Ver.0.0
99% 100%Ext_PWM Input Duty
7/ 43
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
www.panelook.com
Global LCD Panel Exchange Center
www.panelook.com
Product Specification
3-2. Interface Connections
This LCD module employs two kinds of interface connection, 51-pin connector and 41-pin connector are used
for the module electronics and 14-pin connector is used for the integral backlight system.
3-2-1. LCD Module
- LCD Connector(CN1): FI-R51S-HF(manufactured by JAE) or compatible
Refer to below and next Page table
- Mating Connector : FI-R51HL(JAE) or compatible
Table 4-1. MODULE CONNECTOR(CN1) PIN CONFIGURATION
No Symbol Description No Symbol Description
1
2
3
4
5
6
7
8
9
10
11 GND
12 R1AN
13 R1AP
14 R1BN
15
16 R1CN
17
18 GND
19 R1CLKN
20
21 GND
22 R1DN
23 R1DP
24 R1EN
25 R1EP
26
Note
NC
NC
NC
NC
NC
NC
LVDS Select
NC
NC
L-DIM Enable ‘H’ = Enable , ‘L’ or NC = Disable
R1BP
R1CP
R1CLKP
NC
No Connection
No Connection
No Connection
No Connection (Note 4)
No Connection (Note 4)
No Connection (Note 4)
‘H’ =JEIDA , ‘L’ or NC = VESA
No Connection (Note 4)
No Connection (Note 4)
Ground
FIRST LVDS Receiver Signal (A-)
FIRST LVDS Receiver Signal (A+)
FIRST LVDS Receiver Signal (B-)
FIRST LVDS Receiver Signal (B+)
FIRST LVDS Receiver Signal (C-)
FIRST LVDS Receiver Signal (C+)
Ground
FIRST LVDS Receiver Clock Signal(-)
FIRST LVDS Receiver Clock Signal(+)
Ground
FIRST LVDS Receiver Signal (D-)
FIRST LVDS Receiver Signal (D+)
FIRST LVDS Receiver Signal (E-)
FIRST LVDS Receiver Signal (E+)
No Connection
1. All GND(ground) pins should be connected together to the LCD module’s metal frame.
2. All V
LCD (power input) pins should be connected together.
3. All Input levels of LVDS signals are based on the EIA 644 Standard.
4. #1~#6 & #8~#9 NC (No Connection): These pins are used only for LGD (Do not connect)
5. Specific pins(pin No. #10) are used for Local Dimming function of the LCD module.
If not used, these pins are no connection. (Please see the Appendix V for more information.)
6. LVDS pin (pin No. #24,25,40,41) are used for 10Bit(D) of the LCD module.
If used for 8Bit(R), these pins are no connection.
7. Specific pin No. #44 is used for “No signal detection” of system signal interface.
It should be GND for NSB(No Signal Black) during the system interface signal is not.
If this pin is “H”, LCD Module displays AGP(Auto Generation Pattern).
LC550EUD
27
Bit Select
28
29
30
31
32
33
34
35
36
37
38
39
40 R2EN
41 R2EP
42
43
44
45
46
47
48
49
50
51
-- -
R2AN
R2AP
R2BN
R2BP
R2CN
R2CP
GND
R2CLKN
R2CLKP
GND
R2DN
R2DP
NC
NC
GND Ground
GND Ground
GND Ground
NC No connection
VLCD Power Supply +12.0V
VLCD Power Supply +12.0V
VLCD Power Supply +12.0V
VLCD Power Supply +12.0V
‘H’ or NC= 10bit(D) , ‘L’ = 8bit
SECOND LVDS Receiver Signal (A-)
SECOND LVDS Receiver Signal (A+)
SECOND LVDS Receiver Signal (B-)
SECOND LVDS Receiver Signal (B+)
SECOND LVDS Receiver Signal (C-)
SECOND LVDS Receiver Signal (C+)
Ground
SECOND LVDS Receiver Clock Signal(-)
SECOND LVDS Receiver Clock Signal(+)
Ground
SECOND LVDS Receiver Signal (D-)
SECOND LVDS Receiver Signal (D+)
SECOND LVDS Receiver Signal (E-)
SECOND LVDS Receiver Signal (E+)
No Connection
No Connection
Ver.0.0
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
8/ 43
www.panelook.com
Global LCD Panel Exchange Center
-LCD Connector (CN2) : FI-RE41S-HF (manufactured by JAE) or compatible
- Mating Connector : FI-RE41HL
Table 4-2. MODULE CONNECTOR(CN2) PIN CONFIGURATION
No Symbol Description No Symbol Description
1
2
3
4NC
5
6
7
8
9
10
11
12
13 RB3P
14
15
16
17
18 RCLK3P
19
20
21
NC
NC
NC
NC
NC
NC
NC
GND
RA3N
RA3P
RB3N
RC3N
RC3P
GND
RCLK3N
GND
RD3N
RD3P
No connection 22
No connection 23
No connection 24 GND Ground
No connection
No connection
No connection 27
No connection 28
No connection 29 RB4P
Ground
THIRD LVDS Receiver Signal (A-)
THIRD LVDS Receiver Signal (A+)
THIRD LVDS Receiver Signal (B-)
THIRD LVDS Receiver Signal (B+)
THIRD LVDS Receiver Signal (C-)
THIRD LVDS Receiver Signal (C+)
Ground
THIRD LVDS Receiver Clock Signal(-)
THIRD LVDS Receiver Clock Signal(+)
Ground
THIRD LVDS Receiver Signal (D-)
RD LVDS Receiver Signal (D+)
THI
www.panelook.com
Product Specification
RE3N
25 GND Ground
26
30
31
32
33
34 RCLK4P
35
36
37
38
39
40 GND Ground
41 GND Ground
-
RA4N
RB4N
RC4N
RC4P
RCLK4N
RD4N
RD4P
RE4N
RE3P
RA4P
GND
GND
RE4P
LC550EUD
THIRD LVDS Receiver Signal (E-)
THIRD LVDS Receiver Signal (E+)
FORTH LVDS Receiver Signal (A-)
FORTH LVDS Receiver Signal (A+)
FORTH LVDS Receiver Signal (B-)
FORTH LVDS Receiver Signal (B+)
FORTH LVDS Receiver Signal (C-)
FORTH LVDS Receiver Signal (C+)
Ground
FORTH LVDS Receiver Clock Signal(-)
FORTH LVDS Receiver Clock Signal(+)
Ground
FORTH LVDS Receiver Signal (D-)
FORTH LVDS Receiver Signal (D+)
FORTH LVDS Receiver Signal (E-)
FORTH LVDS Receiver Signal (E+)
Note : 1. All GND(ground) pins should be connected together to the LCD module’s metal frame.
2. LVDS pin (pin No. #22,23,38,39) are used for 10Bit(D) of the LCD module.
If used for 8Bit(R), these pins are no connection.
CN3
#1
#8
CN3
#1 #8
CN1 CN2
#1 #51 #1 #41
CN1 CN2
#1 #51
#1 #41
Rear view of LCM
Ver.0.0
9/ 43
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
www.panelook.com
Global LCD Panel Exchange Center
3-2-2. Backlight Module
Master
-LED Driver Connector
: 20022WR - H14B1(Yeonho) or Equivalent
- Mating Connector
: 20022HS - 14B2 or Equivalent
Table 5. LED DRIVER CONNECTOR PIN CONFIGURATION
Pin No Symbol Description Note
www.panelook.com
LC550EUD
Product Specification
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VBL Power Supply +24.0V
VBL Power Supply +24.0V
VBL Power Supply +24.0V
VBL Power Supply +24.0V
VBL Power Supply +24.0V
GND
GND
GND
GND
GND
Status
ON/OFF
V
NC Don’t care
EXTVBR-B External PWM 3
Backlight Ground
Backlight Ground
Backlight Ground
Backlight Ground
Backlight Ground
Back Light Status 2
Backlight ON/OFF control
Notes :1. GND should be connected to the LCD module’s metal frame.
2. Normal : Low (under 0.7V) / Abnormal : High (upper 3.0V)
3. High : on duty / Low : off duty, Pin#14 can be opened. ( if Pin #14 is open , EXTVBR-B is 100% )
4. Each impedance of pin #12 and 14 is over TBD[K].
1
ଝ Rear view of LCM
PCB
1
14
…
1
14
…
<Master>
Ver.0.0
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
10 / 43
www.panelook.com
Global LCD Panel Exchange Center
3-3. Signal Timing Specifications
Table 6 shows the signal timing required at the input of the LVDS transmitter. All of the interface signal
timings should be satisfied with the following specification for normal operation.
Table 6. TIMING TABLE (DE Only Mode)
ITEM Symbol Min Typ Max Unit Note
www.panelook.com
LC550EUD
Product Specification
Horizontal
Vertical
Frequency
Display
Period
Blank t
Total t
Display
Period
Blank t
Total t
ITEM Symbol Min Typ Max Unit Note
DCLK fCLK 66.97 74.25 78.00 MHz
Horizontal f
Vertical f
HV 480 480 480 tCLK 1920 / 4
t
HB 40 70 200 tCLK 1
HP 520 550 680 tCLK
tVV 1080 1080 1080 Lines
VB
VP
H 121.8 135 140 KHz 2
V
20
(228)
1100
(1308)
108
(95)
45
(270)
1125
(1350)
120
(100)
86
(300)
1166
(1380)
122
(104)
Lines 1
Lines
NTSC :
Hz
108~122Hz
(PAL : 95~104Hz)
2
Note 1. The Input of HSYNC & VSYNC signal does not have an effect on normal operation(DE Only Mode).
If you use spread spectrum for EMI, add some additional clock to minimum value for clock margin.
2. The performance of the electro-optical characteristics may be influenced by variance of the vertical
refresh rate and the horizontal frequency.
3. Timing should be set based on clock frequency.
Ver.0.0
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
11 / 43
www.panelook.com
Global LCD Panel Exchange Center
3-4. LVDS Signal Specification
3-4-1. LVDS Input Signal Timing Diagram
www.panelook.com
LC550EUD
Product Specification
DCLK
First data
Second data
Third data
Forth data
DE(Data Enable)
tCLK
0.5 VDD
Invalid data
Invalid data
Invalid data
Invalid data
DE, Data
Valid data
Pixel 0
Valid data
Pixel 1
Valid data
Pixel 2
Valid data
Pixel 3
Pixel 4
Pixel 5
Pixel 6
Pixel 7
0.7VDD
0.3VDD
Invalid data
Invalid data
Invalid data
Invalid data
DE(Data Enable)
Ver.0.0
* tHB = tHFP + tWH +tHBP
* tVB = tVFP + tWV +tVBP
1 1080
tVV
tVP
12 / 43
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
www.panelook.com
Global LCD Panel Exchange Center
3-4-2. LVDS Input Signal Characteristics
1) DC Specification
LVDS -
LVDS +
www.panelook.com
LC550EUD
Product Specification
V
IN _ MAXVIN _ MIN
#VCM= {(LVDS +) + ( LVDS -)} /2
0V
V
CM
Description Symbol Min Max Unit Note
LVDS Common mode Voltage V
LVDS Input Voltage Range V
CM
IN
1.0 1.5 V -
0.7 1.8 V -
Change in common mode Voltage ǻVCM 250 mV -
2) AC Specification
T
clk
LVDS Clock
A
LVDS Data
(F
=1/T
)
clk
A
LVDS 1’st Clock
LVDS 2nd/ 3rd/ 4thClock
tSKEW
t
SKEW_mintSKEW_max
tSKEW
clk
T
clk
80%
20%
t
RF
Description Symbol Min Max Unit Note
LVDS Differential Voltage
High Threshold
Low Threshold
LVDS Clock to Data Skew Margin t
LVDS Clock/DATA Rising/Falling time t
Effective time of LVDS t
LVDS Clock to Clock Skew Margin (Even to Odd) t
Note
1. All Input levels of LVDS signals are based on the EIA 644 Standard.
2. If t
isn’t enough, t
RF
should be meet the range.
eff
3. LVDS Differential Voltage is defined within t
Ver.0.0
V
TH
V
TL
SKEW
RF
eff
SKEW_EO
100 300 mV
-300 -100 mV
|(0.25*T
260 (0.3*T
)/7| ps -
clk
)/7 ps 2
clk
±360
1/7* T
clk
eff
ps -
T
clk
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
3
-
13 / 43
www.panelook.com
Global LCD Panel Exchange Center
www.panelook.com
LC550EUD
Product Specification
360ps
V+
data
Vcm
Vdata
V+
clk
Vcm
0.5tui
tui
VTH
VTL
360ps
teff
tui : Unit Interval
Vclk
Ver.0.0
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
14 / 43
www.panelook.com
Loading...