LG Display LC550EQJ-SGK1 Specification

(●) Preliminary Specification

()Final Specification

Title 55.0” QWUXGA TFT LCD

LC550EQJ

Product Specification

SPECIFICATION

FOR

APPROVAL

BUYER KONKA

SET MODEL

APPROVED BY

/

/

SIGNATURE

DATE

SUPPLIER LG Display Co., Ltd.

*MODEL LC55EQJ

SUFFIX SGK1 (RoHS Verified)

APPROVED BY

S.S.LEE / Team Leader

REVIEWED BY

S.S.LEE / Project Leader

PREPARED BY

SIGNATURE

DATE

/

Please return 1 copy for your confirmation with

your signature and comments.

Ver 0.1

J.K. Kim / Engineer

TV Product Development Dept.

LG Display Co., Ltd.

Product Specification

CONTENTS

LC550EQJ

Number ITEM

OVER

C

CONTENTS

RECORD OF REVISIONS

1 GENERAL DESCRIPTION

2 ABSOLUTE MAXIMUM RATINGS

3 ELECTRICAL SPECIFICATIONS

3-1 ELECTRICAL CHARACTERISTICS

3-2 INTERFACE CONNECTIONS

3-3 SIGNAL TIMING SPECIFICATIONS

3-4 V by One Input Characteristics

3-5 INTARA INTERFACE SIGNAL SPECIFICATION

3-6 COLOR DATA REFERENCE

3-7 POWER SEQUENCE

4 OPTICAL SPECIFICATIONS

Page

0

1

2

3

4

5

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6

7

8

10

11

12

13

5 MECHANICAL CHARACTERISTICS

6 MECHANICAL DIMENSION

6-1 BOARD ASSEMBLY DIMENSION

6-2 CONTROL BOARD ASSEMBLY DIMMENSION

7 RELIABILITY

8 INTERNATIONAL STANDARDS

8-1 SAFETY

8-2 ENVIRONMENT

9 PACKING

9-1 PACKING FORM

10 PRECAUTIONS

10-1 HANDLING PRECAUTIONS

10-2 OPERATING PRECAUTIONS

10-3 PROTECTION FILM

10-4 STORAGE PRECAUTIONS

19

20

20

21

22

23

23

23

24

24

25

25

25

26

26

10-5 PACKING PRECAUTIONS

10-6 OPERATING CONDITION GUIDE

Ver 0.1

26

26

1 /40

Product Specification

RECORD OF REVISIONS

Revision No. Revision Date Page Description

0.1 Sep, 11, 2013 - Preliminary Specification (First Draft)

LC550EQJ

Ver 0.1

2 /40

LC550EQJ

Product Specification

1. General Description

The LC550EQJ is a Color Active Matrix Liquid Crystal Display with an integral the Source PCB and Gate
implanted on Panel (GIP). The matrix employs a-Si Thin Film Transistor as the active element.
It is a transmissive type display operating in the normally black mode. It has a 54.64 inch diagonally measured
active display area with QWUXGA resolution (2160 vertical by 3840 horizontal pixel array).
Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arranged in vertical stripes.
Gray scale or the luminance of the sub-pixel color is determined with a 10-bit gray scale signal for each dot.
Therefore, it can present a palette of more than 1.06Bilion colors.
It has been designed to apply the 10-bit 8 Lane V by One interface.
It is intended to support LCD TV, PCTV where high brightness, super wide viewing angle, high color gamut,
high color depth and fast response time are important.

EPI(RGB)

G1

Control
Signals

G2160

Data
format

Bit
select

HTPDN

LOCKN

Vby1
8lane

+12V

CN1

(51pin)

Vby1
1~8lane

Option
signal

I2C

EEPROM

SCL

SDA

Timing Controller

Vby1 Rx + DGA + ODC

Power Circuit

Block

Power Signals

General Features

Active Screen Size 54.64 inches(1387.8mm) diagonal

Outline Dimension 1225.2 (H) x 696.7 (V) x 1.4 (D) mm(Typ.)

Source Driver Circuit

S1 S3840

TFT - LCD Panel

(3840 ×RGB ×2160 pixels)

Pixel Pitch 0.315 mm x 0.315 mm

Pixel Format 3840 horiz. by 2160 vert. Pixels, RGB stripe arrangement

Color Depth 10bit(D), 1.06Billon colors

Drive IC Data Interface

Source D-IC : 8-bit EPI, gamma reference voltage, and control signals
Gate D-IC : Gate In Panel

4.84 %(Typ.)Transmittance (With POL)

Viewing angle free ( R/L 178 (Min.), U/D 178 (Min.))Viewing Angle (CR>10)

2.6(TBD)Kg (Typ.) Weight

Transmissive mode, Normally blackDisplay Mode

Hard coating(2H), Anti-glare treatment of the front polarizer 1%(Typ)Surface Treatment (Top)

Ver 0.1

3 /40

LC550EQJ

Product Specification

2. Absolute Maximum Ratings

The following items are maximum values which, if exceeded, may cause faulty operation or permanent damage
to the LCD module.

Table 1. ABSOLUTE MAXIMUM RATINGS

Value

Parameter Symbol

Min Max

Power Input Voltage LCD Circuit VLCD -0.3 +14.0 VDC

T-Con Option Selection Voltage VLOGIC -0.3 +4.0 VDC

Unit Note

1

Operating Temperature TOP 0 +50

Storage Temperature (without packing) TST -20 +60

Panel Front Temperature TSUR - +68

C

°

C

°

C

°

Operating Ambient Humidity HOP 10 90 %RH

Storage Humidity HST 5 90 %RH

Note

1. Ambient temperature condition (Ta =

25 ± 2

°

C )

2. Temperature and relative humidity range are shown in the figure below.
Wet bulb temperature should be Max 39°C, and no condensation of water.

3. Gravity mura can be guaranteed below 40°C condition.

4. The maximum operating temperatures is based on the test condition that the surface temperature

of display area is less than or equal to 68°C with LCD module alone in a temperature controlled chamber.
Thermal management should be considered in final product design to prevent the surface temperature of
display area from being over 68℃. The range of operating temperature may be degraded in case of
improper thermal management in final product design.

90%

60

60%

2,3

4

2,3

Ver 0.1

Wet Bulb
Temperature [

10

0

10 20 30 40 50 60 70 800-20

Dry Bulb Temperature [

°

20

50

]

C

30

40

40%

Humidity [(%)RH]

10%

5%

]

C

°

Storage

Operation

4 /40

Product Specification

3. Electrical Specifications

3-1. Electrical Characteristics

Table 2. ELECTRICAL CHARACTERISTICS

Value

Parameter Symbol

Min Typ Max

Circuit :

Power Input Voltage VLCD 10.8 12.0 13.2 VDC

Unit Note

LC550EQJ

Power Input Current ILCD

- 1450(TBD) TBD mA 1

- 2260(TBD) TBD mA 2

T-CON Option
Selection Voltage

Input High Voltage V

Input Low Voltage V

IH

IL

2.7 - 3.6 VDC

0-0.7VDC

Power Consumption PLCD - 17.4(TBD) 22.6(TBD) Watt 1

Rush current IRUSH - - TBD A 3

Note

1. The specified current and power consumption are under the V
condition, and mosaic pattern(8 x 6) is displayed and f

is the frame frequency.

V

=12.0V, Ta=25 ± 2

LCD

C, fV=60Hz

°

2. The current is specified at the maximum current pattern.

3. The duration of rush current is about 2ms and rising time of power input is 0.5ms (min.).

4. Ripple voltage level is recommended under ±5% of typical voltage

White : 1023 Gray
Black : 0 Gray

Ver 0.1

Mosaic Pattern(8 x 6)

5 /40

LC550EQJ

Product Specification

3-2. Interface Connections

This LCD module employs one kind of interface connection, 51-pin connector is used for the module
electronics.

3-2-1. LCD Module

- LCD Connector(CN1): FI-RE51S-HF(manufactured by JAE) or GT05P-51S-H38(manufactured by LSM)
or IS050-C51B-C39(manufactured by UJU)

- Mating Connector : FI-R51HL(manufactured by JAE) or compatible

Table 3. MODULE CONNECTOR(CN2) PIN CONFIGURATION

No Symbol Description No Symbol Description

1 VLCD Power Supply +12.0V 27 GND Ground

2 VLCD Power Supply +12.0V 28 Rx0n V-by-One HS Data Lane 0

3 VLCD Power Supply +12.0V 29 Rx0p V-by-One HS Data Lane 0

4 VLCD Power Supply +12.0V 30 GND Ground

5 VLCD Power Supply +12.0V 31 Rx1n V-by-One HS Data Lane 1

6 VLCD Power Supply +12.0V 32 Rx1p V-by-One HS Data Lane 1

7 VLCD Power Supply +12.0V 33 GND Ground

8 VLCD Power Supply +12.0V 34 Rx2n V-by-One HS Data Lane 2

9 NC NO CONNECTION 35 Rx2p V-by-One HS Data Lane 2

10 GND Ground 36 GND Ground

11 GND Ground 37 Rx3n V-by-One HS Data Lane 3

12 GND Ground 38 Rx3p V-by-One HS Data Lane 3

13 GND Ground 39 GND Ground

14 NC NO CONNECTION 40 Rx4n V-by-One HS Data Lane 4

15 Data format 0

16 Data format 1 42 GND Ground

17 PCID_EN

18

19

20 NC NO CONNECTION 46 Rx6n V-by-One HS Data Lane 6
21 Bit SEL ‘H’ or NC= 10bit(D) , ‘L’ = 8bit 47 Rx6p V-by-One HS Data Lane 6

22 NC NO CONNECTION 48 GND Ground

23 AGP or NSB

24 GND Ground 50 Rx7p V-by-One HS Data Lane 7
25 HTPDN Hot plug detect 51 GND Ground
26 LOCKN Lock detect - - -

SDA SDA (For I2C)
SCL SCL (For I2C)

Input Data Format [1:0] :
‘00’=Mode1, ’01’=Mode2,
’10’=Mode3, ’11’=Mode4

‘H’ : PCID Enable
‘L’ or ‘NC’ : PCID Disable

‘H’ or NC : AGP
‘L’ : NSB (No signal Black)

41 Rx4p V-by-One HS Data Lane 4

43 Rx5n V-by-One HS Data Lane 5

44 Rx5p V-by-One HS Data Lane 5

45 GND Ground

49 Rx7n V-by-One HS Data Lane 7

Note

Ver 0.1

1. All GND (ground) pins should be connected together to the LCD module’s metal frame.

2. All Input levels of V-by-One signals are based on the V-by-One-HS Standard Version 1.4

3. #14, #20 & #22 NC(No Connection) : These pins are used only for LGD (Do not connect)

4. About specific pin(#15, #16), Please see the Appendix

Ⅷ

.

5. Specific pin No. #23 is used for “No signal detection” of system signal interface.
It should be GND for NSB (No Signal Black) while the system interface signal is not.
If this pin is “H”, LCD Module displays AGP (Auto Generation Pattern).

6 /40

LC550EQJ

Product Specification

3-3. Signal Timing Specifications

Table 4 shows the signal timing required at the input of the Vx1 transmitter. All of the interface signal timings
should be satisfied with the following specification for normal operation.

Table 4. TIMING TABLE (DE Only Mode)

ITEM Symbol Min Typ Max Unit Note

Horizontal

Vertical

Frequency

Display

Period

Blank

Total

Display

Period

Blank

Total

ITEM Symbol Min Typ Max Unit Note

DCLK

Horizontal

tHV

tHB

tHP

tVV

tVB

tVP

fCLK

fH

480 480 480

50(TBD) 70 120

530(TBD) 550 600

2160 2160 2160

40 90 600

2200 2250 2760

60(TBD) 74.25 78.00

121.8

(TBD)

135 140

tCLK

tCLK

tCLK

Lines

Lines

Lines

MHz

KHz

3840/8

1

1

594/8

2

Vertical

notes: 1. The input of HSYNC & VSYNC signal does not have an effect on normal operation (DE Only Mode).

If you use spread spectrum of EMI, add some additional clock to minimum value for clock margin.

2. The performance of the electro-optical characteristics may be influenced by variance of the vertical
refresh rate and the horizontal frequency

Timing should be set based on clock frequency.

※

Ver 0.1

fV

47 60 63

Hz

2

7 /40

Product Specification

3-4. V by One input signal Characteristics

3-4-1. V by One Input Signal Timing Diagram

1UI = 1/(Serial data rate)

LC550EQJ

Y

X

X=0 UI X=1 UI

Table5. Eye Mask Specification

X[UI] Note Y[mV] Note

A 0.25 (max) 2 0 -

B 0.3 (max) 2 50 3

C 0.7(min) 3 50 3

B

ㆍ

A

ㆍ

ㆍㆍ

FE

C

ㆍ

ㆍ

D

Y=0mV

D 0.75(min) 3 0 -

E 0.7(min) 3 l -50 l 3

F 0.3(max) 2 l -50 l 3

notes 1. All Input levels of V by One signals are based on the V by One HS Standard Ver. 1.4

2. This is allowable maximum value.

3. This is allowable minimum value.

4. The eye diagram is measured by the oscilloscope and receiver CDR characteristic must be
emulated.

- PLL bandwidth : 20 Mhz(TBD)

- Damping Factor : 1.5(TBD)

Ver 0.1

8 /40

LC550EQJ

Product Specification

3-4-2. V by One Input Signal Characteristics

1) DC Specification

VRTH

VRCT

VRTL

Description Symbol Min Max Unit

CML Differential input High threshold VRTH - 50 mV

CML common mode Bias Voltage VRCT 0.6(TBD) 0.8(TBD) V

2) AC Specification

mV--50VRTLCML Differential input Low threshold

Rx1

Rx2

Lane0

Vdiff =0

tRISK_INTER

Lane1

Vdiff =0

<Inter-pair Skew between two Lanes>

1H

T-CON

Max 1 DE

V By One Rx IP

Vblank

Hblank

DE

Rx1

(Sub Block)

Rx2

(Sub Block)

Vblank

DE

<Inter-pair Skew between two sub Blocks>

4 Lane

<TCON – VbyOne Brief Diagram >

4 Lane

Description Symbol Min Max Unit notes

Allowable inter-pair skew between lanes tRISK_INTER - 5 UI 1,3

Allowable iner-pair skew between sub-blocks tRISK_BLOCK - 1 DE 1,4

Notes 1.1UI = 1/serial data rate

2. it is the time difference between the true and complementary single-ended signals.

3. it is the time difference of the differential voltage between any two lanes in one sub block.

4. it is the time difference of the differential voltage between any two blocks in one IP.

Ver 0.1

9 /40

3-5. Intra interface Signal Specification

3-5-1. EPI Signal Specification

Table 6. ELECTRICAL CHARACTERISTICS

Parameter Symbol Condition MIN TYP MAX Unit notes

LC550EQJ

Product Specification

Logic & EPI Power Voltage VCC - 1.62 1.8 1.98 V

DC

EPI input common voltage VCM LVDS Type 0.8 VCC/2 1.3 V

EPI input differential voltage Vdiff - 150 - 500 mV

EPI Input eye diagram Veye - 90 - - mV

Effective Veye width time B1&B2 0.25 - - UI

EPI +

0 V

Vdiff

Vdiff

(Differential Probe)

EPI -

0 V

Vdiff

Vcm

(Active Probe)

EPI Differential signal characteristics

1 UI

0.5 UI

0 V

(Differential Probe)

Ver 0.1

Veye

Veye

B1 B2

Eye Pattern of EPI Input

*Source PCB

FIG. 3 Measure point

10 /40

LC550EQJ

Product Specification

3-6. Color Data Reference

The brightness of each primary color (red, green, blue) is based on the 10bit or 8bit gray scale data input for the color.
The higher binary input, the brighter the color. Table 8 provides a reference for color versus data input.

Table 7. COLOR DATA REFERENCE

Byte0

Byte1

Packer input &

Unpacker output

D[0] R[2] R[0]

D[1] R[3] R[1]

D[2] R[4] R[2]

D[3] R[5] R[3]

D[4] R[6] R[4]

D[5] R[7] R[5]

D[6] R[8] R[6]

D[7] R[9] R[7]

D[8] G[2] G[0]

D[9] G[3] G[1]

D[10] G[4] G[2]

D[11] G[5] G[3]

D[12] G[6] G[4]

D[13] G[7] G[5]

D[14] G[8] G[6]

D[15] G[9] G[7]

30bpp RGB (10bit) 24bpp RGB (8bit)

Byte2

Byte3

Ver 0.1

D[16] B[2] B[0]

D[17] B[3] B[1]

D[18] B[4] B[2]

D[19] B[5] B[3]

D[20] B[6] B[4]

D[21] B[7] B[5]

D[22] B[8] B[6]

D[23] B[9] B[7]

D[24] Don’t care

D[25] Don’t care

D[26] B[0]

D[27] B[1]

D[28] G[0]

D[29] G[1]

D[30] R[0]

D[31] R[1]

11 /40

3-7. Power Sequence

3-7-1. LCD Driving circuit

LC550EQJ

Product Specification

Power Supply For LCD

V

LCD

0V

0V

Interface Signal (Tx_data)

User Control Signal

(DATA FORMAT,BIT_SEL, PCID_EN)

Power for LED

Table 8. POWER SEQUENCE

Parameter

Min Typ Max

10%

T

90%

1

T6

T2

100%

Value

Vx1 Data

T3 T4

LED ON

90%

10%

T

7

Unit Notes

10%

T5

Note :

1 0.5 - 20 ms 1

T

2 0--ms2

T

3 400 - - ms 3

T

4 100 --ms3

T

5 1.0 - - s 4

T

6 0-T2ms5

T

T7

1. Even though T1 is over the specified value, there is no problem if I2T spec of fuse is satisfied.

2. If T2 is satisfied with specification after removing V by One Cable, there is no problem.

3. The T3 / T4 is recommended value, the case when failed to meet a minimum specification,
abnormal display would be shown. There is no reliability problem.

4. T5 should be measured after the Module has been fully discharged between power off and on period.

5. If the on time of signals (Interface signal and user control signals) precedes the on time of Power (V
it will be happened abnormal display. When T6 is NC status, T6 doesn’t need to be measured.

6. It is recommendation specification that T7 has to be 0ms as a minimum value.

Please avoid floating state of interface signal at invalid period.

※

When the power supply for LCD (VLCD) is off, be sure to pull down the valid and invalid data to 0V.

※

There is no problem even though LOCKN/HTPDN Signal is on before T1.

※

LCD

6ms--0

),

Ver 0.1

12 /40