LG Display LC500EUD-FFF3 Specification

Product Specification
LC500EUD
Ver. 1.0
0 / 44
( ) Preliminary Specification
(●) Final Specification
Title 50.0” WUXGA TFT LCD
LC500EUD
Product Specification
SPECIFICATION
FOR
APPROVAL
BUYER Sony
MODEL
APPROVED BY
/
/
/
SIGNATURE
DATE
SUPPLIER LG Display Co., Ltd.
SUFFIX FFF3 (RoHS Verified)
APPROVED BY
J.T. Kim/ Team Leader
REVIEWED BY
J.Y. Jeong / Project Leader
PREPARED BY
S.W. Kwag / Engineer
SIGNATURE
DATE
Please return 1 copy for your confirmation with
your signature and comments.
Ver. 1.0
TV Product Development Dept.
LG Display Co., Ltd.
1 / 44
Product Specification
CONTENTS
LC500EUD
Number ITEM
COVER
CONTENTS
RECORD OF REVISIONS
1 GENERAL DESCRIPTION
2 ABSOLUTE MAXIMUM RATINGS
3 ELECTRICAL SPECIFICATIONS
3-1 ELECTRICAL CHARACTERISTICS
3-2 INTERFACE CONNECTIONS
3-3 SIGNAL TIMING SPECIFICATIONS
3-4 SIGNAL TIMING WAVEFORMS
3-5 COLOR DATA REFERENCE
3-6 POWER SEQUENCE
4 OPTICAL SPECIFICATIONS
5 MECHANICAL CHARACTERISTICS
6 RELIABILITY
Page
1
2
3
4
5-6
7-9
10
11-13
14
15-16
17-23
24-26
27
7 INTERNATIONAL STANDARDS
7-1 SAFETY
7-2 EMC
7-3 ENVIRONMENT
8 PACKING
8-1 DESIGNATION OF LOT MARK
8-2 PACKING FORM
9 PRECAUTIONS
9-1 MOUNTING PRECAUTIONS
9-2 OPERATING PRECAUTIONS
9-3 ELECTROSTATIC DISCHARGE CONTROL
9-4 PRECAUTIONS FOR STRONG LIGHT EXPOSURE
9-5 STORAGE
9-6 Handling Precautions for Protection Film 31
9-7 OPERATING GONDITION GUIDE
# APPENDIX- I ~ VIII
Ver. 1.0
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32-44
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Product Specification

RECORD OF REVISIONS

Revision No. Revision Date Page Description
0.1 Sep, 11, 2012 - Preliminary Specification (First Draft)
0.2 Dec. 12. 2012 25.26 Mechanical drawing updated
- Spec updated
1.0 Dec. 21. 2012 Final Specification
LC500EUD
Ver. 1.0
3 / 44
LC500EUD
Product Specification

1. General Description

The LC500EUD is a Color Active Matrix Liquid Crystal Display with an integral Light Emitting Diode (LED) backlight system. The matrix employs a-Si Thin Film Transistor as the active element. It is a transmissive display type which is operating in the normally black mode. It has a 49.50 inch diagonally measured active display area with WUXGA resolution (1080 vertical by 1920 horizontal pixel array). Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arrayed in vertical stripes. Gray scale or the luminance of the sub-pixel color is determined with a 10-bit gray scale signal for each dot. Therefore, it can present a palette of more than 1.06Bilion colors. It has been designed to apply the 10-bit 4-port LVDS interface. It is intended to support LCD TV, PCTV where high brightness, super wide viewing angle, high color gamut, high color depth and fast response time are important.
EPI (RGB)
Control Signals
Power Signals
Source Driver Circuit
S1 S1920
G1
TFT - LCD Panel
(1920 × RGB × 1080 pixels)
[Gate In Panel]
G1080
LVDS
2Port
LVDS
2Port
LVDS Select
L-DIM Enable
Bit Select
+12.0V
CN2
(41pin)
CN1
(51pin)
LVDS 3,4
LVDS 1,2
Option signal
EEPROM
SCL
SDA
Timing Controller
LVDS Rx + L/D + DGA + ODC
Integrated
Power Circuit
Block
SIN, SCLK, V_Sync
+24.0V, GND, On/Off
ExtVBR-B
LED Driver
Local Dimming : 3 Block
General Features
Active Screen Size 49.50 inches(1257.31mm) diagonal
Outline Dimension 1115.6(H) × 641.8(V) X 10.8(B)/ 22.4 mm(D) (Typ.)
Pixel Pitch 0.57075 mm x 0.57075 mm
Pixel Format 1920 horiz. by 1080 vert. Pixels, RGB stripe arrangement
Color Depth 10bit(D), 1.06 Billion colors
Luminance, White 400 cd/m2 (Center 1point ,Typ.)
Viewing Angle (CR>10) Viewing angle free ( R/L 178 (Min.), U/D 178 (Min.))
Power Consumption Total 77.3W (Typ.) [Logic= 8.2W, LED Driver=69.1W (ExtVbr_B=100% )]
Weight 12 Kg (Typ.)
Display Mode Transmissive mode, Normally black
Surface Treatment Hard coating(2H), Anti-glare treatment of the front polarizer ,Haze 1%(Typ)
Ver. 1.0
4 / 44
LC500EUD
Product Specification

2. Absolute Maximum Ratings

The following items are maximum values which, if exceeded, may cause faulty operation or permanent damage to the LCD module.
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter Symbol
Power Input Voltage
Driver Control Voltage
T-Con Option Selection Voltage VLOGIC -0.3 +4.0 VDC
Operating Temperature TOP 0 +50 °C
Storage Temperature TST -20 +65 °C
Panel Front Temperature TSUR - +68 °C 4
Operating Ambient Humidity HOP 10 90 %RH
Storage Humidity HST 10 90 %RH
Notes
1. Ambient temperature condition (Ta = 25 ± 2 °C )
LCD Circuit VLCD -0.3 +14.0 VDC
Driver VBL -0.3 + 27.0 VDC
ON/OFF VOFF / VON -0.3 +3.9 VDC
Brightness EXTVBR-B 0.0 +3.9 VDC
Status Status -0.3 +5.5
Value
Unit Notes
Min Max
VDC
2. Temperature and relative humidity range are shown in the figure below.
Wet bulb temperature should be Max 39°C, and no condensation of water.
3. Gravity mura can be guaranteed below 40°C condition.
4. The maximum operating temperatures is based on the test condition that the surface temperature
of display area is less than or equal to 68°C with LCD module alone in a temperature controlled chamber. Thermal management should be considered in final product design to prevent the surface temperature of display area from being over 68. The range of operating temperature may be degraded in case of improper thermal management in final product design.
90%
1
2,3
2,3
Ver. 1.0
Wet Bulb Temperature [°C]
20
10
0
10 20 30 40 50 60 70 800-20 Dry Bulb Temperature [°C]
30
40
50
60
60%
40%
10%
Storage
Operation
Humidity [(%)RH]
5 / 44
LC500EUD
Product Specification
3. Electrical Specifications
3-1. Electrical Characteristics
It requires two power inputs. One is employed to power for the LCD circuit. The other Is used for the LED backlight and LED Driver circuit.
Table 2. ELECTRICAL CHARACTERISTICS
Parameter Symbol
Min Typ Max
Circuit :
Power Input Voltage VLCD 10.8 12.0 13.2 VDC
Power Input Current ILCD
Power Consumption PLCD - 8.2 10.6 Watt 1
Rush current IRUSH - - 5.0 A 3
notes
1. The specified current and power consumption are under the V
- 680 884 mA 1
- 980 1274 mA 2
Value
Unit Note
=12.0V, Ta=25 ± 2°C, fV=120Hz
LCD
condition, and mosaic pattern(8 x 6) is displayed and fVis the frame frequency.
2. The current is specified at the maximum current pattern.
3. The duration of rush current is about 2ms and rising time of power input is 0.5ms (min.).
4. Ripple voltage level is recommended under ±5% of typical voltage
White : 1023 Gray Black : 0 Gray
Ver. 1.0
Mosaic Pattern(8 x 6)
6 / 44
Product Specification
Table 3. ELECTRICAL CHARACTERISTICS (Continue)
LC500EUD
Parameter Symbol
Min Typ Max
LED Driver :
Power Supply Input Voltage VBL 22.8 24.0 25.2 Vdc 1
Power Supply Input Current IBL
Power Supply Input Current (In-Rush) In-rush - - 6 A
Power Consumption PBL -
On V on 2.5 - 3.6 Vdc
Off V off -0.3 0.0 0.7 Vdc
PAL 100 Hz 3
NTSC 120 Hz 3
High Level 2.5 - 3.6
Low Level 0.0 - 0.7
Input Voltage for
Control System
Signals
On/Off
Brightness Adjust ExtVBR-B 1 - 100 %
PWM Frequency for NTSC & PAL
Pulse Duty Level (PWM)
Values
-
2.88
69.1 74.5
3.10
Unit Notes
A 1
VBL = 22.8V Ext VBR-B = 100%
W 1
On Duty
Vdc
Vdc
HIGH : on duty
LOW : off duty
4
6
LED :
Life Time 30,000 50,000 Hrs 2
Notes :
1. Electrical characteristics are determined after the unit has been ‘ON’ and stable for approximately 60
minutes at 25±2°C. The specified current and power consumption are under the typical supply Input voltage 24Vand VBR (ExtVBR-B : 100%), it is total power consumption.
2. The life time (MTTF) is determined as the time which luminance of the LED is 50% compared to that of initial value at the typical LED current (ExtVBR-B :100%) on condition of continuous operating in LCM state at 25±2°C.
3. LGD recommend that the PWM freq. is synchronized with One time harmonic of V_sync signal of system. Though PWM frequency is over 120Hz (max 252Hz), function of LED Driver is not affected.
4. The duration of rush current is about 200ms. This duration is applied to LED on time.
5. Even though inrush current is over the specified value, there is no problem if I2T spec of fuse is satisfied.
6. Ext_PWM Signal have to input available duty range. Between 99% and 100% ExtVBR-B duty have to be avoided. ( 99% < ExtVBR-B < 100%) But ExtVBR-B 0% and 100% are available.
High
Available duty range
Low
0%
1%
99% 100%Ext_PWM Input Duty
Ver. 1.0
7 / 44
LC500EUD
Product Specification
3-2. Interface Connections
This LCD module employs two kinds of interface connection, 51-pin connector and 41-pin connector are used for the module electronics and 14-pin connector is used for the integral backlight system.
3-2-1. LCD Module
- LCD Connector(CN1): FI-RE51S-HF(manufactured by JAE) or GT05P-51S-H38(manufactured by LSM) or IS050-C51B-C39(manufactured by UJU)
- Mating Connector : FI-R51HL(JAE) or compatible
Table 4. MODULE CONNECTOR(CN1) PIN CONFIGURATION
No Symbol Description No Symbol Description
PCID_EN
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20 21 22
23
24 25 26
NC
NC
NC
NC
NC
LVDS Select
NC
NC
L-DIM Enable ‘H’ = Enable , ‘L’ or NC = Disable
GND
R1AN
R1AP
R1BN
R1BP
R1CN
R1CP
GND
R1CLKN
R1CLKP
GND R1DN
R1DP
R1EN R1EP
NC or GND
‘H’ : PCID Enable, ‘L’ or NC : PCID Disable (3D Mode Only)
No Connection (notes 4)
No Connection (notes 4)
No Connection (notes 4)
No Connection (notes 4)
No Connection (notes 4)
‘H’ =JEIDA , ‘L’ or NC = VESA
No Connection (notes 4)
No Connection (notes 4)
Ground
FIRST LVDS Receiver Signal (A-)
FIRST LVDS Receiver Signal (A+)
FIRST LVDS Receiver Signal (B-)
FIRST LVDS Receiver Signal (B+)
FIRST LVDS Receiver Signal (C-)
FIRST LVDS Receiver Signal (C+) Ground
FIRST LVDS Receiver Clock Signal(-)
FIRST LVDS Receiver Clock Signal(+) Ground
FIRST LVDS Receiver Signal (D-)
FIRST LVDS Receiver Signal (D+)
FIRST LVDS Receiver Signal (E-) FIRST LVDS Receiver Signal (E+)
No Connection or Ground
27
Bit Select
28
29
30
31
32
33
34
35
36
37
38
39 40
41
42
43
44
45
46 47 48
49
50 51
- - -
R2AN
R2AP
R2BN
R2BP
R2CN
R2CP
GND
R2CLKN
R2CLKP
GND
R2DN
R2DP
R2EN
R2EP
NC or GND
NC or GND
GND Ground (notes 7)
GND Ground
GND Ground
NC No connection VLCD Power Supply +12.0V
VLCD Power Supply +12.0V
VLCD Power Supply +12.0V VLCD Power Supply +12.0V
‘H’ or NC= 10bit(D) , ‘L’ = 8bit
SECOND LVDS Receiver Signal (A-)
SECOND LVDS Receiver Signal (A+)
SECOND LVDS Receiver Signal (B-)
SECOND LVDS Receiver Signal (B+)
SECOND LVDS Receiver Signal (C-)
SECOND LVDS Receiver Signal (C+) Ground
SECOND LVDS Receiver Clock Signal(-)
SECOND LVDS Receiver Clock Signal(+) Ground
SECOND LVDS Receiver Signal (D-)
SECOND LVDS Receiver Signal (D+)
SECOND LVDS Receiver Signal (E-)
SECOND LVDS Receiver Signal (E+)
No Connection or Ground
No Connection or Ground
notes
Ver. 1.0
1. All GND (ground) pins should be connected together to the LCD module’s metal frame.
2. All VLCD (power input) pins should be connected together.
3. All Input levels of LVDS signals are based on the EIA 644 Standard.
4. #2~#6 & #8~#9 NC (No Connection): These pins are used only for LGD (Do not connect)
5. Specific pin (#10) is used for Local Dimming function of the LCD module. If not used, these pins are no connection. (Please see the Appendix III-3 for more information.)
6. LVDS pin (pin No. #24,25,40,41) are used for 10Bit(D) of the LCD module. If used for 8Bit(R), these pins are no connection.
7. Specific pin No. #44 is used for “No signal detection” of system signal interface. It should be GND for NSB (No Signal Black) while the system interface signal is not. If this pin is “H”, LCD Module displays AGP (Auto Generation Pattern).
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LC500EUD
Product Specification
-LCD Connector (CN2) : FI-RE41S-HF(manufactured by JAE) or GT05P-41S-H38(manufactured by LSM)
- or IS050-C41B-C39(manufactured by UJU)
- Mating Connector : FI-RE41HL
Table 4-2. MODULE CONNECTOR(CN2) PIN CONFIGURATION
No Symbol Description No Symbol Description
1
2
3
4 NC
5
6
7
8
9
10
11
12
13 RB3P
14
15
16
17
18 RCLK3P
19
20
21
NC NC
NC
NC
NC
NC
NC
GND
RA3N
RA3P
RB3N
RC3N
RC3P
GND
RCLK3N
GND
RD3N
RD3P
No connection 22
No connection 23
No connection 24 GND Ground No connection
No connection
No connection 27
No connection 28
No connection 29 RB4P Ground
THIRD LVDS Receiver Signal (A-)
THIRD LVDS Receiver Signal (A+)
THIRD LVDS Receiver Signal (B-)
THIRD LVDS Receiver Signal (B+)
THIRD LVDS Receiver Signal (C-)
THIRD LVDS Receiver Signal (C+) Ground
THIRD LVDS Receiver Clock Signal(-)
THIRD LVDS Receiver Clock Signal(+) Ground
THIRD LVDS Receiver Signal (D-)
THIRD LVDS Receiver Signal (D+)
25 GND Ground
26
30
31
32
33
34 RCLK4P
35
36
37
38
39
40 GND Ground
41 GND Ground
-
RE3N
RE3P
RA4N
RA4P
RB4N
RC4N
RC4P
GND
RCLK4N
GND
RD4N
RD4P
RE4N
RE4P
THIRD LVDS Receiver Signal (E-)
THIRD LVDS Receiver Signal (E+)
FORTH LVDS Receiver Signal (A-)
FORTH LVDS Receiver Signal (A+)
FORTH LVDS Receiver Signal (B-)
FORTH LVDS Receiver Signal (B+)
FORTH LVDS Receiver Signal (C-)
FORTH LVDS Receiver Signal (C+) Ground
FORTH LVDS Receiver Clock Signal(-)
FORTH LVDS Receiver Clock Signal(+) Ground
FORTH LVDS Receiver Signal (D-)
FORTH LVDS Receiver Signal (D+)
FORTH LVDS Receiver Signal (E-)
FORTH LVDS Receiver Signal (E+)
Note : 1. All GND (ground) pins should be connected together to the LCD module’s metal frame.
2. LVDS pin (pin No. #22,23,38,39) are used for 10Bit(D) of the LCD module. If used for 8Bit(R), these pins are no connection.
CN3
#1
#4
CN3
#1 #4
CN1 CN2
#1
CN1 CN2
#1 #51
#51 #1 #41
#1 #41
Rear view of LCM
Ver. 1.0
9 / 44
Product Specification
3-2-2. Backlight Module
Master
LED Driver Connector
: 20022WR - H14B2(Yeonho) or compatible
Mating Connector
: 20022HS - 14B2 or compatible
Table 5-1. LED DRIVER CONNECTOR PIN CONFIGURATION
Pin No Symbol Description Note
LC500EUD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VBL Power Supply +24.0V
VBL Power Supply +24.0V
VBL Power Supply +24.0V
VBL Power Supply +24.0V
VBL Power Supply +24.0V
GND Backlight Ground
GND Backlight Ground
GND Backlight Ground
GND Backlight Ground
GND Backlight Ground
Status Back Light Status 2
ON/OFF
V
NC Don’t care
EXTVBR-B External PWM 3
Backlight ON/OFF control
Notes :1. GND should be connected to the LCD module’s metal frame.
2. Normal : Low (under 0.7V) / Abnormal : Open
3. High : on duty / Low : off duty, Pin#14 can be opened. ( if Pin #14 is open , EXTVBR-B is 100% )
4. Each impedance of pin #12 and 14 is over 50 [K] .
1
Rear view of LCM
1
Ver. 1.0
14
<Master>
Status
PCB
1
14
10 / 44
LC500EUD
Product Specification
3-3. Signal Timing Specifications
Table 6 shows the signal timing required at the input of the LVDS transmitter. All of the interface signal timings should be satisfied with the following specification for normal operation.
Table 6. TIMING TABLE (DE Only Mode)
ITEM Symbol Min Typ Max Unit notes
Horizontal
Vertical
Frequency
Display
Period
Blank tHB 40 70 200 tCLK 1
Total tHP 520 550 680 tCLK
Display
Period
Blank tVB
Total tVP
ITEM Symbol Min Typ Max Unit notes
DCLK fCLK 66.97 74.25 78.00 MHz
Horizontal fH 121.8 135 140 KHz 2
Vertical fV
tHV 480 480 480 tCLK 1920 / 4
tVV 1080 1080 1080 Lines
20
(228)
1100
(1308)
108
(95)
45
(270)
1125
(1350)
120
(100)
86
(300)
1166
(1380)
122
(104)
Lines 1
Lines
Hz
NTSC (PAL)
2
notes: 1. The input of HSYNC & VSYNC signal does not have an effect on normal operation (DE Only Mode).
If you use spread spectrum of EMI, add some additional clock to minimum value for clock margin.
2. The performance of the electro-optical characteristics may be influenced by variance of the vertical refresh rate and the horizontal frequency
3. Spread Spectrum Rate (SSR) for 50KHz ~ 100kHz Modulation Frequency(FMOD) is calculated by
(7 – 0.06*Fmod), where Modulation Frequency (FMOD) unit is KHz. LVDS Receiver Spread spectrum Clock is defined as below figure
Timing should be set based on clock frequency.
Ver. 1.0
11 / 44
Product Specification
Please pay attention to the followings when you set Spread Spectrum Rate(SSR) and Modulation Frequency(FMOD)
LC500EUD
1. Please set proper Spread Spectrum Rate(SSR) and Modulation Frequency (FMOD) of TV system LVDS output.
2. Please check FOS after you set Spread Spectrum Rate(SSR) and Modulation Frequency(FMOD) to avoid abnormal display. Especially, harmonic noise can appear when you use Spread Spectrum under FMOD 30 KHz.
Ver. 1.0
12 / 44
3-4. LVDS Signal Specification
3-4-1. LVDS Input Signal Timing Diagram
LC500EUD
Product Specification
DCLK
First data
Second data
Third data
Forth data
DE(Data Enable)
tCLK
0.5 VDD
Invalid data
Invalid data
Invalid data
Invalid data
DE, Data
Valid data
Pixel 0
Valid data
Pixel 1
Valid data
Pixel 2
Valid data
Pixel 3
Pixel 4
Pixel 5
Pixel 6
Pixel 7
0.7VDD
0.3VDD
Invalid data
Invalid data
Invalid data
Invalid data
DE(Data Enable)
Ver. 1.0
* tHB = tHFP + tWH +tHBP
* tVB = tVFP + tWV +tVBP
1 1080
tVV
tVP
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