LG Display LC470EUF-SDC6 Specification

Product Specification

SPECIFICATION

FOR

APPROVAL

LC470EUF

(

Preliminary Specification

●

))(

Final Specification

47.0” WUXGA TFT LCDTitle

LG Display Co., Ltd.SUPPLIER

LC470EUF*MODEL

SDC6 (Rohs Verified)SUFFIX

SIGNATURE

DATE

MODEL

APPROVED BY

/

LGEBUYER

SIGNATURE

DATE

*When you obtain standard approval,

please use the above model name without suffix

APPROVED BY

D.W. Lee / Team Leader

REVIEWED BY

/ Project Leader

PREPARED BY

/

Please return 1 copy for your confirmation with

your signature and comments.

Ver. 0.0

Y.C. Chang / Engineer

TV Development Dept.

LG Display Co., Ltd

1 / 43

Product Specification

RECORD OF REVISIONS

Preliminary Specification-Jun. 29, 20110.0

LC470EUF

DescriptionPageRevision DateRevision No.

Ver. 0.0

3 / 43

LC470EUF

Product Specification

1. General Description

The LC470EUF is a Color Active Matrix Liquid Crystal Display with an integral Light Emitting Diode (LED) back l i g h t s y s t e m . T h e matr i x employs a-Si T h i n F i l m Transis t o r as t he a c t i ve e l e m e n t. It is a transmissive display type which is operating in the normally black mode. It has a 46.96 inch diagonally measured active display area with WUXGA resolution (1080 vertical by 1920 horizontal pixel array). Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arrayed in vertical stripes. Gray scale or the luminance of the sub-pixel color is determined with a 10-bit gray scale signal for each dot. Therefore, it can present a palette of more than 1.06Bilion colors. It has been designed to apply the 10-bit 4-port LVDS interface. It is intended to support LCD TV, PCTV where high brightness, super wide viewing angle, high color gamut, high color depth and fast response time are important.

LVDS

CN2

(41pin)

2Port

LVDS 3,4

LVDS

2Port

LVDS Select

Bit Select

+12.0V

CN1

(51pin)

LVDS 1,2

Option signal

I2C

LED Anode

LED Cathode

General Features

Active Screen Size

Outline Dimension

Pixel Pitch

Pixel Format

Color Depth

Luminance, White

EEPROM

SCL

SDA

Timing Controller

LVDS Rx + L/Dim + DGA + ODC

Integrated

Power Circuit

Power Signals

Block

CN201 (13pin)

CN202 (12pin)

46.96 inch (1192.78mm) diagonal

1079.0(H) x 625.0 (V) x 10.8(B) / 21.0 mm (D) (Typ.)

0.5415 mm x 0.5415 mm x RGB

1920 horiz. by 1080 vert. Pixels, RGB stripe arrangement

10Bit(D), 1.06 Billion colors

400 cd/m2 (Center 1point ,Typ.)

Mini-LVDS(RGB)

Control Signals

G1

G1080

Source Driver Circuit

S1 S1920

TFT - LCD Panel

(1920 × RGB × 1080 pixels)

[Gate In Panel]

V : 8Block

Local Dimming :

V : 8Block

16 Block

Viewing Angle (CR>10)

Power Consumption

Weight

Display Mode

Surface Treatment

Ver. 0.0

Viewing angle free ( R/L 178 (Min.), U/D 178 (Min.))

Total 90W(Typ.) [Logic= 8.0W, Backlight=82W (ExtVbr_B=100% )]

12.4 Kg (Typ.)

Transmissive mode, Normally black

Hard coating(2H), Anti-glare treatment of the front polarizer (Haze 10%)

4 / 43

Product Specification

2. Absolute Maximum Ratings

The following items are maximum values which, if exceeded, may cause faulty operation or to the LCD module.

Table 1. ABSOLUTE MAXIMUM RATINGS

LC470EUF

permanent damage

Parameter Note

LED Input Voltage

Note

1. Ambient temperature condition (Ta = 25 ± 2 °C )

Symbol

Value

MaxMin

Vf

Unit

VDC+14.0-0.3VLCDLCD CircuitPower Input Voltage

VDC+4.0-0.3VLOGICT-Con Option Selection Voltage

°C+500TOPOperating Temperature

°C+60-20TSTStorage Temperature

°C+68-TSURPanel Front Temperature

%RH9010HOPOperating Ambient Humidity

%RH9010HSTStorage Humidity

2. Temperature and relative humidity range are shown in the figure below.

Wet bulb temperature should be Max 39°C, and no condensation of water.

3. Gravity mura can be guaranteed below 40°C condition.

4. The maximum operating temperatures is based on the test condition that the surface temperature

of display area is less than or equal to 68°C with LCD module alone in a temperature controlled chamber. Thermal management should be considered in final product design to prevent the surface temperature of display area from being over 68℃. The range of operating temperature may be degraded in case of improper thermal management in final product design.

5. Storage condition is guaranteed under packing condition

90%

1VDC+66.00.0

2,3

4

2,3

60

60%

Ver. 0.0

Wet Bulb Temperature [°C]

20

10

0

10 20 30 40 50 60 70 800-20 Dry Bulb Temperature [°C]

30

40

50

40%

Humidity [(%)RH]

10%

Storage

Operation

5 / 43

LC470EUF

Product Specification

3. Electrical Specifications

3-1. Electrical Characteristics

It requires two power inputs. One is employed to power for the LCD circuit. The other Is used for the LED backlight and LED Driver circuit.

Table 2. ELECTRICAL CHARACTERISTICS

Parameter Symbol

Value

Circuit :

Power Input Voltage

Power Input Current

Power Consumption

Rush current

LCD

I

LCD

RUSH

Note : 1. The specified current and power consumption are under the V

condition whereas mosaic pattern(8 x 6) is displayed and fVis the frame frequency.

2. The current is specified at maximum current pattern.

3. The duration of rush current is about 2ms and rising time of power input is 0.5ms (min.).

White : 1023 Gray Black : 0 Gray

MaxTypMin

13.212.010.8V

=12.0V, 25 ± 2°C, fV=120Hz

LCD

V

DC

NoteUnit

1mA871670-

2mA1261970-

1Watt10.58.04-P

3A5.0--I

Mosaic Pattern(8 x 6)

Ver. 0.0

6 / 43

Product Specification

Table 3. ELECTRICAL CHARACTERISTICS (Continue)

LC470EUF

Parameter Symbol

Backlight Assembly :

Forward Current (one array)

Forward Voltage V Forward Voltage Variation △V

Power Consumption P

Burst Dimming Duty On duty

Burst Dimming Frequency 1/T

LED Array : (APPENDIX-VII)

Life Time 30,000 50,000 Hrs 7

Notes :

The design of the LED driver must have specifications for the LED array in LCD Assembly.

Anode #1,#2 I

Cathode I

F (anode)

F (cathode)

F

BL

Min Typ Max

95 100 105

46.4 51.2 56

74.2 81.9 89.6 1 - 100

95 182

Values

400

1.7

Unit Note

mAdc

Vdc 4

Vdc 5

W 6

%

Hz 8

The electrical characteristics of LED driver are based on Constant Current driving type. The performance of the LED in LCM, for example life time or brightness, is extremely influenced by the characteristics of the LED Driver. So, all the parameters of an LED driver should be carefully designed. When you design or order the LED driver, please make sure unwanted lighting caused by the mismatch of the LED and the driver (no lighting, flicker, etc) has never been occurred. When you confirm it, the LCD– Assembly should be operated in the same condition as installed in your instrument.

1. Electrical characteristics are based on LED Array specification.

2. Specified values are defined for a Backlight Assembly. (2 LED array/LCM)

3. Each LED array has 2 anode terminals and 8 cathode terminals. The forward current(IF) of the anode terminal is 400mA and it supplies 100mA into 4 strings, respectively

1string(8 LED PKG)

±5%

2, 3

Anode#1

Anode#2

400mA

° ° °

100mA

Cathode #1

Cathode #4

1 LED Array (8 Strings)

Cathode #5

Cathode #8

4. The forward voltage(VF) of LED array depends on ambient temperature.(Appendix VI)

5. ΔVFmeans Max VF-Min VFin one Backlight. So VFvariation in a Backlight isn’t over Max. 1.7V

6. Maximum level of power consumption is measured at initial turn on. Typical level of power consumption is measured after 1hrs aging at 25 ± 2°C.

7. The life time(MTTF) is determined as the time at which brightness of the LED is 50% compared to that of

initial value at the typical LED current on condition of continuous operating at 25 ± 2°C, based on duty 100%.

8. The reference method of burst dimming duty ratio. It is recommended to use synchronous V-sync frequency to prevent waterfall (Vsync x 1 =Burst Frequency) Though PWM frequency is over 182Hz (max252Hz), function of backlight is not affected.

Ver. 0.0

7 / 43

LC470EUF

Product Specification

3-2. Interface Connections

This LCD module employs two kinds of interface connection, 51-pin connector and 41-pin connector are used for the module electronics and 14-pin connector is used for the integral backlight system.

3-2-1. LCD Module

- LCD Connector(CN1): FI-R51S-HF(manufactured by JAE) or IS050-C51B-C39(manufactured by UJU) Refer to below and next Page table

- Mating Connector : FI-R51HL(JAE) or compatible

Table 4-1. MODULE CONNECTOR(CN1) PIN CONFIGURATION

1

2

3

4

5

6

7

8

9

10 11

12

13

14

15

16

17

18

19

20 21 22

23

24 25 26

NC or GND

NC

LVDS Select

NC

GND

R1AN

R1AP

R1BN

R1BP

R1CN

R1CP

GND

R1CLKN R1CLKP

GND

R1DN

R1DP

R1EN R1EP

NC or GND

DescriptionSymbolNo

No Connection or Ground

No Connection (Note 4)

‘H’ =JEIDA , ‘L’ or NC = VESA

No Connection (Note 4)

No Connection (Note 4) No Connection (Note 4)NC

Ground

FIRST LVDS Receiver Signal (A-)

FIRST LVDS Receiver Signal (A+)

FIRST LVDS Receiver Signal (B-)

FIRST LVDS Receiver Signal (B+)

FIRST LVDS Receiver Signal (C-)

FIRST LVDS Receiver Signal (C+) Ground

FIRST LVDS Receiver Clock Signal(-)

FIRST LVDS Receiver Clock Signal(+) Ground

FIRST LVDS Receiver Signal (D-)

FIRST LVDS Receiver Signal (D+)

FIRST LVDS Receiver Signal (E-) FIRST LVDS Receiver Signal (E+)

No Connection or Ground

No

27

28

29

30

31

32

33

34

35

36

37

38

39 40

41

42

43

44

45

46 47 48

49

50 51

-

Symbol

Bit Select

R2AN

R2AP

R2BN

R2BP

R2CN

R2CP

GND

R2CLKN

R2CLKP

GND

R2DN

R2DP

R2EN

R2EP

NC or GND

GND

NC VLCD

VLCD

VLCD VLCD

-

‘H’ or NC= 10bit(D) , ‘L’ = 8bit

SECOND LVDS Receiver Signal (A-)

SECOND LVDS Receiver Signal (A+)

SECOND LVDS Receiver Signal (B-)

SECOND LVDS Receiver Signal (B+)

SECOND LVDS Receiver Signal (C-)

SECOND LVDS Receiver Signal (C+) Ground

SECOND LVDS Receiver Clock Signal(-)

SECOND LVDS Receiver Clock Signal(+) Ground

SECOND LVDS Receiver Signal (D-)

SECOND LVDS Receiver Signal (D+)

SECOND LVDS Receiver Signal (E-)

SECOND LVDS Receiver Signal (E+)

No Connection or Ground

Ground

Ground No connection Power Supply +12.0V

Power Supply +12.0V

Power Supply +12.0V Power Supply +12.0V

Description

-

Note

1. All GND(ground) pins should be connected together to the LCD module’s metal frame.

2. All VLCD (power input) pins should be connected together.

3. All Input levels of LVDS signals are based on the EIA 644 Standard.

4. #1~#6 & #8~#10 NC (No Connection): These pins are used only for LGD (Do not connect)

5. LVDS pin (pin No. #24,25,40,41) are used for 10Bit(D) of the LCD module. If used for 8Bit(R), these pins are no connection.

6. Specific pin No. #44 is used for “No signal detection” of system signal interface. It should be GND for NSB(No Signal Black) during the system interface signal is not. If this pin is “H”, LCD Module displays AGP(Auto Generation Pattern).

Ver. 0.0

8 / 43

LC470EUF

Product Specification

- LCD Connector (CN2) : FI-RE41S-HF (manufactured by JAE) or IS050-C41B-C39(manufactured by UJU)

- Mating Connector : FI-RE41HL or compatible

Table 4-2. MODULE CONNECTOR(CN2) PIN CONFIGURATION

10

11

12

14

15

16

17

19

20

21

DescriptionSymbolNo

NC

2

3

5

6

7

8

9

NC

NC4 NC

NC

GND

RA3N

RA3P

RB3N

RB3P13

RC3N

RC3P

GND

RCLK3N

RCLK3P18

GND

RD3N

RD3P

No connection1

No connection

No connection No connection

No connection

No connection Ground

THIRD LVDS Receiver Signal (A-)

THIRD LVDS Receiver Signal (A+)

THIRD LVDS Receiver Signal (B-)

THIRD LVDS Receiver Signal (B+)

THIRD LVDS Receiver Signal (C-)

THIRD LVDS Receiver Signal (C+) Ground

THIRD LVDS Receiver Clock Signal(-)

THIRD LVDS Receiver Clock Signal(+) Ground

THIRD LVDS Receiver Signal (D-)

THIRD LVDS Receiver Signal (D+)

No

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

Symbol

RE3N

RE3P

GND

RA4N

RA4P

RB4N

RB4P

RC4N

RC4P

GND

RCLK4N

RCLK4P

GND

RD4N

RD4P

RE4N

RE4P

GND

-

THIRD LVDS Receiver Signal (E-)

THIRD LVDS Receiver Signal (E+)

Ground

Ground FORTH LVDS Receiver Signal (A-)

FORTH LVDS Receiver Signal (A+)

FORTH LVDS Receiver Signal (B-)

FORTH LVDS Receiver Signal (B+)

FORTH LVDS Receiver Signal (C-)

FORTH LVDS Receiver Signal (C+) Ground

FORTH LVDS Receiver Clock Signal(-)

FORTH LVDS Receiver Clock Signal(+) Ground

FORTH LVDS Receiver Signal (D-)

FORTH LVDS Receiver Signal (D+)

FORTH LVDS Receiver Signal (E-)

FORTH LVDS Receiver Signal (E+)

Ground

Description

Note : 1. All GND(ground) pins should be connected together to the LCD module’s metal frame.

2. LVDS pin (pin No. #22,23,38,39) are used for 10Bit(D) of the LCD module. If used for 8Bit(R), these pins are no connection.

CN3

#1

#8

CN3

#1 #8

CN1 CN2

#1

CN1 CN2

#1 #51

#51 #1 #41

#1 #41

Rear view of LCM

Ver. 0.0

9 / 43

3-2-2. Backlight Module

LC470EUF

Product Specification

[ CN201 ]

1) LED Array assy Connector (Plug)

: 20022HS-13B2(BK) (manufactured by Yeonho)

2) Mating Connector (Receptacle)

: 20022WR-13BD (manufactured by Yeonho) or equivalent

[ CN202 ]

1) LED Array assy Connector (Plug)

: 20022HS-12B2 (manufactured by Yeonho)

2) Mating Connector (Receptacle)

: 20022WR-12BD (manufactured by Yeonho )or equivalent

Table 5. BACKLIGHT CONNECTOR PIN CONFIGURATION(CN201,CN202)

No Symbol

1

2

3

4

5

6

7

8

9

10

11

12

13

Anode_L1

(1~4Cathode)

N.C

L1 Cathode

L2 Cathode

L3 Cathode

L4 Cathode

N.C

L5 Cathode

L6 Cathode

L7 Cathode

L8 Cathode

N.C

Anode_L2

(5~8Cathode)

Description

LED Input Current

Open

LED Output Current

Open

LED Output Current

Open

LED Input Current

Note

No Symbol

1

2

3

4

5

6

7

8

9

10

11

12

Anode_R2

(5~8Cathode)

N.C

R8Cathode

R7 Cathode

R6 Cathode

R5 Cathode

R4 Cathode

R3 Cathode

R2 Cathode

R1 Cathode

N.C

Anode_R1

(1~4Cathode)

Description

LED Input Current

Open

LED Output Current

Open

LED Input Current

Note

◆ Rear view of LCM

L8

L7

L6

L5

L4

L3

L3L4

L3

L2

L1

Ver. 0.0

13pin 12pin

1

CN202CN201

T-con

R8

1

R8

R7

R6

R5

R4

R3

R2

R1

10 / 43

LC470EUF

Product Specification

3-3. Signal Timing Specifications

Table 6 shows the signal timing required at the input of the LVDS transmitter. All of the interface signal timings should be satisfied with the following specification for normal operation.

Table 6. TIMING TABLE (DE Only Mode)

Symbol

Display

Period

Horizontal

Vertical 1Lines

Frequency

Blank

Total

Display

Period

DCLK

Horizontal

Vertical

tHV

tHB

tHP

tVBBlank

tVPTotal

fCLK

fH

fV

20

(228)

1100

(1308)

108 (95)

45

(270)

1125

(1350)

120

(100)

86

(300)

1166

(1380)

122

(104)

tCLK680550520

Lines108010801080tVV

Lines

NoteUnitMaxTypMinITEM

1920 / 4tCLK480480480

1tCLK2007040

NoteUnitMaxTypMinSymbolITEM

MHz78.0074.2566.97

2KHz140135121.8

2

NTSC :

Hz

108~122Hz

(PAL : 95~104Hz)

Note: 1. The input of HSYNC & VSYNC signal does not have an effect on normal operation (DE Only Mode).

If you use spread spectrum of EMI, add some additional clock to minimum value for clock margin.

2. The performance of the electro-optical characteristics may be influenced by variance of the vertical refresh rate and the horizontal frequency

※ Timing should be set based on clock frequency.

Ver. 0.0

11 / 43

3-4. LVDS Signal Specification

3-4-1. LVDS Input Signal Timing Diagram

LC470EUF

Product Specification

DCLK

First data

Second data

Third data

Forth data

DE(Data Enable)

tCLK

0.5 VDD

Invalid data

DE, Data

Valid data

Pixel 0

Valid data

Pixel 1

Valid data

Pixel 2

Valid data

Pixel 3

Pixel 4

Pixel 5

Pixel 6

Pixel 7

0.7VDD

0.3VDD

Invalid data

DE(Data Enable)

Ver. 0.0

* tHB = tHFP + tWH +tHBP

* tVB = tVFP + tWV +tVBP

1 1080

tVV

tVP

12 / 43

3-4-2. LVDS Input Signal Characteristics

1) DC Specification

LVDS -

LVDS +

LC470EUF

Product Specification

0V

LVDS Common mode Voltage

LVDS Input Voltage Range

2) AC Specification

LVDS Clock

LVDS Data

LVDS 1’st Clock

LVDS 2nd/ 3rd/ 4thClock

t

SKEW_mintSKEW_max

# VCM= {(LVDS +) + ( LVDS - )} /2

CM

A

(F

tSKEW

clk

T

clk

IN

= 1/T

V

CM

V

IN _ MAXVIN _MIN

NoteUnitMaxMinSymbolDescription

-V1.51.0V

-V1.80.7V

-mV250ΔVCMChange in common mode Voltage

T

clk

)

clk

A

80%

20%

t

RF

NoteUnitMaxMinSymbolDescription

LVDS Differential Voltage

High Threshold

Low Threshold

LVDS Clock to Data Skew Margin

LVDS Clock/DATA Rising/Falling time

Effective time of LVDS

LVDS Clock to Clock Skew Margin (Even to Odd)

Note

1. All Input levels of LVDS signals are based on the EIA 644 Standard.

2. If tRFisn’t enough, t

should be meet the range.

eff

3. LVDS Differential Voltage is defined within t

Ver. 0.0

TH

TL

SKEW

RF

eff

t

SKEW_EO

260 ps(0.3*T

eff

1/7* T

clk

mV300100V

3

mV-100-300V

)/7|t

)/7t

-ps|(0.25*T

2

-psl±360lt

T

clk

-

13 / 43

LG Display LC470EUF-SDC6 Specification

Specifications and Main Features

Frequently Asked Questions

User Manual

CONTENTS

RECORD OF REVISIONS

3. Electrical Specifications