The LC420WUN is a Color Active Matrix Liquid Crystal Display with an integral External Electrode Fluorescent
Lamp(EEFL) backlight system. The matrix employs a-Si Thin Film Transistor as the active element.
It is a transmissive display type which is operating in the normally black mode. It has a 42.02 inch diagonally
measured active display area with WUXGA resolution (1080 vertical by 1920 horizontal pixel array).
Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arrayed in vertical stripes.
Gray scale or the luminance of the sub-pixel color is determined with a 10-bit gray scale signal for each dot.
Therefore, it can present a palette of more than 1.06Bilion (FRC) colors.
It has been designed to apply the 10-bit 2-port LVDS interface.
It is intended to support LCD TV, PCTV where high brightness, super wide viewing angle, high color gamut,
high color depth and fast response time are important.
Total 147.8 W (typ.) (Logic=7.8W, Inverter=140W ) Power Consumption
9.1 Kg (Typ.) Weight
Transmissive mode, Normally blackDisplay Mode
Hard coating(3H), Anti-glare treatment of the front polarizer (Haze 10%)Surface Treatment
4 /37
LC420WUN
Product Specification
2. Absolute Maximum Ratings
The following items are maximum values which, if exceeded, may cause faulty operation or damage to the
LCD module.
Table 1. ABSOLUTE MAXIMUM RATINGS
ParameterSymbol
Power Input Voltage
Inverter Control Voltage
T-Con Option Selection VoltageVLOGIC-0.3+4.0VDC
T-Con LVDS Input VoltageVLVDS-0.3+3.6V
Operating TemperatureTOP0+50°C
Storage TemperatureTST-20+65°C
Panel Front Temperature TSUR-+68°C4
Operating Ambient HumidityHOP1090%RH
Storage HumidityHST1090%RH
Note
1. Ambient temperature condition (Ta = 25 ± 2 °C )
LCD CircuitVLCD-0.3+14.0VDC
InverterVBL-0.3+ 27.0VDC
ON/OFFVOFF / VON-0.3+5.5VDC
BrightnessVBR0.0+5.0VDC
Value
UnitNote
MinMax
2. Temperature and relative humidity range are shown in the figure below.
Wet bulb temperature should be Max 39°C, and no condensation of water.
3. Gravity mura can be guaranteed below 40°C condition.
4. The maximum operating temperatures is based on the test condition that the surface temperature
of display area is less than or equal to 68°C with LCD module alone in a temperature controlled chamber.
Thermal management should be considered in final product design to prevent the surface temperature of
display area from being over 68℃. The range of operating temperature may degraded in case of
improper thermal management in final product design.
90%
1
2,3
2,3
Ver. 1. 2
Wet Bulb
Temperature [C]
10
0
10203040506070800-20
Dry Bulb Temperature [C]
20
30
40
50
60
60%
40%
10%
Storage
Operation
Humidity
[(%)RH]
5 /37
LC420WUN
Product Specification
3. Electrical Specifications
3-1. Electrical Characteristics
It requires two power inputs. One is employed to power for the LCD circuit. The other Is used for the EEFL
backlight and inverter circuit.
Table 2. ELECTRICAL CHARACTERISTICS
ParameterSymbol
Circuit :
ILCDPower Input Current
Note
1. The specified current and power consumption are under the V
Value
MaxTypMin
=12.0V, Ta=25 ± 2°C, fV=60Hz
LCD
condition whereas mosaic pattern(8 x 6) is displayed and fVis the frame frequency.
2. The current is specified at the maximum current pattern.
3. The duration of rush current is about 2ms and rising time of power input is 0.5ms (min.).
White : 1023 Gray
Black : 0 Gray
NoteUnit
VDC13.212.010.8VLCDPower Input Voltage
1mA845650455
2mA1242955668
1Watt7.8PLCDPower Consumption
3A5.0--IRUSHRush current
Ver. 1. 2
Mosaic Pattern(8 x 6)
6 /37
Product Specification
Table 3. ELECTRICAL CHARACTERISTICS (Continue)
LC420WUN
ParameterSymbol
Inverter :
Power Supply Input VoltageVBL22.824.025.2VDC1
Power Supply
Input Current
Power Supply Input Current (In-Rush)IRUSH--11A
Power ConsumptionPBL-
Input Voltage for
Control System
Signals
Lamp:
Lamp Voltage
Lamp Current
After AgingIBL_A-5.8
Before AgingIBL_B-7.0
On/Off
Brightness AdjustEXTVBR-B20-100%
PWM Frequency for
NTSC & PAL
Pulse Duty
Level (PWM)
(Burst mode)
OnVON2.5-5.0VDC
OffVOFF-0.30.00.8VDC
PAL100Hz5
NTSC120Hz5
High Level2.5-5.0VDC
Low Level0.0-0.8VDC
VOUT
IOUT
MinTypMax
90010501200VRMS
126136146mARMS
Values
140160
6.7
7.5
UnitNote
A1
A2
VBL = 22.8V
EXTVBR-B = 100%
W1
On Duty
High: Lamp on
Low : Lamp off
EXTVBR-B =100%
EXTVBR-B =100%
6
7
1
1
Discharge Stabilization TimeTs
Life Time50,00060,000Hrs4
1. Electrical characteristics are determined after the unit has been ‘ON’ and stable for approximately 120
Note
3min3
minutes at 25±2°C. The specified current and power consumption are under the typical supply Input voltage
24Vand VBR (EXTVBR-B : 100%), it is total power consumption.
2. Electrical characteristics are determined within 30 minutes at 25±2°C.
The specified currents are under the typical supply Input voltage 24V.
3. The brightness of the lamp after lighted for 5minutes is defined as 100%.
Ts is the time required for the brightness of the center of the lamp to be not less than 95% at typical current.
The screen of LCD module may be partially dark by the time the brightness of lamp is stable after turn on.
4. Specified Values are for a single lamp which is aligned horizontally.
The life time is determined as the time which luminance of the lamp is 50% compared to that of initial value
at the typical lamp current (EXTVBR-B :100%), on condition of continuous operating at 25± 2°C
5. LGD recommend that the PWM freq. is synchronized with Two times harmonic of Vsync signal of system.
6. The duration of rush current is about 10ms.
7. EXTVBR-B is based on input PWM duty of the inverter.
Ver. 1. 2
7 /37
LC420WUN
Product Specification
3-2. Interface Connections
This LCD module employs two kinds of interface connection, 51-pin connector is used for the module
electronics and 14/12-pin connector is used for the integral backlight system.
3-2-1. LCD Module
-LCD Connector (CN1) : FI-R51S-HF(manufactured by JAE)
Refer to below table.
- Mating Connector : FI-R51HL(JAE) or compatible
Table 4. MODULE CONNECTOR(CN1) PIN CONFIGURATION
NoSymbolDescriptionNoSymbolDescription
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
GNDGround
NCNo Connection
NCNo Connection
NCNo Connection (Reserved for LGD)
NCNo Connection (Reserved for LGD)
NCNo Connection (Reserved for LGD)
LVDS Select
NCNo Connection
NCNo Connection
NCNo Connection
GND
R1AN
R1AP
R1BN
R1BP
R1CN
R1CP
GND
R1CLKN
R1CLKP
GND
R1DN
R1DP
R1EN
R1EP
NC
‘H’ =JEIDA , ‘L’ or NC = VESA
Ground
FIRST LVDS Receiver Signal (A-)
FIRST LVDS Receiver Signal (A+)
FIRST LVDS Receiver Signal (B-)
FIRST LVDS Receiver Signal (B+)
FIRST LVDS Receiver Signal (C-)
FIRST LVDS Receiver Signal (C+)
Ground
FIRST LVDS Receiver Clock Signal(-)
FIRST LVDS Receiver Clock Signal(+)
Ground
FIRST LVDS Receiver Signal (D-)
FIRST LVDS Receiver Signal (D+)
FIRST LVDS Receiver Signal (E-)
FIRST LVDS Receiver Signal (E+)
No Connection
27
Bit Select
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
---
R2AN
R2AP
R2BN
R2BP
R2CN
R2CP
GND
R2CLKN
R2CLKP
GND
R2DN
R2DP
R2EN
R2EP
NC
NC
GNDGround
GNDGround
GNDGround
NCNo connection
VLCDPower Supply +12.0V
VLCDPower Supply +12.0V
VLCDPower Supply +12.0V
VLCDPower Supply +12.0V
‘H’ or NC= 10bit(D) , ‘L’ = 8bit
SECOND LVDS Receiver Signal (A-)
SECOND LVDS Receiver Signal (A+)
SECOND LVDS Receiver Signal (B-)
SECOND LVDS Receiver Signal (B+)
SECOND LVDS Receiver Signal (C-)
SECOND LVDS Receiver Signal (C+)
Ground
SECOND LVDS Receiver Clock Signal(-)
SECOND LVDS Receiver Clock Signal(+)
Ground
SECOND LVDS Receiver Signal (D-)
SECOND LVDS Receiver Signal (D+)
SECOND LVDS Receiver Signal (E-)
SECOND LVDS Receiver Signal (E+)
No Connection
No Connection
Note
Ver. 1. 2
1. All GND(ground) pins should be connected together to the LCD module’s metal frame.
2. All VLCD (power input) pins should be connected together.
3. All Input levels of LVDS signals are based on the EIA 644 Standard.
4. Specific pins(pin No. #2~#6) are used for internal data process of the LCD module.
These pins should be no connection.
5. LVDS pin (pin No. #24,25,40,41) are used for 10Bit(D) of the LCD module.
If used for 8Bit(R), these pins are no connection.
6. Specific pin No. #44 is used for “No signal detection” of system signal interface.
It should be GND for NSB(No Signal Black) during the system interface signal is not.
If this pin is “H”, LCD Module displays AGP(Auto Generation Pattern).
8 /37
3-2-2. Backlight Module
LC420WUN
Product Specification
[ Master ]
-Inverter Connector : S14B-PH-SM4(JST)
- Mating Connector : PHR-14
[ Slave ]
-Inverter Connector : S12B-PH-SM3(JST)
-Mating Connector : PHR-12
Table 5. INVERTER CONNECTOR PIN CONFIGULATION
Pin NoSymbolDescriptionMasterSlaveNote
1
2
3
4
5
6
7
8
9
10
11
VBLPower Supply +24.0VVBLVBL
VBLPower Supply +24.0VVBLVBL
VBLPower Supply +24.0VVBLVBL
VBLPower Supply +24.0VVBLVBL
VBLPower Supply +24.0VVBLVBL
GNDBacklight GroundGNDGND
GNDBacklight GroundGNDGND
GNDBacklight GroundGNDGND
GNDBacklight GroundGNDGND
GNDBacklight GroundGNDGND
NCNo ConnectionNCNC
1
12
13
V
EXTVBR-BExternal PWMEXTVBR-B-3
14
Note
1. GND should be connected to the LCD module’s metal frame.
2. Normal : Low (under 0.7V) / Abnormal : High (upper 3.0V)
Please see Appendix IV-1 for more information.
3. The impedance of pin #12 is over 50[KΩ] & the impedance of Pin #13 is over 100[KΩ].
◆◆◆◆ Rear view of LCM
◆◆◆◆ Rear view of LCM
Ver. 1. 2
ON/OFF
StatusLamp StatusStatus-2
Backlight ON/OFF controlV
PCB
14
…
…
ON/OFF
1
Don’t care3
PCB
…
…
1
<Master>
12
<Slave>
9 /37
LC420WUN
Product Specification
3-3. Signal Timing Specifications
Table 6 shows the signal timing required at the input of the LVDS transmitter. All of the interface signal
timings should be satisfied with the following specification for normal operation.
Table 6-1. TIMING TABLE for NTSC (DE Only Mode)
Symbol
Display Period
Horizontal
VerticaltHP694511tVBBlank
Frequency
Blank
Total
DCLK
Horizontal
Vertical
tHV
tHB
tHP
fCLK
fH
fV
Table 6-2. TIMING TABLE for PAL (DE Only Mode)
Symbol
Display Period
tHV
NoteUnitMaxTypMinITEM
tclk-960-
tclk240140100
2200/2tclk120011001060
tHP-1080-tVVDisplay Period
tHP114911251091tVPTotal
148.5/2MHz7774.2570
KHz7067.565
Hz636057
NoteUnitMaxTypMinITEM
tclk-960-
Horizontal
VerticaltHP348270228tVBBlank
Frequency
Note
The Input of HSYNC & VSYNC signal does not have an effect on normal operation(DE Only Mode).
The performance of the electro-optical characteristics may be influenced by variance of the vertical
refresh rate.
Ver. 1. 2
Blank
Total
DCLK
Horizontal
Vertical
tHB
tHP
fCLK
fH
fV
tclk240140100
2200/2tclk120011001060
tHP-1080-tVVDisplay Period
tHP142813501308tVPTotal
148.5/2MHz7774.2570
KHz7067.565
Hz535047
10 /37
3-4. LVDS Signal Specification
3-4-1. LVDS Input Signal Timing Diagram
LC420WUN
Product Specification
DE, Data
DCLK
First data
Second data
0.7VDD
0.3VDD
tCLK
DE(Data Enable)
0.5 VDD
Invalid data
Invalid data
Valid data
Pixel 0,0
Valid data
Pixel 1,0
tHP
Pixel 2,0
Pixel 3,0
Invalid data
Invalid data
tHV
DE(Data Enable)
Ver. 1. 2
11080
tVV
tVP
11 /37
3-4-2. LVDS Input Signal Characteristics
1) DC Specification
LVDS -
LVDS +
LC420WUN
Product Specification
0V
LVDS Common mode Voltage
LVDS Input Voltage Range
2) AC Specification
LVDS Clock
LVDS Data
LVDS 1’st Clock
LVDS 2nd/ 3rd/ 4thClock
t
SKEW_mintSKEW_max
# VCM= {(LVDS +) + ( LVDS - )} /2
CM
A
(F
tSKEW
tSKEW
clk
T
clk
IN
= 1/T
V
CM
V
IN _ MAXVIN _MIN
NoteUnitMaxMinSymbolDescription
-V1.51.0V
-V1.80.7V
-mV250ΔVCMChange in common mode Voltage
T
clk
)
clk
A
80%
20%
t
RF
LVDS Differential Voltage
High Threshold
Low Threshold
LVDS Clock to Data Skew Margin
LVDS Clock/DATA Rising/Falling time
Effective time of LVDS
LVDS Clock to Clock Skew Margin (Even to Odd)
1. All Input levels of LVDS signals are based on the EIA 644 Standard.
Note
2. If tRFisn’t enough, t
should be meet the range.
eff
3. LVDS Differential Voltage is defined within t
TH
TL
SKEW
RF
eff
t
SKEW_EO
260ps(0.3*T
eff
Ver. 1. 2
1/7* T
NoteUnitMaxMinSymbolDescription
mV300100V
3
mV-100-300V
)/7|t
clk
)/7t
clk
-ps|(0.25*T
2
-ps±360t
T
clk
clk
-
12 /37
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